CN106409760A - 半导体器件和封装半导体管芯的方法 - Google Patents

半导体器件和封装半导体管芯的方法 Download PDF

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CN106409760A
CN106409760A CN201610402516.8A CN201610402516A CN106409760A CN 106409760 A CN106409760 A CN 106409760A CN 201610402516 A CN201610402516 A CN 201610402516A CN 106409760 A CN106409760 A CN 106409760A
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semiconductor
semiconductor element
semiconductor wafer
groove
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CN106409760B (zh
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S.金努萨米
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Abstract

本发明涉及半导体器件和封装半导体管芯的方法。半导体器件具有半导体晶片。半导体晶片包括多个半导体管芯。绝缘层形成在半导体管芯的有源表面之上。沟槽形成在半导体管芯之间的半导体晶片的非有源区域中。沟槽部分地延伸通过半导体晶片。提供具有粘合层的载体。同时作为单个单元而将半导体管芯设置在粘合层和载体之上。执行背面研磨操作以去除半导体晶片的部分并且暴露沟槽。粘合层在背面研磨操作期间将半导体管芯保持在适当位置。将密封剂沉积在半导体管芯之上以及沉积到沟槽中。去除载体和粘合层。对经封装的半导体管芯清洗并且将经封装的半导体管芯单体化成个体半导体器件。测试半导体器件的电气性能和功能性。

Description

半导体器件和封装半导体管芯的方法
技术领域
本发明大体涉及半导体器件，并且更具体地涉及半导体器件和封装半导体管芯的方法。
背景技术
通常在现代电子产品中找到半导体器件。半导体器件在电气部件的数目和密度方面变化。分立半导体器件一般包含一种类型的电气部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含数百个到数百万个电气部件。集成半导体器件的示例包括微控制器、微处理器和各种信号处理电路。
半导体器件执行各种各样的功能，诸如信号处理、高速计算、传送和接收电磁信号、控制电子器件、将阳光转变成电力、以及创建用于电视显示器的视觉图像。在娱乐、通信、功率转换、网络、计算机和消费者产品的领域中找到半导体器件。还在军事应用、航空、机动车、工业控制器和办公设备中找到半导体器件。
半导体器件采用半导体材料的电气性质。半导体材料的结构允许由电场或基电流的施加或者通过掺杂过程来操纵材料的电气传导性。掺杂向半导体材料中引入杂质以操纵和控制半导体器件的传导性。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平以及电场或基电流的施加，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构创建执行各种电气功能所必要的电压与电流之间的关系。无源和有源结构电气连接以形成电路，其使得半导体器件能够执行高速操作和其它有用功能。
一般使用两个复杂的制造过程即前端制造和后端制造（每一个潜在地涉及数百个步骤）来制造半导体器件。前端制造涉及在半导体晶片的表面上形成多个管芯。每一个半导体管芯典型地相同并且包含通过电气连接有源和无源部件所形成的电路。后端制造涉及从成品（finished）晶片单体化（singulate）个体半导体管芯并且封装管芯以提供结构支撑、电气互连和环境隔离。如本文中所使用的术语“半导体管芯”是词语的指单数和复数形式二者，并且因而可以是指单个半导体器件和多个半导体器件二者。
半导体制造的一个目标是生产更小的半导体器件。更小的器件典型地消耗更少的功率，具有更高的性能，并且可以被更高效地生产。此外，更小的半导体器件具有更小的占用面积（footprint），其对于更小的最终产品而言是所期望的。更小的半导体管芯尺寸可以通过前端过程中的改进而被实现，从而导致具有更小、更高密度的有源和无源部件的半导体管芯。后端过程通过电气互连和封装材料中的改进而可以导致具有更小占用面积的半导体器件封装。
半导体管芯可能经受损坏或退化，如果半导体管芯的部分暴露于外部元件的话。例如，半导体管芯可能在处置期间或者由于暴露于光而受损或退化。因而，半导体管芯被典型地围起在密封剂内以用于管芯的电气隔离、结构支撑和环境保护。将半导体管芯封装可以通过将半导体晶片单体化成个体半导体管芯，将半导体管芯单独地安装到载体，以及然后将密封剂沉积在半导体之上来执行。然而，安装个体半导体管芯增加制造时间，这降低生产量。个体即经单体化的半导体管芯还是易碎的并且可能在附着到载体期间受损。另外，将个体半导体管芯安装到载体可能增加半导体管芯之间的距离和半导体管芯周围的密封剂量，这引起最终封装尺寸的增加。
发明内容
存在封装半导体管芯而同时增加生产量并减小封装尺寸的需要。因而，在一个实施例中，本发明是一种制作半导体器件的方法，包括以下步骤：提供包括多个半导体管芯的半导体晶片；在半导体管芯之间并且部分地通过半导体晶片形成沟槽；将半导体管芯设置在载体之上；去除半导体晶片的第一部分；以及将密封剂沉积在半导体管芯之上以及沉积到沟槽中。
在另一实施例中，本发明是一种制作半导体器件的方法，包括以下步骤：提供包括多个半导体管芯的半导体晶片；在半导体管芯之间形成沟槽；将半导体管芯设置在载体之上；以及将密封剂沉积到沟槽中。
在另一实施例中，本发明是制作半导体器件的方法，包括以下步骤：提供多个半导体管芯；在半导体管芯之间形成沟槽；以及将密封剂沉积到沟槽中。
在另一实施例中，本发明是包括载体的半导体器件。半导体晶片被设置在载体之上并且包括由沟槽分离的多个半导体管芯。
附图说明
图1a-1m图示了封装半导体管芯的方法；以及
图2图示了经封装的半导体管芯。
具体实施方式
在参照附图的以下描述中的一个或多个实施例中描述本发明，其中相同标号表示相同或相似的元件。尽管根据用于实现本发明的目的的最佳模式描述了本发明，但是本领域技术人员将领会到，公开内容意图覆盖如可以被包括在如由随附权利要求和权利要求等同物所限定的本发明的精神和范围内的可替换、修改和等同物，如由以下公开内容和附图所支持的随附权利要求和权利要求等同物。
半导体器件一般使用以下两个复杂的制造过程来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每一个管芯包含有源和无源电气部件，其电气连接以形成功能电气电路。有源电气部件（诸如晶体管和二极管）具有控制电流的流动的能力。无源电气部件（诸如电容器、电感器和电阻器）创建执行电气电路功能所必要的电压与电流之间的关系。
无源和有源部件通过一系列过程步骤（包括掺杂、沉积、光刻、蚀刻和平面化）而形成在半导体晶片的表面之上。掺杂通过诸如离子注入或热扩展之类的技术而向半导体材料中引入杂质。掺杂过程通过响应于电场或基电流动态地改变半导体材料传导性来修改有源器件中的半导体材料的电气传导性。晶体管包含变化类型和程度的掺杂的区，其如使得晶体管能够在施加电场或基电流时促进或限制电流的流动所必要的那样进行布置。
有源和无源部件通过具有不同电气性质的材料的层而形成。层可以通过部分地由所沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可以涉及化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀以及无电电镀过程。每一个层一般被图案化以形成以下的部分：有源部件、无源部件或者部件之间的电气连接。
后端制造是指将成品晶片切割或单体化成个体半导体管芯并且封装半导体管芯以用于结构支撑、电气互连和环境隔离。为了单体化半导体管芯，沿着称为锯切道（saw street）或划线的晶片的非功能区刻划和断开晶片。使用激光切割工具或锯片来单体化晶片。在单体化之后，将个体半导体管芯安装到封装衬底，其包括引脚或接触垫以用于与其它系统部件互连。形成在半导体管芯之上的接触垫然后连接到封装内的接触垫。可以利用传导层、凸块、柱状凸块、导电膏或引线接合做出电气连接。密封剂或其它模制材料被沉积在封装之上以提供物理支撑和电气隔离。成品封装然后被插入到电气系统中并且使半导体器件的功能性可用于其它系统部件。
图1a示出具有诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或者用于结构支撑的其它块状半导体材料之类的基底衬底材料102的半导体晶片100。通过如上文所述的非有源、管芯间晶片区域或锯切道106分离的多个半导体管芯或部件104形成在晶片100上。锯切道106提供切割区域以将半导体晶片100单体化成个体半导体管芯104。
图1b示出半导体晶片100的部分的横截面视图。每一个半导体管芯104具有背部或非有源表面108以及有源表面110，其包含被实现为形成在管芯内并且根据管芯的电气设计和功能而电气互连的有源器件、无源器件、传导层和电介质层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管、以及形成在有源表面110内的其它电路元件，以实现模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、MEMS、存储器或者其它信号处理电路。半导体管芯104还可以包含集成无源器件（IPD），诸如电感器、电容器和电阻器，以用于射频（RF）信号处理。
电气传导层112使用PVD、CVD、电解电镀、无电电镀过程或者其它适当的金属沉积过程而形成在有源表面110之上。传导层112包括下述各项的一个或多个层：铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）、钯（Pd）、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu、或者其它适当的电气传导材料或者其组合。传导层112作为电气连接到有源表面110上的电路的接触垫而操作。接触垫112促进半导体管芯104内的有源电路与外部器件例如印刷电路板（PCB）之间的电气互连。
绝缘或钝化层114使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或者热学氧化而形成在有源表面110之上以及接触垫112周围。绝缘层114包含下述各项的一个或多个层：二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、氧化铪（HfO2）、苯并环丁烯（BCB）、聚酰亚胺（PI）、聚苯并恶唑（PBO）、聚合物、阻焊剂、或者具有类似绝缘和结构性质的其它材料。绝缘层114覆盖有源表面110并且提供针对有源表面110的保护。绝缘层114围绕接触垫112并且提供电气隔离。将接触垫112的部分从绝缘层114暴露以允许到半导体管芯104的随后电气连接。
在图1c中，使用切割工具118在晶片100中形成多个沟槽或开口116。在一个实施例中，使用深反应离子蚀刻（DRIE）来形成沟槽116。沟槽116还可以使用激光直接烧蚀（LDA）、机械钻孔、等离子体蚀刻或者其它适当的过程而形成。沟槽116形成在锯切道106中的半导体管芯104之间。沟槽116形成为围绕半导体管芯104周围的外围区中的半导体管芯104。沟槽116通过绝缘层114和基底衬底材料102而形成。沟槽116仅部分地延伸通过半导体晶片100使得基底衬底材料102的部分剩余在半导体晶片100的表面108与沟槽116的底部表面119之间。半导体管芯104保持通过锯切道106中所剩余（即在表面119与表面108之间）的基底衬底材料102的部分而连接到彼此。
图1d示出包含牺牲基底衬底材料，诸如硅、聚合物、氧化铍、玻璃、或者用于结构支撑的其它适当的低成本刚性材料的载体或临时衬底120的部分的横截面视图。粘合层122形成在载体120之上作为临时结合膜、蚀刻停止层、热释放层或者UV释放层。在一个实施例中，粘合层122是附着到载体120的表面的双面胶。可替换地，粘合层122可以使用旋涂、层压、锡膏印刷或者其它适当的施加过程而形成在载体120的表面上。
将半导体晶片100设置在粘合层122和载体120之上，其中半导体管芯104的有源表面110和沟槽116朝向载体取向。半导体管芯104通过半导体管芯104之间所剩余的部分锯切道106而被连接或保持在一起。半导体管芯104之间所剩余的锯切道106的部分允许晶片100的半导体管芯104作为单个单元被安装。作为单个单元将半导体管芯104设置在载体120之上允许在单个步骤中同时安装半导体管芯104。
图1e示出设置在粘合层122和载体120上的半导体管芯104。在将半导体晶片100安装到载体120之后，表面108经受使用研磨机124的背面研磨操作。背面研磨操作从表面108去除基底衬底材料102的部分并且暴露沟槽116。背面研磨操作去除覆盖沟槽116的锯切道106的部分并且减薄或减小半导体管芯104的厚度。基底衬底材料102从背表面108的去除留下具有新的背表面130的半导体管芯104。可替换地，可以使用LDA、蚀刻、抛光、化学机械平面化（CMP）或者其它适当的去除过程来减薄半导体管芯104并且使沟槽116露出。背面研磨操作单体化半导体管芯104，即在背面研磨之后，半导体管芯104不再通过基底衬底材料102彼此连接。半导体管芯104通过粘合层122在背面研磨期间以及在单体化之后（即在背面研磨之后）保持在适当位置。
图1f示出在背面研磨操作之后的半导体管芯104。半导体管芯104之间的空间由沟槽116创建使得经单体化的半导体管芯104之间的宽度W1等于沟槽116的宽度。
图1g-1j示出单体化半导体管芯104的可替换方法。从图1d继续，图1g示出设置在粘合层122和载体120之上的晶片100，其中沟槽116和半导体管芯104的有源表面110朝向载体取向。半导体管芯104通过晶片100的表面108和沟槽116的表面119之间所剩余的锯切道106的部分而连接。半导体管芯104之间所剩余的锯切道106的部分允许在载体120之上作为单个单元同时安装半导体管芯104。
在图1h中，半导体晶片100的表面108经受背面研磨操作以去除基底衬底材料102的部分。研磨机126从表面108去除基底衬底材料102并且创建新的背表面128。背面研磨操作不暴露沟槽116。在背面研磨操作之后，半导体管芯104保持通过锯切道106中的基底衬底材料102的部分而连接。在一个实施例中，在背面研磨之后，30-40微米的基底衬底材料102剩余在晶片100的新的背表面128和沟槽116的表面119之间。
图1i示出在背面研磨操作之后的晶片100。晶片100的表面128和沟槽116的表面119之间所剩余的基底衬底材料102的部分在背面研磨操作期间支撑并且强化半导体管芯104。连接半导体管芯104的基底衬底材料102的部分减轻放在半导体管芯104上的研磨应力。减小半导体管芯104上的研磨应力减少了半导体管芯104在背面研磨操作期间受损的可能性，这增加了功能半导体管芯104的可靠性和生产量。
连接半导体管芯104的锯切道106的部分还允许沟槽116在研磨操作期间保持被覆盖。使沟槽116未暴露防止研磨碎屑，例如基底衬底材料102的颗粒，落入到沟槽116中。防止研磨碎屑进入沟槽116消除了针对沟槽116的研磨后清洗的需要。消除研磨后清洗过程减少了制造时间和成本。
在图1j中，锯切道106的剩余部分使用等离子体蚀刻、DRIE或者其它适当的蚀刻规程而被去除。从锯切道106去除基底衬底材料102的最终部分暴露沟槽116并且单体化半导体管芯104。用于暴露沟槽116的蚀刻操作还可以去除背表面128的部分以便进一步减薄半导体管芯104。粘合层122既在背面研磨和蚀刻过程期间又在在单体化之后（即在蚀刻之后）将半导体管芯104保持在适当位置。半导体管芯104之间的空间由沟槽116创建使得经单体化的半导体管芯104之间的宽度W1等于沟槽116的宽度。
从图1f继续，图1k示出沉积在半导体管芯104、粘合层122和载体120之上的密封剂或模制化合物132。密封剂132使用丝网印刷、喷涂、锡膏印刷、压缩模制、转移模制、液体密封剂模制、真空层压、旋涂或者其它适当的施加方法而被沉积在半导体管芯104之上以及在半导体管芯104周围。密封剂132覆盖半导体管芯104的四个侧表面和背表面130。密封剂132包括聚合物复合材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或者具有适当填充物的聚合物。密封剂132是非传导的并且在环境上保护半导体器件免受外部元件和污染物的影响。将密封剂132沉积在由沟槽116创建的空间中的半导体管芯104之间。沟槽116允许密封剂132在半导体管芯104的侧表面之上和在半导体管芯104的侧表面周围流动。可以在沉积之后立即固化或者在制造过程中随后固化密封剂132。
在图1l中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烤、UV光、激光扫描或者湿法脱模而去除载体120和粘合层122。去除载体120和粘合层122暴露绝缘层114、接触垫112和密封剂132的表面134。密封剂132的表面134与绝缘层114和接触垫112的表面共面。将半导体管芯104通过密封剂132保持在一起。密封剂132提供结构支撑并且在随后的制造期间保护半导体管芯104。
在去除载体120和粘合层122之后，经封装的半导体管芯104经受表面沾污去除或清洗过程以从绝缘层114、接触垫112和密封剂132的表面134去除任何颗粒或残留物。清洗过程可以包括离心喷射干燥（SRD）过程、等离子体清洗过程、干法清洗过程、湿法清洗过程或者其组合。
在图1m中，将切分带或支撑载体136施加在经封装的半导体管芯104之上。经封装的半导体管芯104然后使用锯片或激光切割工具138而被单体化成个体半导体器件或封装140。切割工具138切穿设置在半导体管芯104之间的密封剂132。切分带136在单体化期间支撑半导体管芯104。在单体化之后，密封剂132剩余在半导体管芯104的四个侧表面之上。
半导体器件140内的有源和无源部件经受针对电气性能和电路功能的测试。测试可以包括电路功能性、引线完整性、电阻性、连续性、可靠性、结深度、静电放电（ESD）、RF性能、驱动电流、阈值电流、漏电流以及特定于部件类型的操作参数。检查和测试使得能够将通过的半导体器件140指定为已知良好的。然后使用例如压纹带卷而卷起已知良好的器件。经卷起的半导体器件140然后被发出以用于另外的处理或者并入到其它电气器件和系统中。
图2示出在单体化之后的半导体器件140。接触垫112电气连接到半导体管芯104的有源表面110上的电路并且促进外部器件（例如PCB）与半导体器件140之间的随后连接。将绝缘层114设置在有源表面110之上以及接触垫112周围以用于保护和电气隔离。将密封剂132设置在半导体管芯104的背表面130和四个侧表面之上。密封剂132提供机械保护、电气隔离以及防止由于暴露给来自光或其它发射的光子所致的退化的保护。密封剂132在环境上保护半导体管芯104免受外部元件和污染物的影响。
半导体器件140的生产量被增加，因为半导体管芯104被设置在载体120之上作为单个晶片或单元。将半导体管芯104设置在载体120之上作为单个单元简化了制造并且消除了针对将半导体管芯104单独地安装于载体的需要。安装半导体管芯104同时减少制造时间，这增大生产量并且降低成本。在半导体管芯仍以晶片形式的同时即在半导体管芯仍通过基底衬底材料102连接的同时安装半导体管芯104强化并且增大半导体管芯104在安装期间的鲁棒性。所连接的半导体管芯得到更多支撑并且因而不太可能在附着到载体120期间受损。粘合层122在背面研磨操作期间将半导体管芯104保持在适当位置。粘合层122还在密封剂132的沉积期间维持半导体管芯104之间的对准和间隔。
以预成型的沟槽116安装所连接的半导体管芯104增大载体120之上的半导体管芯104的对准精度和间隔一致性。密封剂132由于半导体管芯104之间的一致性间隔而可以更均匀地分布在半导体管芯104之上以及在半导体管芯104周围。半导体管芯104之间的一致性间隔以及均匀量的密封剂允许半导体器件140的单体化期间的增大精度。精确的单体化创建统一的半导体器件140并且降低在单体化期间对半导体管芯104损坏的可能性。
经封装的半导体管芯104以小的占用面积制作鲁棒的半导体器件140。当半导体管芯104被安装到载体120时，由于半导体管芯104之间的基底衬底材料102的存在，所以半导体管芯104得到更多支撑并且经受较小应力。在单体化半导体管芯104之后，将密封剂132沉积在半导体管芯104之上以及在半导体管芯104周围以在随后的处置和制造期间保护和支撑半导体管芯104。因而，良好半导体器件140的总体功能性和数目由于半导体管芯104既在制造过程期间又在制造过程之后不太容易受损而增大。
尽管已经详细说明了本发明的一个或多个实施例，但是本领域技术人员将领会到，在不脱离如在所附权利要求中阐述的本发明的范围的情况下，可以做出对那些实施例的修改和适配。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供包括多个半导体管芯的半导体晶片；
在半导体管芯之间并且部分地通过半导体晶片形成沟槽；
在载体之上设置半导体晶片，其中沟槽朝向载体取向；
在载体之上设置半导体晶片之后，去除沟槽之上的半导体晶片的第一部分以单体化半导体管芯；以及
将密封剂沉积在半导体管芯之上以及沉积到沟槽中。
2.权利要求1的方法，还包括在去除半导体晶片的第一部分之前，去除沟槽之上的半导体晶片的第二部分。
3.权利要求2的方法，还包括：
通过背面研磨去除半导体晶片的第二部分；以及
通过蚀刻去除半导体晶片的第一部分。
4.权利要求1的方法，其中去除半导体晶片的第一部分暴露沟槽。
5.权利要求1的方法，还包括在载体之上设置粘合层。
6.权利要求1的方法，还包括：
去除载体；以及
清洗半导体管芯。
7.一种制作半导体器件的方法，包括：
提供包括多个半导体管芯的半导体晶片；
在半导体管芯之间的半导体晶片中形成沟槽；
在载体之上设置半导体晶片；以及
将密封剂沉积到沟槽中。
8.权利要求7的方法，还包括去除半导体晶片的部分以暴露沟槽。
9.权利要求7的方法，还包括去除沟槽之上的半导体晶片的第一部分而同时留下沟槽之上的半导体晶片的第二部分。
10.权利要求9的方法，还包括通过蚀刻去除半导体晶片的第二部分。
11.一种半导体器件，包括：
载体；以及
设置在载体之上的半导体晶片，其中半导体包括通过沟槽分离的多个半导体管芯，其中沟槽朝向载体取向。
12.权利要求11的半导体器件，还包括设置在载体之上的粘合层。
13.权利要求12的半导体器件，其中粘合层包括双面胶。
14.权利要求11的半导体器件，其中半导体管芯的有源表面朝向载体取向。
15.权利要求11的半导体器件，其中沟槽部分地延伸通过半导体晶片。
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