CN106328711A - 鳍式场效应晶体管(FinFET)器件结构及其形成方法 - Google Patents
鳍式场效应晶体管(FinFET)器件结构及其形成方法 Download PDFInfo
- Publication number
- CN106328711A CN106328711A CN201610511247.9A CN201610511247A CN106328711A CN 106328711 A CN106328711 A CN 106328711A CN 201610511247 A CN201610511247 A CN 201610511247A CN 106328711 A CN106328711 A CN 106328711A
- Authority
- CN
- China
- Prior art keywords
- fin
- finfet
- gate electrode
- electrode layer
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 74
- 230000005669 field effect Effects 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims description 46
- 230000002829 reductive effect Effects 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000009467 reduction Effects 0.000 claims description 7
- 230000002441 reversible effect Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 144
- 230000008569 process Effects 0.000 description 29
- 238000005530 etching Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 239000003989 dielectric material Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000000059 patterning Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- MJGARAGQACZIPN-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O--].[O--].[Al+3].[Hf+4] MJGARAGQACZIPN-UHFFFAOYSA-N 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 206010019133 Hangover Diseases 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- VQYPKWOGIPDGPN-UHFFFAOYSA-N [C].[Ta] Chemical compound [C].[Ta] VQYPKWOGIPDGPN-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920000554 ionomer Polymers 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- -1 silicon hydrogen Chemical class 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
提供了一种FinFET器件结构及其形成方法。FinFET器件结构包括:鳍结构,形成在衬底的上方;以及栅极结构,横越在鳍结构上方。栅极结构包括栅电极层,栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,在上部和下部之间形成虚拟界面,并且下部具有从虚拟界面至下部的底面逐渐减小的减小的宽度。本发明实施例涉及鳍式场效应晶体管(FinFET)器件结构及其形成方法。
Description
相关申请的交叉引用
本申请要求于2015年7月2日提交的标题为“fin field effect transistor(FinFET)device structure and method for forming the same”的美国临时专利第62/188,028号的优先权,其全部内容通过引用结合于此。本申请涉及以下共同代决和共同转让的专利申请:于2015年11月16日提交的标题为“Finfield effect transistor(FinFET)device structure and method for forming thesame”的美国第14/942,491号,其全部内容通过引用结合于此(申请人代理卷号P20150483US01)。
技术领域
本发明实施例涉及鳍式场效应晶体管(FinFET)器件结构及其形成方法。
背景技术
半导体器件用于各种电子应用中,诸如个人计算机、手机、数码相机、以及其他电子设备。通过在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导体材料层,和使用光刻图案化各个材料层以在其上形成电路组件和元件来制造半导体器件。通常在单个半导体晶圆上制造许多集成电路,并且通过沿着划线在集成电路之间锯切来分割晶圆上的单独的管芯。例如,通常以多芯片模式或者以其他的封装类型来单独地封装单个管芯。
在半导体器件的制造中,半导体器件的尺寸已经不断降低以增加器件密度。因此,提供了多层互连结构。互连结构可以包括一个或多个导电线和通孔层。
虽然现有的互连结构和制造互连结构的方法通常已经满足于他们的预期目的,但是它们并非在所有方面都尽如人意。
发明内容
根据本发明的一些实施例,提供了一种鳍式场效应晶体管(FinFET)器件结构,包括:鳍结构,形成在衬底上方;以及栅极结构,横越在所述鳍结构上方,其中,所述栅极结构包括栅电极层,所述栅电极层包括位于所述鳍结构之上的上部和位于鳍结构下方的下部,在所述上部和所述下部之间形成有虚拟界面,并且所述下部具有从所述虚拟界面至所述下部的底面逐渐减小的减小的宽度。
根据本发明的另一些实施例,还提供了一种鳍式场效应晶体管(FinFET)器件结构,包括:鳍结构,形成在衬底上方;隔离结构,形成在所述衬底上方,其中,所述鳍结构的部分嵌入在所述隔离结构中;以及第一栅极结构,横越在所述鳍结构上方,其中,第一栅极结构包括第一栅电极层,第一栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,并且所述下部具有倒梯形形状。
根据本发明的又一些实施例,还提供了一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法,包括:在衬底上方形成鳍结构;在所述衬底上方形成隔离结构,其中,所述鳍结构的部分嵌入在所述隔离结构中;以及在所述鳍结构和所述隔离结构上方形成栅极结构,其中,所述栅极结构包括栅电极层,所述栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,并且所述下部具有从虚拟界面至所述下部的底面逐渐减小的减小的宽度,所述虚拟界面形成在所述上部和所述下部之间。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的方面。应该强调的是,根据工业中的标准实践,各个部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意地增大或减小。
图1示出了根据本发明的一些实施例的位于鳍式场效应晶体管(FinFET)器件结构上的互连结构的三维视图。
图2A至图2M示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的各个阶段的截面图示。
图3示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构的顶视图。
图4A至图4F示出了根据一些实施例的形成FinFET器件结构的各个阶段的截面图示。
图4D’示出了根据本发明的一些实施例的图4D的区域A的放大视图。
图5A至图5C示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的截面图示。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。以下将描述组件和布置的具体实例以简化本发明。当然,这些仅仅是实例并且不旨在限制。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和字符。这种重复是为了简化和清楚的目的,并且其本身并不表示所论述多个实施例和/或配置之间的关系。
描述了实施例的一些变化例。在各个视图和示例性实施例中,相同的参考标号用于代表相同的元件。应当理解,可以在该方法之前、期间和之后提供额外的操作,并且对于该方法的其他实施例,可以替换或消除一些操作。
提供了形成鳍式场效应晶体管(FinFET)器件结构的实施例。图1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构100的透视图。
参考图1A,提供了衬底102。该衬底102可以由硅或其他半导体材料制成。可选地或额外地,该衬底102可以包括其他元素半导体材料,诸如锗。在一些实施例中,衬底102是由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成的。在一些实施例中,衬底102是由诸如硅锗、碳化硅锗、磷砷化镓或磷铟化镓的合金半导体制成的。在一些实施例中,衬底102包括外延层。例如,该衬底102具有位于块状半导体上面的外延层。
FinFET器件结构100还包括从衬底102延伸的一个或多个鳍结构104(例如,Si鳍)。鳍结构104可以任选地包括锗。可采用诸如光刻和蚀刻工艺的适当的工艺形成鳍结构104。在一些实施例中,使用干蚀刻或等离子体工艺从衬底102蚀刻鳍结构104。
诸如浅沟槽隔离(STI)结构的隔离结构108形成为围绕鳍结构104。如图1所示,在一些实施例中,鳍结构104的下部由隔离结构108围绕,和鳍结构104的上部从隔离结构108突出。也就是说,隔离结构108的一部分嵌入在隔离结构108中。隔离结构108防止电气干扰或串扰。
FinFET器件结构100还包括栅极堆叠结构,栅极堆叠结构包括栅电极层144和栅极介电层142。栅极堆叠结构形成在鳍结构104的中心部分上方。在一些实施例中,在鳍结构104上方形成多个栅极堆叠结构。在栅极结构中也可以存在多个其他层,例如,覆盖层、界面层、间隔元件和/或其他合适的部件。
栅极介电层142可以包括介电材料,诸如氧化硅、氮化硅、氮氧化硅、具有高介电常数(高k)的介电材料或它们的组合。高k介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金,氧化铪硅,氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆等或它们的组合。
栅电极层144可以包括多晶硅或金属。金属包括氮化钽(TaN),硅化镍(NiSi),硅化钴(CoSi)、钼(Mo)、铜(Cu)、钨(W)、铝(Al)、钴(Co)、锆(Zr),铂(Pt),或其他适用的材料。可以在后栅极工艺(或栅极替换工艺)中形成栅电极层144。在一些实施例中,栅极堆叠结构包括附加层,诸如界面层、覆盖盖层、扩散/阻挡层或其他适用的层。
鳍结构104包括被栅电极层144和栅极介电层142围绕或包裹的沟道区114。可以掺杂鳍结构104以提供用于n型FinFET(NMOS器件)或P型FinFET(PMOS器件)的合适的沟道。可以使用诸如离子注入工艺、扩散工艺、退火工艺、其他适用的工艺或它们的组合的合适的工艺掺杂鳍结构104。鳍结构104包括位于源极区112和漏极区116之间的沟道区114。FinFET器件100可以是包括在微处理器、存储器单元(例如,静态随机存取存储器(SRAM)),和/或其他集成电路中的器件。
图2A至图2M示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面图示。
参考图2A,在衬底102上形成介电层204和硬掩模层206,并且在硬掩模层206上形成光刻胶层208。可以通过图案化工艺图案化光刻胶层208。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺包括光刻胶涂布(例如,旋涂),软烘烤,掩模对准、曝光,曝光后烘烤,显影光刻胶、水洗和干燥(例如,硬烘烤)。该蚀刻工艺包括干蚀刻工艺或湿蚀刻工艺。
介电层204是衬底102和硬掩模层206之间的缓冲层。此外,当去除硬掩模层206时,介电层204用作停止层。介电层204可以由氧化硅制成。硬掩模层206可以由氧化硅、氮化硅、氮氧化硅,或其他适用的材料制成。在一些其他的实施例中,在介电层204上形成一个以上的硬掩模层206。
通过诸如化学汽相沉积(CVD)工艺、高密度等离子体化学汽相沉积(HDPCVD)工艺,旋涂工艺,溅射工艺,或其他适用的工艺的沉积工艺形成介电层204和硬掩模层206。
如图2B所示,根据一些实施例,在图案化光刻胶层208之后,通过使用图案化的光刻胶层208作为掩模来图案化介电层204和硬掩模层206。结果,获得图案化的介电层204和图案化的硬掩模层206。之后,去除图案化的光刻胶层208。
之后,通过将图案化的介电层204和图案化的硬掩模层206用作掩模对衬底102实施蚀刻工艺以形成鳍结构104。该蚀刻工艺可以是干蚀刻工艺或湿蚀刻工艺。蚀刻工艺可以是时间控制的工艺,并持续到鳍结构104达到预定的高度。
应注意的是,鳍结构104的数目可根据实际应用进行调整,且不限于一个鳍结构104。在一些实施例中,鳍结构104具有从顶部到下部的逐渐增大的宽度。
之后,如图2C所示,根据一些实施例,在鳍结构104上形成介电材料107。在一些实施例中,介电材料107是由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG),或其他低k介电材料制成的。可以通过化学汽相沉积(CVD)工艺、旋涂玻璃工艺或另一个适用的工艺沉积介电材料107。
之后,如图2D所示,根据一些实施例,减薄或平坦化介电材料107以形成隔离结构108。在一些实施例中,通过化学机械抛光(CMP)工艺减薄介电材料107。其结果是,鳍结构104的顶部部分被暴露,并且去除了介电层204和硬掩模层206。隔离结构108的顶面与鳍结构104的顶面平齐。
之后,如图2E所示,根据一些实施例,去除隔离结构108的顶部。作为一个结果,鳍结构104从隔离结构108突出。换言之,鳍结构104的顶部高于隔离结构108。通过湿蚀刻工艺或干蚀刻工艺去除隔离结构108的顶部部分。剩下的隔离结构108看做为浅槽隔离(STI)结构。
之后,如图2F所示,根据一些实施例,在鳍结构104和隔离结构108上方形成伪栅电极层110。
在一些实施例中,伪栅电极层110是由导电或非导电材料制成的。在一些实施例中,伪栅电极层110是由多晶硅制成的。通过诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD),高密度等离子体CVD(HDPCVD)、金属有机CVD(MOCVD),或等离子增强CVD(PECVD)的沉积工艺形成伪栅电极层110。
如图2G所示,根据一些实施例,在形成伪栅电极层110之后,在伪栅电极层110上方形成第一硬掩模层212a和第二硬掩模层212b。在第二硬掩模层212b上方形成光刻胶层214。之后,图案化光刻胶层214以形成图案化的光刻胶层214。图案化的光刻胶层214用于在随后的工艺中保护下面的层不被蚀刻。
之后,如图2H所示,根据一些实施例,图案化第一硬掩模层212a和第二硬掩模层212b,去除伪栅电极层110的一部分以形成伪栅极结构110’。通过诸如湿蚀刻工艺或干蚀刻工艺的蚀刻工艺121去除伪栅电极层110的部分。
伪栅极结构110’包括位于鳍结构104的顶面之上的上部110a和位于鳍结构104的顶面下方的下部110b。上部110a具有基本上垂直侧侧壁并且下部110b具有倾斜的侧壁。下部110b具有倒梯形形状(在图4D’中显示)。
上部110a具有第一宽度W1的顶面,和下部110b具有第二宽度W2的底面。虚拟界面形成在上部110a和下部110b之间。虚拟界面具有第三宽度W3。下部110b具有逐渐减小的宽度,该逐渐减小的宽度从虚拟界面至下部110b的底面逐渐减小。
在一些实施例中,第一宽度W1大于第二宽度W2。在一些实施例中,第二宽度W2小于或等于第三宽度W3。在一些实施例中,第三宽度W3和第二宽度W2之间的差值(ΔW=W3-W2)在从约0nm至约15nm的范围内。如果差值(ΔW)大于15nm,则伪栅极结构110的下部110b可能太小而无法支撑上部110a。如果差值小于0nm,可能难以形成源极/漏极(S/D)结构116(图2J显示)。
虚拟界面用于限定两个部分,并且在上部110a和下部110b之间没有形成实际界面。该界面可以看作上部110a的底面。此外,该界面可以看作下部110b的顶面。在一些实施例中,虚拟界面与鳍结构104的顶面基本上平齐。
如果伪栅极结构110’的上部在水平方向上具有延伸部分,当伪栅极结构110’被栅极结构取代时,栅极结构可以突出。突出的栅极结构可以与邻近突出的栅极结构形成的接触结构接触。结果,可能发生电短路问题。更具体地,栅电极层144的突出问题可能降低FinFET器件结构100的性能。
衬底102是晶圆的一部分。在一些实施例中,该晶圆包括中心区域和边缘区域,并且与在中心区域相比,晶圆的边缘区域中的突出问题加剧。因此,应当良好地控制边缘区域中的蚀刻气体。
为了防止突出的问题,如图2H所示,蚀刻伪栅极结构110’以形成基本上垂直的上部110a和位于鳍结构104下方的有缺口的下部110b。换句话说,伪栅极结构110’的带缺口的下部110b具有凹进的侧壁部分。
此外,应该指出的是,第二宽度W2小于或等于第三宽度W3,因此防止了漏致势垒降低(DIBL)效应。此外,当第一宽度W1大于第二宽度W2时,防止了击穿电压(Vbd)的拖尾的问题(Vbd分布在较宽的电压值范围内)。
上部110a具有第一高度H1和下部110b具有第二高度H2。在一些实施例中,第一高度H1大于第二高度H2。第一高度H1高于第二高度H2用于填充更多的金属材料,该金属材料将在随后的工艺中形成在鳍结构104之上。
如图2I所示,根据一些实施例,在形成伪栅极结构110’之后,在伪栅极结构110’的相对侧壁上形成间隔件212。在一些实施例中,间隔件212是由氮化硅、碳化硅、氮氧化硅、碳化硅、氧化硅、硅氢,其他适用的材料,或它们的组合制成的。
之后,去除鳍结构104的顶部以形成凹槽(未示出),和如图2J中所示,根据一些实施例,在凹槽中形成源极/漏极(S/D)结构116。
在一些实施例中,S/D结构116是应变的源极/漏极结构。在一些实施例中,通过外延(epi)工艺在鳍结构104的凹槽中生长应变材料来形成S/D结构116。
此外,应变材料的晶格常数可能不同于衬底102的晶格常数。
在一些实施例中,源极/漏极结构116包括Ge,SiGe,InAs,InGaAs,InSb,GaAs,GaSb,InAlP,InP,或它们的组合。外延工艺可以包括选择性外延生长(SEG)工艺,CVD沉积技术(如汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延、或其他合适的外延工艺。
在一些实施例中,在形成S/D结构116之后,在S/D结构116和伪栅极结构110’上形成接触蚀刻停止层(CESL)(未显示)。在一些实施例中,接触蚀刻停止层是由氮化硅,氮氧化硅,和/或其他适用的材料制成的。接触蚀刻停止层可以采用等离子体增强CVD、低压CVD、ALD、或其他适用的工艺形成。
之后,如图2K所示,根据一些实施例,在衬底102上方的鳍结构104上方形成层间介电(ILD)材料。在一些实施例中,层间介电(ILD)材料形成在隔离结构108上方并且然后被平坦化以形成ILD结构136。
如图2L所示,根据一些实施例,在形成ILD结构136之后,通过在ILD结构136中形成沟槽138来去除伪栅极结构110’。通过执行蚀刻工艺除去伪栅极结构110’。应该注意的是,不去除鳍结构104,并且因此,通过沟槽138暴露鳍结构104的中间部分。
如图2M所示,根据一些实施例,在形成沟槽138之后,在沟槽138中依次形成栅极介电层142和栅电极144。因此,得到包括栅极介电层142和栅电极层144的栅极结构146。
栅极介电层142具有高于鳍结构104的顶面的上部和低于鳍结构104的顶面的下部。栅极介电层142的上部具有恒定的宽度,并且栅极介电层142的下部具有不同的宽度。
在一些实施例中,该栅极介电层142采用高k介电材料制成。高k介电材料可以包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金,氧化铪硅,氮氧化铪硅、氧化铪钽、氧化铪钛,氧化铪锆等。
栅电极层144具有高于鳍结构104的顶面的上部和低于鳍结构104的顶面的下部。栅电极层144的上部具有恒定的宽度,并且栅电极层144的下部具有不同的宽度。
在一些实施例中,栅电极层144是由金属材料制成的。金属材料可以包括N-功函金属或P-功函金属。N-功函金属包括钨(W)、铜(Cu)、钛(Ti),银(Ag)、铝(Al)、钛铝合金(TiAl),氮化铝钛(TiAlN),碳化钽(TaC)、碳氮化钽(TaCN),氮化硅钽(TaSiN)、锰(Mn)、锆(Zr)或它们的组合。P-功函金属包括氮化钛(TiN)、氮化钨(WN)、氮化钽(TaN)、钌(Ru)或它们的组合。
如图2M所示,栅电极层144具有上部144a和下部144b。上部144a具有基本上垂直的侧壁并且下部144b具有倾斜的侧壁。下部144b具有从下部144b的虚拟表面至下部144b的底面逐渐减小的减小的宽度。应当指出的是,栅电极层144的上部144a具有基本上垂直的侧壁以防止突出部分与接触结构接触。此外,当底面的第二宽度W2小于或等于虚拟表面的第三宽度W3时,防止了漏致势垒降低(DIBL)效应。因此,提高了FinFET结构100的性能。
栅电极层144的上部144a具有第一高度,和栅电极层144的下部144b具有第二高度。第一高度高于第二高度,以在鳍结构104之上填充更多的金属材料。
图3示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构100的顶视图。FinFET器件结构100包括多个鳍结构104和多个栅极结构110。栅极结构110横跨在鳍结构104上方。FinFET器件结构100被隔离结构108围绕。
如图3所示,鳍结构104基本上彼此平行。栅极结构110也可以彼此平行并且基本上垂直于鳍结构104。在一些实施例中,当从顶部看时,栅极结构110也被称为栅电极线。
第一栅极晶体管300a和第二栅极晶体管300b形成在第一鳍结构104a上方。第三栅极晶体管300c和第四栅极晶体管300d形成在第二鳍结构104b上方。
图4A至图4F示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面图示。图4A至图4F是沿着图3的AA’线截取的截面图示。
参考图4A,在第一鳍结构104a,第二鳍结构104b和隔离结构108上方形成栅电极层110。隔离结构108的顶面低于鳍结构104的顶面。随后,在栅电极层110上方形成第一硬掩模层212a和第二硬掩模层212b。
在形成第二硬掩模层212b后,如图4B所示,根据本发明的一些实施例,在第二硬掩模层212b上方形成光刻胶层214。之后,图案化光刻胶层214。
如图4C所示,根据披露的一些实施例,在图案化光刻胶层214之后,图案化第一硬掩模层212a的一部分和第二硬掩模层212b的一部分以形成沟槽352。
在形成沟槽352之后,如图4D所示,根据本发明的一些实施例,通过将第一硬掩模层212a和第二硬掩模层212b作为掩模来图案化栅电极层110的一部分。其结果是,第一沟槽354形成在鳍结构104之上和在栅电极层110中。第二沟槽356形成在隔离结构108上方和形成在栅电极层110中。
通过蚀刻工艺121去除栅电极层110的部分。在一些实施例中,蚀刻工艺是等离子体工艺。等离子体工艺包括使用蚀刻气体,诸如氢溴酸。在一些实施例中,在等离子体工艺中也使用氦气(He)和氧气(O2)。在蚀刻工艺中,蚀刻气体的流速在从约700sccm至约1000sccm的范围内。如果流速小于700sccm,则蚀刻选择性可能较差。如果流速大于1000sccm,则蚀刻速率可能很难控制。
在一些实施例中,在从约350瓦到约1500瓦的范围内的功率下实施等离子体工艺。如果功率小于350瓦,则蚀刻选择性差。如果功率大于1500瓦,则蚀刻速率可能难以控制。在一些实施例中,在从约10托至约100托的范围内的压力下实施等离子体工艺。如果压力低于10托,则蚀刻选择性差。如果压力大于100托,则蚀刻速率可能难以控制。
应注意的是,该衬底102是晶圆的一部分,而晶圆包含中心区域和边缘区域。与在晶圆的中心区域中的宽度相比,在晶圆的边缘区域中的第二宽度W2的尺寸很难控制。为了使得第二宽度W2小于或等于第三宽度W3,在一些实施例中,边缘区域中蚀刻气体的量与所有区域中蚀刻气体的量的比率在从约50体积%至约90体积%的范围内。如果蚀刻气体的比率小于50体积%或者大于90体积%,则位于中心区域和边缘区域之间的负载效应可能较大,并且因此,难以控制第一宽度W1或者第二宽度W2的尺寸。
图4D’示出了根据本发明的一些实施例的图4D中的区域A的放大视图。如图4D’所示,栅电极层110包括上部110a和下部110b。上部110a位于高于鳍结构104a,104b的顶面的位置。下部110b位于低于鳍结构104a,104b的顶面的位置。栅电极层110的上部110a具有基本上垂直的侧壁并且栅电极层110的下部110b具有倾斜侧壁。
在上部110a和下部110b之间形成界面。该界面不是真正的边界,而是用于限定栅电极层110的形状。界面可以被认为是上部110a的底面。此外,该界面可以被认为是下部110b的顶面。在一些实施例中,上部110a的侧壁与虚拟界面之间的角度θ是从约85度到约95度的范围内。
上部110a具有均匀的宽度,和下部110b具有变化的宽度。上部110a具有第一宽度W1,界面具有第三宽度W3。下部110b的底面有第二宽度W2。在一些实施例中,第一宽度W1大于第二宽度W2,和第二宽度W2小于第三宽度W3。在一些实施例中,第三宽度W3和第二宽度W2之间的差异(ΔW=W3-W2)是在从约0纳米到约15纳米的范围内。如果差异(ΔW)大于15nm,则伪栅电极层110的下部110b可能太小而无法支撑上部110a。如果差值小于0纳米,则难以形成源极/漏极(S/D)结构116。
之后,去除第一硬掩模层212a和第二硬掩模层212b,和在伪栅极结构110的相对的侧壁上形成间隔件212。接下来,如图4所示,按照披露的一些实施例,将介电材料填充至沟槽354,356内和栅电极层110上作为掩模。
在填充介电材料之后,通过诸如化学机械抛光工艺(CMP)的平坦化的工艺去除位于沟槽354,356外的介电材料的一部分。作为一个结果,形成ILD结构136。ILD结构136是在相邻的两个栅极结构146之间形成。ILD结构136包括上部和下部,而下部比上部宽。
之后,如图4F所示,按照披露的一些实施例,去除栅电极层110以形成沟槽(未显示),并且在沟槽中依次形成栅极介电层142和栅电极层144。在一些实施例中,栅极介电层142是高介电常数(高k)介电层和栅电极144是金属栅电极。换句话说,在鳍结构104上形成HK/MG堆叠结构。
如图4F所示,栅极介电层142和栅电极层144分为四个部分,并且分别形成第一晶体管300a、和第二晶体管300b、第三晶体管300c和第四晶体管300d。第一晶体管300a、和第二晶体管300b、第三晶体管300c和第四晶体管300d中的每个均由栅极介电层142和栅电极层144构成。ILD结构136位于第一晶体管300a和第二晶体管300b之间。此外,ILD结构136位于第三晶体管300c和第四晶体管300d之间。
图5A至图5C示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的界面图。图5A至图5C是沿着图3的BB’线截取的截面图示。
如图5A中所示,在栅电极层110上方形成第一硬掩模层212a和第二硬掩模层212b。
之后,如图5B所示,根据本发明的一些实施例,图案化第一硬掩模层212a和第二硬掩模层212b以形成图案化的第一硬掩模层212a和图案化的第二硬掩模层212b。
之后,如图5C所示,根据本发明的一些实施例,蚀刻栅电极层110以形成上部110a和下部110b。
提供了形成FinFET器件结构及其形成方法的实施例。FinFET器件结构包括形成在衬底上方的鳍结构和形成在鳍结构上方的栅极结构。栅极结构包括上部和下部。上部有基本垂直的侧壁,和下部具有从顶部至底部逐渐呈锥形的倾斜侧壁。上部的基本垂直侧壁用于防止突出问题。虚拟界面形成在上部和下部之间,当下部的底面的第二宽度小于或等于虚拟界面的第三宽度时,防止了漏致势垒降低(DIBL)效应。因此,改进了FinFET器件结构的性能和可靠性。
在一些实施例中,提供了一种FinFET器件结构。FinFET器件结构包括:鳍结构,形成在衬底上方;以及栅极结构,横越在鳍结构上方。栅极结构包括栅电极层,栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,在上部和下部之间形成虚拟界面,并且下部具有从虚拟界面至下部的底面逐渐减小的减小的宽度。
在一些实施例中,提供了一种FinFET器件结构。FinFET器件结构包括:鳍结构,形成在衬底上方;隔离结构,形成在衬底上方。鳍结构的部分嵌入在隔离结构中。FinFET器件结构包括横越在鳍结构上方的第一栅极结构,和第一栅极结构包括第一栅电极层,第一栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部。下部具有倒梯形形状。
在一些实施例中,提供了一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法。该方法包括:在衬底上方形成鳍结构和;在衬底上方形成隔离结构。鳍结构的部分嵌入在隔离结构中。该方法也包括在鳍结构和隔离结构上方形成栅极结构,和栅极结构包括栅电极层,栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部。下部具有从虚拟界面至下部的底面逐渐减小的减小的宽度,虚拟界面形成在上部和下部之间。
根据本发明的一些实施例,提供了一种鳍式场效应晶体管(FinFET)器件结构,包括:鳍结构,形成在衬底上方;以及栅极结构,横越在所述鳍结构上方,其中,所述栅极结构包括栅电极层,所述栅电极层包括位于所述鳍结构之上的上部和位于鳍结构下方的下部,在所述上部和所述下部之间形成有虚拟界面,并且所述下部具有从所述虚拟界面至所述下部的底面逐渐减小的减小的宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述上部具有第一宽度的顶面,和所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述虚拟界面具有第三宽度,并且所述第三宽度大于所述第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述虚拟界面与所述鳍结构的顶面平齐。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述栅电极层的上部具有垂直的侧壁。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述栅电极层的上部具有第一高度,和所述栅电极层的下部具有第二高度,并且所述第一高度大于所述第二高度。
在上述鳍式场效应晶体管(FinFET)器件结构中,还包括:隔离结构,形成在所述衬底上方,其中,所述栅极结构的一部分形成在所述隔离结构上方。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述栅电极层的下部具有倒梯形形状。
根据本发明的另一些实施例,还提供了一种鳍式场效应晶体管(FinFET)器件结构,包括:鳍结构,形成在衬底上方;隔离结构,形成在所述衬底上方,其中,所述鳍结构的部分嵌入在所述隔离结构中;以及第一栅极结构,横越在所述鳍结构上方,其中,第一栅极结构包括第一栅电极层,第一栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,并且所述下部具有倒梯形形状。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述第一栅电极层的上部具有第一高度,并且所述第一栅电极层的下部具有第二高度,并且所述第一高度高于所述第二高度。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述上部具有第一宽度的顶面和所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,在所述上部和所述下部之间形成有虚拟界面,和所述虚拟界面具有第三宽度,并且所述第二宽度小于或等于所述第三宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述第一栅电极层的下部从所述虚拟界面至所述底面逐渐变细。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述第一栅电极层的上部具有垂直的侧壁。
在上述鳍式场效应晶体管(FinFET)器件结构中,还包括:第二栅极结构,横越在所述鳍结构上方;和层间介电层(ILD)结构,位于所述第一栅极结构和所述第二栅极结构之间,其中,所述ILD结构包括上表面和下表面,所述下表面宽于所述上表面。
在上述鳍式场效应晶体管(FinFET)器件结构中,所述ILD结构的下部具有倾斜的侧壁,所述倾斜的侧壁从所述下部的底面至所述下部的顶面逐渐变细。
根据本发明的又一些实施例,还提供了一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法,包括:在衬底上方形成鳍结构;在所述衬底上方形成隔离结构,其中,所述鳍结构的部分嵌入在所述隔离结构中;以及在所述鳍结构和所述隔离结构上方形成栅极结构,其中,所述栅极结构包括栅电极层,所述栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,并且所述下部具有从虚拟界面至所述下部的底面逐渐减小的减小的宽度,所述虚拟界面形成在所述上部和所述下部之间。
在上述用于形成鳍式场效应晶体管(FinFET)器件结构的方法中,在所述鳍结构和所述隔离结构上方形成所述栅极结构包括:在所述鳍结构和所述隔离结构上方形成栅极材料;在所述栅极材料上方形成硬掩模层;图案化所述硬掩模层;以及将所述硬掩模层用作掩模蚀刻所述栅极材料以形成栅极结构。
在上述用于形成鳍式场效应晶体管(FinFET)器件结构的方法中,蚀刻所述栅极材料包括使用蚀刻工艺,并且在从10托至100托的范围内的压力下实施所述蚀刻工艺。
在上述用于形成鳍式场效应晶体管(FinFET)器件结构的方法中,还包括:在所述衬底上方并且邻近所述栅极结构形成层间介电(ILD)结构;去除所述栅极结构以在所述ILD结构中形成沟槽;以及在所述沟槽中填充栅极介电层和栅电极层。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解、他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优点的其他处理和结构。本领域技术人员也应该意识到、这种等效构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下、可以进行多种变化、替换以及改变。
Claims (10)
1.一种鳍式场效应晶体管(FinFET)器件结构,包括:
鳍结构,形成在衬底上方;以及
栅极结构,横越在所述鳍结构上方,其中,所述栅极结构包括栅电极层,所述栅电极层包括位于所述鳍结构之上的上部和位于鳍结构下方的下部,在所述上部和所述下部之间形成有虚拟界面,并且所述下部具有从所述虚拟界面至所述下部的底面逐渐减小的减小的宽度。
2.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述上部具有第一宽度的顶面,和所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
3.根据权利要求2所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述虚拟界面具有第三宽度,并且所述第三宽度大于所述第二宽度。
4.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述虚拟界面与所述鳍结构的顶面平齐。
5.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述栅电极层的上部具有垂直的侧壁。
6.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述栅电极层的上部具有第一高度,和所述栅电极层的下部具有第二高度,并且所述第一高度大于所述第二高度。
7.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,还包括:
隔离结构,形成在所述衬底上方,其中,所述栅极结构的一部分形成在所述隔离结构上方。
8.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述栅电极层的下部具有倒梯形形状。
9.一种鳍式场效应晶体管(FinFET)器件结构,包括:
鳍结构,形成在衬底上方;
隔离结构,形成在所述衬底上方,其中,所述鳍结构的部分嵌入在所述隔离结构中;以及
第一栅极结构,横越在所述鳍结构上方,其中,第一栅极结构包括第一栅电极层,第一栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,并且所述下部具有倒梯形形状。
10.一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法,包括:
在衬底上方形成鳍结构;
在所述衬底上方形成隔离结构,其中,所述鳍结构的部分嵌入在所述隔离结构中;以及
在所述鳍结构和所述隔离结构上方形成栅极结构,其中,所述栅极结构包括栅电极层,所述栅电极层包括位于鳍结构之上的上部和位于鳍结构下方的下部,并且所述下部具有从虚拟界面至所述下部的底面逐渐减小的减小的宽度,所述虚拟界面形成在所述上部和所述下部之间。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562188028P | 2015-07-02 | 2015-07-02 | |
US62/188,028 | 2015-07-02 | ||
US14/942,491 | 2015-11-16 | ||
US14/942,491 US10269651B2 (en) | 2015-07-02 | 2015-11-16 | Fin field effect transistor (FinFET) device structure and method for forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106328711A true CN106328711A (zh) | 2017-01-11 |
CN106328711B CN106328711B (zh) | 2019-08-30 |
Family
ID=57582599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610511247.9A Active CN106328711B (zh) | 2015-07-02 | 2016-07-01 | 鳍式场效应晶体管(FinFET)器件结构及其形成方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US10269651B2 (zh) |
KR (1) | KR101820226B1 (zh) |
CN (1) | CN106328711B (zh) |
DE (1) | DE102016100035B4 (zh) |
TW (1) | TWI578529B (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110277447A (zh) * | 2018-03-14 | 2019-09-24 | 台湾积体电路制造股份有限公司 | 用于半导体器件的具有期望轮廓的栅极结构 |
CN111613583A (zh) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN112447828A (zh) * | 2019-08-27 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体结构及其形成方法 |
CN113451212A (zh) * | 2020-06-12 | 2021-09-28 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN113540235A (zh) * | 2020-04-13 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN113555317A (zh) * | 2020-07-10 | 2021-10-26 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
CN114093946A (zh) * | 2021-09-18 | 2022-02-25 | 上海华力集成电路制造有限公司 | 提升FinFET的交流性能的结构和方法 |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10262870B2 (en) | 2015-07-02 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure and method for forming the same |
US10269651B2 (en) | 2015-07-02 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure and method for forming the same |
US10096712B2 (en) | 2015-10-20 | 2018-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming and monitoring quality of the same |
US9960273B2 (en) * | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
US9704969B1 (en) * | 2015-12-31 | 2017-07-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin semiconductor device having multiple gate width structures |
US9859420B1 (en) * | 2016-08-18 | 2018-01-02 | International Business Machines Corporation | Tapered vertical FET having III-V channel |
US10446662B2 (en) * | 2016-10-07 | 2019-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode |
WO2018182617A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Transistors employing non-selective deposition of source/drain material |
US10186456B2 (en) | 2017-04-20 | 2019-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming contact plugs with reduced corrosion |
US10204905B2 (en) | 2017-04-25 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
US10141225B2 (en) | 2017-04-28 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gates of transistors having reduced resistivity |
KR102303300B1 (ko) * | 2017-08-04 | 2021-09-16 | 삼성전자주식회사 | 반도체 장치 |
US10811320B2 (en) * | 2017-09-29 | 2020-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Footing removal in cut-metal process |
US10741667B2 (en) * | 2018-02-27 | 2020-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a protective stack on a semiconductor fin |
US10515955B1 (en) * | 2018-05-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing transistor gate structures by local thinning of dummy gate stacks using an etch barrier |
US10658491B2 (en) * | 2018-06-15 | 2020-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling profiles of replacement gates |
US11315933B2 (en) * | 2018-06-29 | 2022-04-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM structure and method for forming the same |
US11158545B2 (en) | 2018-09-25 | 2021-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming isolation features in metal gates |
KR102612592B1 (ko) * | 2018-10-15 | 2023-12-12 | 삼성전자주식회사 | 반도체 소자 |
US11482421B2 (en) * | 2019-10-29 | 2022-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a semiconductor device by a replacement gate process |
US11309403B2 (en) * | 2019-10-31 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistor device and method of forming the same |
US11430865B2 (en) * | 2020-01-29 | 2022-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US11398384B2 (en) | 2020-02-11 | 2022-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for manufacturing a transistor gate by non-directional implantation of impurities in a gate spacer |
US11302581B2 (en) * | 2020-05-05 | 2022-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate profile control through sidewall protection during etching |
US11532481B2 (en) * | 2020-06-30 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field-effect transistor device and method of forming |
US11670675B2 (en) | 2020-12-04 | 2023-06-06 | United Semiconductor Japan Co., Ltd. | Semiconductor device |
US11824103B2 (en) * | 2021-04-23 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8264048B2 (en) * | 2008-02-15 | 2012-09-11 | Intel Corporation | Multi-gate device having a T-shaped gate structure |
CN102969232B (zh) * | 2011-09-01 | 2015-01-14 | 中国科学院微电子研究所 | 后栅工艺中假栅的制造方法 |
US20150115363A1 (en) * | 2013-10-30 | 2015-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd | Mechanisms for forming finfet device |
CN105336624A (zh) * | 2014-08-11 | 2016-02-17 | 中国科学院微电子研究所 | 鳍式场效应晶体管及其假栅的制造方法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6762129B2 (en) | 2000-04-19 | 2004-07-13 | Matsushita Electric Industrial Co., Ltd. | Dry etching method, fabrication method for semiconductor device, and dry etching apparatus |
JP2003077900A (ja) | 2001-09-06 | 2003-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
US6649489B1 (en) | 2003-02-13 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | Poly etching solution to improve silicon trench for low STI profile |
US7859065B2 (en) | 2005-06-07 | 2010-12-28 | Nec Corporation | Fin-type field effect transistor and semiconductor device |
US7473593B2 (en) | 2006-01-11 | 2009-01-06 | International Business Machines Corporation | Semiconductor transistors with expanded top portions of gates |
US20110241118A1 (en) | 2010-03-30 | 2011-10-06 | Globalfoundries Inc | Metal gate fill by optimizing etch in sacrificial gate profile |
US8541296B2 (en) | 2011-09-01 | 2013-09-24 | The Institute of Microelectronics Chinese Academy of Science | Method of manufacturing dummy gates in gate last process |
US8629512B2 (en) | 2012-03-28 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate stack of fin field effect transistor with slanted sidewalls |
US8652932B2 (en) | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US9041115B2 (en) | 2012-05-03 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for FinFETs |
KR101909091B1 (ko) | 2012-05-11 | 2018-10-17 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US8803241B2 (en) | 2012-06-29 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy gate electrode of semiconductor device |
JP2014120661A (ja) | 2012-12-18 | 2014-06-30 | Tokyo Electron Ltd | ダミーゲートを形成する方法 |
US9117908B2 (en) | 2013-12-16 | 2015-08-25 | Globalfoundries Inc. | Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor products |
KR102125749B1 (ko) | 2013-12-27 | 2020-07-09 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
US9620621B2 (en) | 2014-02-14 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Gate structure of field effect transistor with footing |
US9620417B2 (en) | 2014-09-30 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method of manufacturing fin-FET devices |
US9064943B1 (en) | 2014-09-30 | 2015-06-23 | International Business Machines Corporation | Gate-all-around field effect transistor structures and methods |
KR20160044976A (ko) | 2014-10-16 | 2016-04-26 | 삼성전자주식회사 | 핀형 전계 효과 트랜지스터를 구비한 반도체 소자 |
KR102224386B1 (ko) | 2014-12-18 | 2021-03-08 | 삼성전자주식회사 | 집적 회로 장치의 제조 방법 |
WO2016105348A1 (en) * | 2014-12-22 | 2016-06-30 | Intel Corporation | Optimizing gate profile for performance and gate fill |
DE102015005856A1 (de) | 2015-05-06 | 2016-11-10 | Audi Ag | Beduftungsanlage für ein Fahrzeug |
US10269651B2 (en) | 2015-07-02 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure and method for forming the same |
US10262870B2 (en) | 2015-07-02 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure and method for forming the same |
JP2017039383A (ja) | 2015-08-19 | 2017-02-23 | スズキ株式会社 | 4輪車の車体フロア構造 |
-
2015
- 2015-11-16 US US14/942,491 patent/US10269651B2/en active Active
-
2016
- 2016-01-04 DE DE102016100035.3A patent/DE102016100035B4/de active Active
- 2016-01-08 TW TW105100491A patent/TWI578529B/zh active
- 2016-02-15 KR KR1020160017205A patent/KR101820226B1/ko active IP Right Grant
- 2016-07-01 CN CN201610511247.9A patent/CN106328711B/zh active Active
-
2018
- 2018-07-31 US US16/049,884 patent/US10854519B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8264048B2 (en) * | 2008-02-15 | 2012-09-11 | Intel Corporation | Multi-gate device having a T-shaped gate structure |
CN102969232B (zh) * | 2011-09-01 | 2015-01-14 | 中国科学院微电子研究所 | 后栅工艺中假栅的制造方法 |
US20150115363A1 (en) * | 2013-10-30 | 2015-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd | Mechanisms for forming finfet device |
CN105336624A (zh) * | 2014-08-11 | 2016-02-17 | 中国科学院微电子研究所 | 鳍式场效应晶体管及其假栅的制造方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110277447A (zh) * | 2018-03-14 | 2019-09-24 | 台湾积体电路制造股份有限公司 | 用于半导体器件的具有期望轮廓的栅极结构 |
CN110277447B (zh) * | 2018-03-14 | 2022-09-20 | 台湾积体电路制造股份有限公司 | 用于半导体器件的具有期望轮廓的栅极结构 |
CN111613583A (zh) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN111613583B (zh) * | 2019-02-25 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN112447828A (zh) * | 2019-08-27 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体结构及其形成方法 |
CN112447828B (zh) * | 2019-08-27 | 2024-03-01 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体结构及其形成方法 |
CN113540235A (zh) * | 2020-04-13 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN113451212A (zh) * | 2020-06-12 | 2021-09-28 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN113555317A (zh) * | 2020-07-10 | 2021-10-26 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
CN114093946A (zh) * | 2021-09-18 | 2022-02-25 | 上海华力集成电路制造有限公司 | 提升FinFET的交流性能的结构和方法 |
Also Published As
Publication number | Publication date |
---|---|
US20180337095A1 (en) | 2018-11-22 |
KR20170004827A (ko) | 2017-01-11 |
DE102016100035B4 (de) | 2022-09-29 |
TW201703258A (zh) | 2017-01-16 |
CN106328711B (zh) | 2019-08-30 |
KR101820226B1 (ko) | 2018-01-18 |
DE102016100035A1 (de) | 2017-01-05 |
US10854519B2 (en) | 2020-12-01 |
US10269651B2 (en) | 2019-04-23 |
US20170005005A1 (en) | 2017-01-05 |
TWI578529B (zh) | 2017-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11309189B2 (en) | Fin field effect transistor (FinFET) device structure and method for forming the same | |
CN106328711B (zh) | 鳍式场效应晶体管(FinFET)器件结构及其形成方法 | |
KR101785154B1 (ko) | 핀 전계 효과 트랜지스터(finfet) 디바이스 구조체 | |
KR101780869B1 (ko) | 수직 게이트 올 어라운드 소자 내의 실리사이드 영역 및 그 형성 방법 | |
CN105977284B (zh) | 用于鳍式场效应晶体管的源极/漏极区及其形成方法 | |
US8786019B2 (en) | CMOS FinFET device | |
KR101713422B1 (ko) | 핀의 보호층을 포함하는 핀 구조 전계 효과 트랜지스터 소자 구조체 및 그 형성방법 | |
CN103515440B (zh) | 半导体器件的伪栅电极 | |
CN106158854A (zh) | 半导体器件及其制造方法 | |
CN106252407A (zh) | 具有停止层的鳍式场效应晶体管(FinFET)器件结构及其形成方法 | |
CN105932060A (zh) | 无轻掺杂漏极的半导体结构及其制造方法 | |
US11264383B2 (en) | Fin field effect transistor (FinFET) device structure with capping layer and method for forming the same | |
US20150236132A1 (en) | Fin field effect transistor (finfet) device and method for forming the same | |
CN106531686A (zh) | 互连结构和其制造方法及半导体器件 | |
US20190148241A1 (en) | Method for forming fin field effect transistor (finfet) device structure | |
US20230411391A1 (en) | Stacked device structures and methods for forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |