CN106158931B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN106158931B
CN106158931B CN201610146084.9A CN201610146084A CN106158931B CN 106158931 B CN106158931 B CN 106158931B CN 201610146084 A CN201610146084 A CN 201610146084A CN 106158931 B CN106158931 B CN 106158931B
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groove
metal
layer
dielectric spacer
semiconductor substrate
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CN106158931A (zh
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洪奇成
陈科维
王喻生
钟明锦
吴家扬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Abstract

一种半导体结构包括半导体衬底、至少一个介电层、介电间隔件衬垫(DSL)层和至少一个导体。该介电层存在于半导体衬底上。该介电层具有至少一个接触孔，其曝光半导体衬底的至少一部分。该半导体衬底具有与接触孔连通的至少一个凹槽。该凹槽具有底表面和至少一个侧壁。该DSL层至少存在于凹槽的该侧壁上。导体至少部分地存在于接触孔中并且电连接至半导体衬底。本发明还提供了用于制造半导体结构的方法。

Description

半导体结构及其制造方法
优先权及交叉引用
本申请要求于2015年5月15日提交的、美国临时专利申请序列号62/162,388的优先权，其通过引用结合于此。
技术领域
本公开涉及一种半导体器件。
背景技术
持续努力着对集成电路进行缩放。随着电路变得更小且更快，金属硅化物触点常常被用以获得更高的电路性能。由于金属硅化物触点比非硅化区域具有更小的接触电阻，使用这种技术的集成电路能够具有更小的接触面积，并且使用更少的能量来使电流穿过它们。总之，这些效果产生了更高性能的集成电路。
发明内容
根据本发明的一个方面，提供了一种半导体结构，包括：半导体衬底；至少一个介电层，存在于半导体衬底上，介电层具有曝光半导体衬底的至少一部分的至少一个接触孔，其中半导体衬底具有与接触孔连通的至少一个凹槽，并且凹槽具有底表面和至少一个侧壁；介电间隔件衬垫(DSL)层，至少存在于凹槽的侧壁上；以及至少一个导体，至少部分地存在于接触孔中并且电连接至半导体衬底。
根据本发明的一个实施例，进一步包括：存在于凹槽中的至少一个金属半导体合金触点，其中导体通过所述金属半导体合金触点电连接至半导体衬底。
根据本发明的一个实施例，DSL层由防止在金属半导体合金触点的形成中使用的蚀刻剂穿过的材料制成。
根据本发明的一个实施例，DSL层由碳氧化硅(SiOC)、氮氧化硅(SiON)、二氧化硅(SiO2)、氮化硅(SiN)或上述的组合制成。
根据本发明的一个实施例，DSL层进一步存在于接触孔的至少一个侧壁上。
根据本发明的一个实施例，半导体衬底具有位于其中的至少一个应力源，接触孔曝光应力源的至少一部分，并且凹槽存在于应力源中。
根据本发明的另一方面，提供了一种用于制造半导体结构的方法，该方法包括：在半导体衬底上形成至少一个介电层；在介电层中形成至少一个接触孔，以曝光半导体衬底的至少一部分；在半导体衬底中形成至少一个凹槽，其中，凹槽与接触孔连通，并且凹槽具有底表面和至少一个侧壁；至少在凹槽的侧壁上形成至少一个介电间隔件衬垫(DSL)层；以及至少部分地在接触孔中形成至少一个导体，其中导体电连接至半导体衬底。
根据本发明的一个实施例，进一步包括：在形成DSL层之前，至少去除凹槽的侧壁上的氧化物。
根据本发明的一个实施例，氧化物被物理性地去除。
根据本发明的一个实施例，氧化物借助惰性气体通过溅射去除。
根据本发明的一个实施例，氧化物通过氩溅射去除。
根据本发明的一个实施例，进一步包括：至少在凹槽中形成含金属材料；将含金属材料和半导体衬底的邻近凹槽的一部分转变成金属半导体合金触点；以及去除未转变成金属半导体合金触点的剩余的含金属材料。
根据本发明的一个实施例，DSL层由防止在去除剩余的含金属材料中使用的蚀刻剂穿过的材料制成。
根据本发明的一个实施例，DSL层由碳氧化硅(SiOC)、氮氧化硅(SiON)、二氧化硅(SiO2)、氮化硅(SiN)或上述的组合制成。
根据本发明的一个实施例，形成DSL层进一步在接触孔的至少一个侧壁上形成DSL层。
根据本发明的又一个方面，提供了一种用于制造半导体结构的方法，该方法包括：在半导体衬底中形成至少一个源极/漏极区；至少在源极/漏极区上形成至少一个介电层；在介电层中形成至少一个接触孔以曝光源极/漏极区的至少一部分，其中形成接触孔进一步在源极/漏极区中形成至少一个凹槽，并且凹槽具有底表面和至少一个侧壁；物理性地清除凹槽的至少侧壁；在介电层、接触孔和凹槽上形成至少一个介电间隔件衬垫(DSL)层；去除凹槽的底表面上的DSL层；以及在接触孔中形成至少一个导体，其中导体电连接至源极/漏极区。
根据本发明的一个实施例，物理性地清除将凹槽的至少侧壁上的氧化物去除。
根据本发明的一个实施例，进一步包括：在半导体衬底上形成至少一个栅极堆叠件。
根据本发明的一个实施例，进一步包括：至少在凹槽中形成含金属材料；将含金属材料和源极/漏极区的邻近凹槽的一部分转变成金属半导体合金触点；借助蚀刻剂去除未转变成金属半导体合金触点的剩余的含金属材料；以及通过DSL层阻挡蚀刻剂进入到栅极堆叠件中。
根据本发明的一个实施例，栅极堆叠件是含金属栅极堆叠件。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图15是根据一些示例性实施例的金属氧化物半导体(MOS)器件的形成的中间阶段的截面图。
具体实施方式
为了实施本公开的不同部件，以下公开提供了许多不同的实施例或示例。以下描述元件和布置的特定示例以简化本公开。当然这些仅仅是示例并不打算限定。例如，以下描述中第一部件形成在第二部件上可包括其中第一和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成插入到第一和第二部件中的实施例，使得第一和第二部件不直接接触。再者，本公开可在各个示例中重复参照数字和/或字母。该重复是为了简明和清楚，而且其本身没有规定所述各种实施例和/或结构之间的关系。
此外，为便于描述，在本文中可以使用诸如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等的空间相对位置术语，以描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且因此可以对本文中使用的空间相对位置描述符作同样地解释。
根据多个示例性实施例提供了金属氧化物半导体(MOS)器件及其制造方法。图示出了形成该MOS器件的中间阶段。对实施例的变型进行讨论。纵观多种视图和示意性实施例，相同参考标号被用以表示相同元件。
图1至图15是根据一些示例性实施例的金属氧化物半导体(MOS)器件100的形成的中间阶段的截面图。参照图1，提供包括半导体衬底110的晶圆。该半导体衬底110可以由半导体材料制成，该半导体材料诸如为硅、碳化硅(SiC)、硅锗(SiGe)、III-V化合物半导体或上述的组合。诸如浅沟槽隔离(STI)区200的隔离区形成在半导体衬底110中并且用以限定MOS器件100的有源区域。
栅极堆叠件120形成在半导体衬底110之上。该栅极堆叠件120包括伪栅极介电层122和伪栅极电极124。伪栅极介电层122在一些示例性实施例中包括氧化硅。在可选的实施例中，也使用诸如氮化硅、碳化硅(SiC)等的其他材料。伪栅极电极124可包括多晶硅。在一些实施例中，栅极堆叠件120进一步包括位于伪栅极电极124之上的硬掩模126。硬掩模126可例如包括氮化硅，但也可使用诸如碳化硅(SiC)、氮氧化硅等的其他材料。在可选的实施例中，未形成硬掩模126。
根据由此产生的金属氧化物半导体(MOS)器件100的导电类型，轻掺杂的漏极/源极(LDD)区130例如通过植入p型杂质(诸如硼和/或铟)或n型杂质(诸如磷和/或砷)来形成。例如，当MOS器件100是pMOS器件时，该LDD区130是p型区。当该MOS器件100是nMOS器件时，该LDD区130是n型区。栅极堆叠件120充当注入掩模，以便LDD区130的边缘与栅极堆叠件120的边缘基本对齐。
参照图2。栅极间隔件140形成在栅极堆叠件120的侧壁上。在一些实施例中，每个栅极间隔件140均包括氮氧化硅层142和氧化硅层144。在可选的实施例中，栅极间隔件140包括一个或多个层，每个层均包括氧化硅、氮化硅、氮氧化硅或其他介电材料。可用的形成方法包括等离子增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)、次大气压化学汽相沉积(SACVD)和其他的沉积方法。
源极和漏极区(此后称作源极/漏极区)135形成在半导体衬底110中。在可选的实施例中，其中，金属氧化物半导体(MOS)器件100是pMOS器件，则该源极/漏极区135是p型的。在MOS器件100是nMOS器件的实施例中，该源极/漏极区135是n型的。在一些实施例中，源极/漏极应力源(同样标记为135)形成在半导体衬底110中。该源极/漏极应力源形成源极/漏极区135的至少一些部分。图2图示出了源极/漏极区135与各个源极/漏极应力源完全重叠的实施例。在可选的实施例中，源极/漏极区135和源极/漏极应力源是部分上重叠。
此外，在金属氧化物半导体(MOS)器件100是nMOS器件的实施例中，该源极/漏极应力源135可以包括磷化硅(SiP)、碳化硅(SiC)等。在MOS器件100是pMOS器件的实施例中，该源极/漏极应力源135可以包括硅锗(SiGe)。该源极/漏极应力源135的形成可以通过蚀刻半导体衬底110以在其中形成凹槽并且然后执行外延附生以在该凹槽中生长该源极/漏极应力源135来实现。
参照图3。接触蚀刻终止层(CESL)150形成在栅极堆叠件120和源极/漏极区135之上。在一些实施例中，该CESL150包括氮化硅、碳化硅(SiC)或其他介电材料。层间介电层(ILD)160形成在CESL150之上。该ILD160覆盖形成到比栅极堆叠件120的顶表面更高的高度。该ILD160可包括例如使用流动性化学汽相沉积(FCVD)形成的流动性氧化物。该ILD160还可以是使用旋转涂布形成的旋涂玻璃。例如，该ILD160可包括磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼掺杂磷硅玻璃(BPSG)、原硅酸四乙酯(TEOS)氧化物、TiN、SiOC或其他低k非渗透性介电材料。
图4图示出了平坦化步骤，这例如使用化学机械抛光(CMP)来执行。执行该CMP以去除层间介电层(ILD)160和接触蚀刻终止层(CESL)150的多余部分，其中，该多余部分位于硬掩模126之上。因此，得以曝光该栅极堆叠件120。在可选的实施例中，硬掩模126在CMP期间被去除，其中该CMP在伪栅极电极124的顶表面上停止。
参照图5。去除硬掩模126、伪栅极电极124和伪栅极介电层122。由于硬掩模126、伪栅极电极124和伪栅极介电层122的去除而形成开口O。在一些实施例中，开口O的宽度W1小于约25nm并且可以在从约18nm至约22nm的范围中。然而，可以想到，在整个说明书中列举的值仅仅是实例，并且可以改变成不同的值。此外，开口O的深度D1可大于约40nm。开口O的深宽比D1/W1可高于约1.3、高于约7或高于约10。
参照图6。形成栅极介电层121。在一些实施例中，该栅极介电层121包括界面层(IL，栅极介电层121的下部)，其为介电层。在一些实施例中，该IL包括诸如氧化硅层的氧化层，其可以通过半导体衬底110的热氧化、化学氧化或沉积步骤而形成。该栅极介电层121还可包括高k介电层(栅极介电层121的上部)，其包括高k介电材料，该高k介电材料诸如为氧化铪、氧化镧、氧化铝或上述的组合。高k介电材料的介电常数(k值)高于约3.9，并且可以高于约7，并且有时像约21一样高或更高。该高k介电层是与IL重叠的并且可接触该IL。
如图6中所示，扩散势垒层123形成在栅极介电层121之上。在一些实施例中，该扩散势垒层123包括TiN、TaN或上述的组合。例如，该扩散势垒层123可包括TiN层(该扩散势垒层123的下部)和位于该TiN层之上的TaN层(该扩散势垒层123的上部)。该TiN层可具有小于约的厚度，并且该TaN层可具有小于约厚度。
金属层125形成在扩散势垒层123之上。在由此产生的金属氧化物半导体(MOS)器件100是nMOS器件的实施例中，该金属层125与扩散势垒层123接触。例如，在扩散势垒层123包括TiN层和TaN层的实施例中，该金属层125可与该TaN层物理接触。在由此产生的MOS器件100是pMOS器件的替代实施例中，另外的TiN层(未示出)形成在TaN层(位于扩撒势垒层123中)与重叠的金属层125之间并且与这两者接触。该另外的TiN层提供适于pMOS器件的功函数，该功函数高于中间禁带(mid-gap)功函数(约4.5eV)，该中间禁带功函数位于硅的价电带和导电带的中间。高于中间禁带功函数的功函数被称作p功函数，且具有p功函数的各金属被称作p金属。
该金属层125提供适于nMOS器件的功函数，该功函数低于中间禁带功函数。低于中间禁带功函数的功函数被称作n功函数，并且具有n功函数的各金属被称作n金属。在一些实施例中，金属层125是具有低于约4.3eV的功函数的n金属。金属层125的功函数还可以在从约3.8eV至约4.6eV的范围中。金属层125根据一些实施例可包括钛铝(TiAl)(其可包括、不含或基本不含其它元素)。金属层125的形成可通过物理汽相沉积(PVD)来实现。根据本公开的一些实施例，金属层50在室温下(例如，从约20℃至约25℃)下形成。在替代实施例中，金属层125在比室温高的高温(例如，高于约200℃)下形成。
块层127形成在金属层125之上。该块层127在一些实施例中可包括TiN。该块层127可使用原子层沉积(ALD)形成。在一些实施例中，该块层127具有位于从约2nm至约7nm的范围中的厚度。
润湿层128形成在块层127之上，该润湿层128具有在填充金属129的回流期间黏附(且润湿)随后形成的填充金属129的能力。在一些实施例中，该润湿层128是钴层，其可使用原子层沉积(ALD)或化学汽相沉积(CVD)形成。在一些实施例中，该润湿层128具有位于从约1nm至约3nm的范围中的厚度。
填充金属129形成为填充开口O(如图5中所示)的剩余部分。该填充金属129可包括铝或铝合金，其还可以使用物理汽相沉积(PVD)、化学汽相沉积(CVD)等形成。该填充金属129可回流以完全充满如图5中所示的剩余开口O。润湿层128的形成改进填充金属129对下面的层的润湿。
图7图示出了平坦化步骤(例如，化学机械抛光(CMP))用于去除层129、128、127、125、123和121的多余部分，其中该多余部分位于层间介电层(ILD)160之上。层129、128、127、125、123和121的剩余部分形成替换含金属栅极堆叠件。层129、128、127、125、123和121的剩余部分的每个均包括底部、以及位于底部之上并且连接至底部的侧壁部。
参照图8。根据一些实施例，氧化膜170形成在层间介电层(ILD)160和栅极堆叠件120上。该氧化膜170是连续膜。该氧化膜170可覆盖或直接接触ILD160和栅极堆叠件120。该氧化膜170例如由氧化硅、氧化铝或适于黏附至ILD160和随后形成的层的其他含氧化物材料制成。该氧化膜170可具有在从约至约的范围中的厚度。该氧化膜170可例如使用化学汽相沉积(CVD)形成。
根据一些实施例，接触蚀刻终止层(CESL)175形成在层间介电层(ILD)160和栅极堆叠件120之上。该CESL175可形成在氧化膜170上。该CESL175由氮化硅或其他合适的材料制成。
本公开的实施例具有诸多变型。例如，在替代实施例中，未形成氧化膜170。该栅极堆叠件120与接触蚀刻终止层(CESL)175直接接触。
保护层180形成在接触蚀刻终止层(CESL)175上。根据一些实施例，该保护层180构造成保护CESL175在随后的预非晶化注入(PAI)工艺期间免于被损坏。该保护层180例如包括等离子体增强氧化(PEOX)层。
参照图9。保护层180、接触蚀刻终止层(CESL)175、氧化膜170、层间介电层(ILD)160以及接触蚀刻终止层(CESL)150可分别被图案化以形成曝光源极/漏极区135的接触孔C。光刻工艺和蚀刻工艺可被用于图案化。例如，通过将光刻胶层应用至保护层180的上表面、将该光刻胶层曝光至辐射图案、并随后利用光刻胶显影剂使该图案显影到光刻胶蚀刻掩模中，能够制造出光刻胶蚀刻掩模。该光刻胶蚀刻掩模可安置成使得保护层180、CESL175、氧化膜170、ILD160和CESL150的部分未由该光刻胶蚀刻掩模所保护以便提供接触孔C。
保护层180、接触蚀刻终止层(CESL)175、氧化膜170、层间介电层(ILD)160以及接触蚀刻终止层(CESL)150的曝光部分随后被去除以形成接触孔C。在一些实施例中，源极/漏极区135的一些部分同样被去除以分别在源极/漏极区135中形成凹槽R。该凹槽R分别与接触孔C连通。
在一些实施例中，接触孔C和凹槽R使用干法蚀刻与湿法蚀刻的组合来形成。具体地，保护层180、接触蚀刻终止层(CESL)175、氧化膜170、层间介电层(ILD)160以及接触蚀刻终止层(CESL)150的曝光部分可使用诸如反应性离子蚀刻(RIE)的干法蚀刻被去除以形成接触孔C。然后，源极/漏极区135的部分可使用湿法蚀刻去除以形成凹槽R。
在形成凹槽R之后，氧化物可形成在凹槽R的侧壁S和底表面B上。该氧化物是用于形成凹槽R的蚀刻的副产品并且具有小于约的厚度。至少在凹槽R的侧壁S上的氧化物被物理性地去除或清洁。在一些实施例中，借助惰性气体使用溅射来去除凹槽R的侧壁S上的氧化物，诸如氩溅射。在一些实施例中，凹槽R的底表面B上的氧化物同样通过溅射而被去除或清洁。
参照图10。根据一些实施例，介电间隔件衬垫(DSL)层190共形地形成在保护层180上、接触孔C的侧壁上以及凹槽R的侧壁S和底表面B上。该DSL层190构造成保护接触孔C的侧壁免于被随后的预非晶化注入(PAI)工艺损坏。该DSL层190例如由碳氧化硅(SiOC)、氮氧化硅(SiON)、二氧化硅(SiO2)、氮化硅(SiN)、其他合适的材料或上述的组合制成。该DLS层190例如通过原子层沉积(ALD)或其他合适的工艺形成。
在一些实施例中，介电间隔件衬垫(DSL)层190是共形沉积层。术语“共形沉积层”表示具有以下厚度的层：该厚度不偏离大于或小于该层的平均厚度值的20％。
由于凹槽R的侧壁S上的氧化物被物理性地去除或清洁，介电间隔件衬垫(DSL)层190能够形成在凹槽R的侧壁S上。该凹槽R的侧壁S上的DSL层190构造成防止随后的工艺中使用的蚀刻剂穿过DSL层190、源极/漏极区135、栅极间隔件140和/或衬底110以损坏栅极堆叠件120。
参照图11。执行蚀刻工艺以去除凹槽R的底表面B上的介电间隔件衬垫(DSL)层190以便曝光源极/漏极区135的部分。该蚀刻工艺例如包括氩等离子体蚀刻工艺。
然后，可执行清洁工艺以从凹槽R的底表面B上的介电间隔件衬垫(DSL)层190的蚀刻工艺清洁残余物。该清洁工艺例如包括使用包含NH4OH、H2O2和H2O的清洁溶液的氢氧化铵-双氧水-水混合物(APM)清洁工艺。
可执行预非晶化注入(PAI)工艺以降低掺杂沟道效应并增强掺杂剂活性。在一些实施例中，使用硅、锗或碳。在替代实施例中，使用诸如氖、氩、氪、氙和/或氡的惰性气体。该PAI工艺防止随后掺杂的杂质沟道穿过晶格结构内的间隙并到达比期望更大的深度。源极/漏极区135的曝光并定位在凹槽R的底表面B上的部分由于PAI工艺而转变成非晶态。
参照图12。含金属材料137形成在凹槽R上。含金属材料137可沉积在介电间隔件衬垫(DSL)层190上和凹槽R的底表面B上。在一些实施例中，含金属材料137是共形沉积层。在替代实施例中，含金属材料137填充凹槽R。
含金属材料137可使用物理汽相沉积(PVD)或化学汽相沉积(CVD)来沉积。适于形成含金属材料137的PVD的实例包括溅射和电镀。在一些实施例中，含金属材料137可包括镍或镍铂合金。在替代实施例中，含金属材料137可包括钴(Co)、钨(W)、钛(Ti)、钽(Ta)、铝(Al)、铂(Pt)、镱(Yb)、钼(Mo)、铒(Er)或上述的组合。含金属材料137可具有在从约5nm至约20nm的范围中的厚度。在替代实施例中，含金属材料137可具有从约6nm至约15nm的范围中的厚度。
参照图13。在沉积含金属材料137之后，该结构经历退火步骤，包括但不限于快速热退火(RTA)。在退火步骤期间，所沉积的含金属材料137与源极/漏极135的邻近凹槽R的部分反应形成金属半导体合金触点139(诸如金属硅化物)。在一些实施例中，在从约1s至约90s范围的时间段内、在从约350℃至约600℃的温度下执行退火步骤。
在退火步骤之后，将未转化成金属半导体合金触点139的剩余的含金属材料(此后称作未反应含金属材料)去除。该未反应含金属材料可通过蚀刻工艺来去除，其对于金属半导体合金触点139是选择性的。该蚀刻工艺科包括湿法蚀刻、干法蚀刻或上述的组合。在一些实施例中，该未反应含金属材料通过湿法蚀刻去除。选择诸如热磷酸的蚀刻剂来去除该未反应含金属材料。
由于介电间隔件衬垫(DSL)层190形成在凹槽R的侧壁S上，并且该DSL层190是由能够防止未反应含金属材料的湿法蚀刻中使用的蚀刻剂穿过的材料制成。因此，该蚀刻剂被阻止穿过DSL层190、源极/漏极区135、栅极间隔件140和/或衬底110而损坏该栅极堆叠件120。
参照图14。势垒层197形成在介电间隔件衬垫(DSL)层190和金属半导体合金触点139上。势垒层197由能够将接触孔C中的导体黏附至DSL层190并且阻止该导体扩散到DSL层190中的材料制成。在一些实施例中，当接触孔C中的导体由钨(W)制成时，该势垒层197例如由氮化钛(TiN)、钛(Ti)/TiN、Ti或其他过渡金属基材料或上述的组合制成。势垒层197例如通过物理汽相沉积(PVD)、电离物理汽相沉积(IPVD)、原子层沉积(ALD)、化学汽相沉积(CVD)或上述的组合形成。
导体199过填充该接触开口C。导体199由诸如钨(W)或其他合适的导电材料的金属制成。该导体199例如通过电化学沉积、物理汽相化学沉积(PVD)、化学汽相沉积(CVD)或上述的组合形成。
图15图示出了平坦化步骤，其例如使用化学机械抛光(CMP)来执行。执行该CMP以去除接触孔C外侧和保护层180的顶表面之上的导体199、势垒层197和DSL层195。在CMP之后，剩余在接触孔C中的导体199和势垒层197形成接触塞，其电连接至金属半导体合金触点139和源极/漏极区135。
对于上面示出的实施例应当理解，可执行另外的工艺以完成半导体器件的制造。例如，这些另外的工艺可包括互连结构(例如，提供与半导体器件的电气互连的线和通孔、金属层以及层间介电层)的形成、钝化层的形成、以及半导体器件的封装。
上述半导体器件的实施例在介电间隔件衬垫(DSL)层190形成之前去除凹槽R的侧壁S上的氧化物。因此，该DSL层190能够形成在凹槽R的侧壁S上。该DSL层190可以由能够防止在后续的未反应含金属材料的湿法蚀刻中使用的蚀刻剂穿过的材料制成。因此，在未反应含金属材料的湿法蚀刻期间，蚀刻剂被阻挡穿过DSL层190、源极/漏极区135、栅极间隔件140和/或衬底110而损坏栅极堆叠件120。
根据本发明的一些实施例，一种半导体结构包括半导体衬底、至少一个介电层、介电间隔件衬垫(DSL)层和至少一个导体。该介电层存在于半导体衬底上。该介电层具有至少一个接触孔，其曝光半导体衬底的至少一部分。该半导体衬底具有与接触孔连通的至少一个凹槽。该凹槽具有底表面和至少一个侧壁。该DSL层存在于凹槽的至少该侧壁上。该导体至少部分地存在于接触孔中并且电连接至半导体衬底。
根据本公开的替代实施例，一种用于制造半导体结构的方法包括在半导体衬底上形成至少一个介电层。至少一个接触孔形成在介电层中以曝光半导体衬底的至少一部分。至少一个凹槽形成在半导体衬底中，其中该凹槽与接触孔连通，并且该凹槽具有底表面和至少一个侧壁。至少一个介电间隔件衬垫(DSL)层形成在凹槽的至少该侧壁上。至少一个导体至少部分地形成在接触孔中，其中该导体电连接至半导体衬底。
根据本公开的又一替代实施例，一种用于制造半导体结构的方法包括在半导体衬底中形成至少一个源极/漏极区。至少一个介电层形成在至少该源极/漏极区中。至少一个接触孔形成在该介电层中以曝光源极/漏极区的至少一部分，其中形成该接触孔进一步包括在源极/漏极区中形成至少一个凹槽，并且该凹槽具有底表面和至少一个侧壁。该凹槽的至少该侧壁被物理性地清洁。至少一个介电间隔件衬垫(DSL)层形成在介电层、接触孔和凹槽上。位于凹槽的底表面上的DSL层被去除。至少一个导体形成在该接触孔中，其中该导体电连接至源极/漏极区。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种半导体结构，包括：
半导体衬底；
至少一个介电层，存在于所述半导体衬底上，所述介电层具有曝光所述半导体衬底的至少一部分的至少一个接触孔，其中所述半导体衬底具有与所述接触孔连通的至少一个凹槽，并且所述凹槽具有底表面和至少一个侧壁；
介电间隔件衬垫(DSL)层，至少存在于所述凹槽的所述侧壁上；
势垒层，位于所述介电间隔件衬垫层上，所述介电间隔件衬垫层比所述势垒层更深地延伸至所述半导体衬底中；以及
至少一个金属半导体合金触点，存在于所述凹槽中，其中，所述至少一个金属半导体合金触点的顶面高于所述介电间隔件衬垫层的位于所述凹槽的侧壁上的部分的底面；
至少一个导体，至少部分地存在于所述接触孔中并且电连接至所述半导体衬底。
2.根据权利要求1所述的半导体结构，
其中所述导体通过所述金属半导体合金触点电连接至所述半导体衬底。
3.根据权利要求2所述的半导体结构，其中，所述介电间隔件衬垫层由防止在所述金属半导体合金触点的形成中使用的蚀刻剂穿过的材料制成。
4.根据权利要求1所述的半导体结构，其中，所述介电间隔件衬垫层由碳氧化硅(SiOC)、氮氧化硅(SiON)、二氧化硅(SiO2)、氮化硅(SiN)或上述的组合制成。
5.根据权利要求1所述的半导体结构，其中，所述介电间隔件衬垫层进一步存在于所述接触孔的至少一个侧壁上。
6.根据权利要求1所述的半导体结构，其中，所述半导体衬底具有位于其中的至少一个应力源，所述接触孔曝光所述应力源的至少一部分，并且所述凹槽存在于所述应力源中。
7.一种用于制造半导体结构的方法，所述方法包括：
在半导体衬底上形成至少一个介电层；
在所述介电层中形成至少一个接触孔，以曝光所述半导体衬底的至少一部分；
在所述半导体衬底中形成至少一个凹槽，其中，所述凹槽与所述接触孔连通，并且所述凹槽具有底表面和至少一个侧壁；
至少在所述凹槽的所述侧壁上形成至少一个介电间隔件衬垫(DSL)层；
至少在所述凹槽中形成含金属材料；
将所述含金属材料和所述半导体衬底的邻近所述凹槽的一部分转变成金属半导体合金触点；
在所述至少一个介电间隔件衬垫层上形成至少一个势垒层，其中，所述至少一个介电间隔件衬垫层比所述至少一个势垒层更深地延伸至所述半导体衬底中；以及
至少部分地在所述接触孔中形成至少一个导体，其中所述导体电连接至所述半导体衬底；
其中，所述金属半导体合金触点的顶面高于所述介电间隔件衬垫层的位于所述凹槽的侧壁上的部分的底面。
8.根据权利要求7所述的方法，进一步包括：
在形成所述介电间隔件衬垫层之前，至少去除所述凹槽的所述侧壁上的氧化物。
9.根据权利要求8所述的方法，其中，所述氧化物被物理性地去除。
10.根据权利要求8所述的方法，其中，所述氧化物借助惰性气体通过溅射去除。
11.根据权利要求8所述的方法，其中，所述氧化物通过氩溅射去除。
12.根据权利要求7所述的方法，进一步包括：
去除未转变成所述金属半导体合金触点的剩余的含金属材料。
13.根据权利要求12所述的方法，其中，所述介电间隔件衬垫层由防止在去除所述剩余的含金属材料中使用的蚀刻剂穿过的材料制成。
14.根据权利要求7所述的方法，其中，所述介电间隔件衬垫层由碳氧化硅(SiOC)、氮氧化硅(SiON)、二氧化硅(SiO2)、氮化硅(SiN)或上述的组合制成。
15.根据权利要求7所述的方法，其中，形成所述介电间隔件衬垫层进一步在所述接触孔的至少一个侧壁上形成所述介电间隔件衬垫层。
16.一种用于制造半导体结构的方法，所述方法包括：
在半导体衬底中形成至少一个源极/漏极区；
至少在所述源极/漏极区上形成至少一个介电层；
在所述介电层中形成至少一个接触孔以曝光所述源极/漏极区的至少一部分，其中形成所述接触孔进一步在所述源极/漏极区中形成至少一个凹槽，并且所述凹槽具有底表面和至少一个侧壁；
物理性地清除所述凹槽的至少所述侧壁；
在所述介电层、所述接触孔和所述凹槽上形成至少一个介电间隔件衬垫(DSL)层；
去除所述凹槽的所述底表面上的所述介电间隔件衬垫层；
至少在所述凹槽中形成含金属材料；
将所述含金属材料和所述源极/漏极区的邻近所述凹槽的一部分转变成金属半导体合金触点；
在所述介电间隔件衬垫层上形成势垒层，所述介电间隔件衬垫层比所述势垒层更深地延伸至所述源极/漏极区中；以及
在所述接触孔中形成至少一个导体，其中所述导体电连接至所述源极/漏极区；
其中，所述金属半导体合金触点的顶面高于所述介电间隔件衬垫层的位于所述凹槽的侧壁上的部分的底面。
17.根据权利要求16所述的方法，其中，所述物理性地清除将所述凹槽的至少所述侧壁上的氧化物去除。
18.根据权利要求16所述的方法，进一步包括：
在所述半导体衬底上形成至少一个栅极堆叠件。
19.根据权利要求18所述的方法，进一步包括：
借助蚀刻剂去除未转变成所述金属半导体合金触点的剩余的含金属材料；以及
通过所述介电间隔件衬垫层阻挡所述蚀刻剂进入到所述栅极堆叠件中。
20.根据权利要求18所述的方法，其中，所述栅极堆叠件是含金属栅极堆叠件。
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