CN106057797A - 混合型有源‑场间隙延伸漏极mos晶体管 - Google Patents

混合型有源‑场间隙延伸漏极mos晶体管 Download PDF

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CN106057797A
CN106057797A CN201610377205.0A CN201610377205A CN106057797A CN 106057797 A CN106057797 A CN 106057797A CN 201610377205 A CN201610377205 A CN 201610377205A CN 106057797 A CN106057797 A CN 106057797A
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S·P·彭哈卡
J·林
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Abstract

一种集成电路(100)包括具有并行交替的有源间隙漂移区和场间隙漂移区的延伸漏极MOS晶体管(102)。延伸漏极MOS晶体管包括在场间隙漂移区上具有场板的栅极。延伸漏极MOS晶体管可以以对称嵌套配置形成。用于形成包含延伸漏极MOS晶体管的集成电路的工艺提供并行交替的有源间隙漂移区和场间隙漂移区，其中栅极在场间隙漂移区上具有场板。

Description

混合型有源-场间隙延伸漏极MOS晶体管
本申请是于2011年10月26日提交的名称为“混合型有源-场间隙延伸漏极MOS晶体管”的中国专利申请201180051651.8(PCT/US2011/057843)的分案申请。
技术领域
本发明涉及集成电路，更具体地涉及集成电路中的延伸漏极MOS晶体管。
背景技术
集成电路可以包括延伸漏极金属氧化物半导体(MOS)晶体管，其中在漏极区中的漂移区邻近沟道区，这类晶体管例如横向扩散金属氧化物半导体(LDMOS)晶体管、双扩散金属氧化物半导体(DMOS)晶体管或漏极延伸金属氧化物半导体(DEMOS)晶体管。通常，漂移区中的平均掺杂小于MOS晶体管的源极区中的平均掺杂密度的一半。漂移区由栅极延伸场板覆盖的延伸漏极MOS晶体管(有时被称为场间隙MOS晶体管)可以展示出高于10伏的击穿电压，但由于漏极中的场氧化物元件终止场板，因此在漏极中可能具有不期望大的电阻。在漂移区上没有场板的延伸漏极MOS晶体管(有时称为有源间隙MOS晶体管)由于在栅极边缘处产生热载流子，因此可能不期望地展示出低于10伏的击穿电压和退化的可靠性。
发明内容
集成电路可以包括具有并行交替的有源间隙漂移区和场间隙漂移区的延伸漏极MOS晶体管。延伸漏极MOS晶体管包括在场间隙漂移区上方具有场板的栅极。可以形成对称嵌套配置的延伸漏极MOS晶体管。公开了形成集成电路的工艺。
附图说明
图1A和图1B是以连续制造阶段描绘的、包含根据实施例形成的混合型有源-场间隙延伸漏极MOS晶体管的集成电路的透视图。
图2是包含根据另一个实施例形成的混合型有源-场间隙延伸漏极MOS晶体管的集成电路的透视图。
图3是包含根据其他实施例形成的混合型有源-场间隙延伸漏极MOS晶体管的集成电路的透视图。
图4A和图4B分别是集成电路的顶视图和剖视图，该集成电路包含根据实施例以对称嵌套配置形成的混合型有源-场间隙延伸漏极MOS晶体管。
具体实施方式
集成电路可以包括具有多个并行交替的有源间隙漂移区和场间隙漂移区的混合型有源-场间隙延伸漏极MOS晶体管。场板是栅极的延伸部分。场板终止于延伸漏极MOS晶体管的漏极中的场氧化物元件。
图1A和图1B示出以连续制造阶段描绘的、包含根据实施例形成的混合型有源-场间隙延伸漏极MOS晶体管102的集成电路100。集成电路100形成在衬底104中和在其上，该衬底可以为单晶硅晶片、绝缘体上硅(SOI)晶片、具有不同晶向区域的混合晶向技术(HOT)晶片或其他适用于制造集成电路100的材料。在衬底104中紧靠延伸漏极MOS晶体管102的沟道区108形成延伸漏极MOS晶体管102的延伸漏极106。延伸漏极106包括漂移区110。延伸漏极106可以由例如包括以下步骤的工艺形成：在衬底104上通过光刻工艺形成光刻胶的离子注入掩模，以便暴露延伸漏极106的区域；将掺杂剂离子注入到衬底104中由离子注入掩模暴露的区域中；移除离子注入掩模；以及对衬底104进行退火，以便激活注入的掺杂剂。在延伸漏极106中邻近漂移区110形成场氧化物元件112。场氧化物112可以是例如主要由250到600纳米厚的二氧化硅构成。场氧化物元件112可以通过如图1A描绘的浅槽隔离(STI)工艺、硅局部氧化(LOCOS)工艺或其他方法形成。STI工艺可以包括以下步骤：在衬底104上形成氧化层；在氧化层上形成氮化硅层；图形化氮化硅层，以便暴露场氧化物112的一区域；在衬底中暴露的区域中刻蚀槽至一合适深度，以便得到期望厚度的场氧化物112；在槽的侧壁和底部上生长热氧化物层；通过化学气相淀积(CVD)、高密度等离子体(HDP)或高纵横比工艺(HARP)用二氧化硅填充槽；从氮化硅层的顶表面去除不需要的二氧化硅；以及去除氮化硅层。LOCOS工艺可以包括以下步骤：在衬底104上形成氧化层；在氧化层上形成氮化硅层；图形化氮化硅层，以便暴露场氧化物112的一区域；在暴露的区域中衬底104的顶表面上生长热氧化层至一合适厚度，以便得到期望厚度的场氧化物112；以及去除氮化硅层。
延伸漏极106在场氧化物元件112的下面延伸。在本实施例的替代版本中，可以在形成延伸漏极106之前形成场氧化物元件112。
参考图1B，在衬底104上沟道区108和漂移区110上方形成栅极介电层114。栅极介电层114可以是例如二氧化硅、氮氧化硅、氧化铝、氮氧化铝、氧化铪、硅酸铪、铪硅氧氮化物、氧化锆、硅酸锆、锆硅氧氮化物、上述材料的组合或其他绝缘材料的一层或多层。由于在50℃到800℃之间的温度下暴露于含氮的等离子体或含氮的环境气体，因此栅极介电层114可能包括氮。栅极介电层114的厚度可以为每伏栅源偏压2.5到3.0纳米。可以通过多种栅极电介质形成工艺中的任何一种来形成栅极介电层114，例如热氧化、氧化物层的等离子体氮化和/或通过原子层淀积(ALD)的介电材料淀积。
在栅极介电层114上形成延伸漏极MOS晶体管102的栅极116，以便暴露漂移区110的有源间隙区118，并且在有源间隙区118间形成延伸至场氧化物元件112上的场板120。栅极116可以通过例如包括以下步骤的工艺形成：在栅极介电层114上方形成栅极材料层，例如多晶的硅，通常被称为多晶硅；利用光刻工艺在栅极材料层上方形成包括光刻胶的栅极刻蚀掩模，以便覆盖栅极116的一区域；通过反应离子刻蚀(RIE)工艺执行栅极刻蚀工艺，RIE工艺从由栅极刻蚀掩模暴露的区域中的栅极材料层去除材料；以及去除栅极刻蚀掩模。
漂移区110在场板120下面的区域为场间隙漂移区。本实施例的一个版本中，相邻场板120间的每个有源间隙区118的有源间隙宽度122小于2微米。在其他版本中，每个有源间隙区118的有源间隙宽度122小于1微米。可以在栅极116的侧表面上形成栅极侧壁间隔层。
在延伸漏极106中紧靠有源间隙区118和场氧化物元件112形成漏极接触扩散区124。在衬底104中紧靠沟道区108且在延伸漏极106对面形成延伸漏极MOS晶体管102的源极126。漏极接触扩散区124和源极126可以例如通过包括以下步骤的工艺同时形成：通过光刻工艺在集成电路100的现有顶表面上形成光刻胶的离子注入掩模，以便暴露漏极接触扩散区124的一区域和源极126的一区域；将掺杂剂离子注入到衬底104中由离子注入掩模暴露的区域中；去除离子注入掩模；以及对衬底104进行退火，以便激活注入的掺杂剂。
可以在衬底104中形成背栅接触扩散区128，以便与沟道区108电连接。背栅接触扩散区128(如果形成)可以如图1B所描绘地分布，或可以是局部的。背栅接触扩散区128可以例如通过包括以下步骤的工艺形成：通过光刻工艺在集成电路100的现有顶表面上方形成光刻胶的离子注入掩模，以便暴露背栅接触扩散区128的一区域；将掺杂剂离子注入到衬底104中由离子注入掩模暴露的区域中；去除离子注入掩模；以及对衬底104进行退火，以便激活注入的掺杂剂。
在源极126上和可选地在背栅接触扩散区128(如果存在)上形成源极触点130。在漏极接触扩散区124上形成漏极触点132。在本实施例的一个版本中，邻近每个有源间隙区118且邻近每个场氧化物元件112，与重叠场氧化物元件112的每个场板120相对地形成每个漏极触点132。触点130和132可以例如通过包括以下步骤的工艺形成：用通过光刻工艺形成的触点光刻胶图形，在衬底104上方预金属介电(PMD)层的顶表面上定义触点区域；通过利用RIE工艺去除PMD层材料来刻蚀触点区域中的接触孔，以暴露衬底104；以及用接触衬垫金属(例如钛)和接触填充金属(通常是钨)来填充接触孔，然后用刻蚀和/或CMP方法从PMD层的顶表面去除接触填充金属。
在延伸漏极MOS晶体管102的工作期间，有源间隙区118可以提供通过漂移区110的期望阻抗，而场板120可以减小有源间隙区118中的电场，以便提供期望的高击穿电压和期望水平的热载流子可靠性。
在本实施例的一个版本中，延伸漏极MOS晶体管102可以是N沟道，如图1A和图1B所示。在另一个版本中，延伸漏极MOS晶体管102可以是P沟道。
图2示出包含根据另一个实施例形成的混合型有源-场间隙延伸漏极MOS晶体管202的集成电路200。在栅极介电层204上形成延伸漏极MOS晶体管202的栅极206，以便具有锥形的场板208。每个锥形场板208在氧化物元件212上方的漏极末端宽度210比每个锥形场板208在锥形场板208的与对应的场氧化物元件212相对的一侧上的源极末端宽度214小至少100纳米。在本实施例的一个版本中，每个有源间隙区218的源极末端有源间隙宽度216小于2微米。在其他版本中，每个有源间隙区218的源极末端有源间隙宽度216小于1微米。每个锥形场板208的漏极末端宽度210和源极末端宽度214是使得有源间隙区的顶表面上的每个点在场间隙漂移区中的相邻场板的一微米范围内。锥形场板208和有源间隙区218的尺寸可以被调整为提供期望的击穿电压值、导通电流和热载流子可靠性。
在本实施例的一个版本中，延伸漏极MOS晶体管202可以是N沟道，如图2所示。在另一个版本中，延伸漏极MOS晶体管202可以是P沟道。
图3是包含根据其他实施例形成的混合型有源-场间隙延伸漏极MOS晶体管302的集成电路300的透视图。在栅极介电层304上形成延伸漏极MOS晶体管302的栅极306，以便具有倒锥形场板308。每个倒锥形场板308在场氧化物元件312上方的漏极末端宽度310比每个倒锥形场板308在倒锥形场板308的与对应的场氧化物元件312相对的一侧上的源极末端宽度314大至少100纳米。在本实施例的一个版本中，每个有源间隙区318的源极末端有源间隙宽度316小于2微米。在其他版本中，每个有源间隙区318的源极末端有源间隙宽度316小于1微米。倒锥形场板308和有源间隙区318的尺寸可以被调整为提供期望的击穿电压值、导通电流和热载流子可靠性。
在本实施例的一个版本中，延伸漏极MOS晶体管302可以是N沟道，如图3所示。在另一个版本中，延伸漏极MOS晶体管302可以是P沟道。
图4A和4B示出包含根据实施例以对称嵌套配置形成的混合型有源-场间隙延伸漏极MOS晶体管402的集成电路400。参考图4A，延伸漏极MOS晶体管402包括第一部分404和第二部分406。在第一部分404和第二部分406中以交替线性配置在延伸漏极MOS晶体管402的延伸漏极中形成场氧化物元件408，如图4所描绘的。延伸漏极在场氧化物元件408下面延伸且横向经过场氧化物元件408，并且延伸漏极包括在第一部分404中的第一漂移区和在第二部分406中的第二漂移区。延伸漏极MOS晶体管402包括在第一部分404中紧靠第一漂移区的第一沟道区，并且包括在第二部分406中紧靠第二漂移区的第二沟道区，使得第二沟道区位于延伸漏极的与第一沟道区相对的一侧。分别在第一漂移区和第一沟道区上方的栅极介电层上，以及在第二漂移区和第二沟道区上方的栅极介电层上形成第一栅极部件410和第二栅极部件412。第一栅极部件410和第二栅极部件412可以在延伸漏极MOS晶体管402的一端或两端处可选地连接。第一栅极部件410包括第一场板414，其延伸到场氧化物元件408上。第一场板414覆盖第一部分404中的第一场间隙漂移区，其与第一有源间隙区416交替。第二栅极部件412包括第二场板418，其延伸到场氧化物元件408上。第二场板418覆盖第二部分406中的第二场间隙漂移区，其与第二有源间隙区420交替。第一场板414与第二有源间隙区420对齐，且第二场板418与第一有源间间隙区416对齐。在本实施例的一个版本中，相邻的第一场板414之间的每个第一有源间隙区416的有源间隙宽度和相邻的第二场板418之间的每个第二有源间隙区420的有源间隙宽度小于2微米。在其他版本中，每个第一有源间隙区域416和每个第二有源间隙区420的有源间隙宽度小于1微米。
在第一部分404中紧靠第一沟道区且邻近第一栅极部件410形成第一源极422。可以邻近第一源极422形成第一背栅接触扩散区424，以便与第一沟道区电连接。在第二部分406中紧靠第二沟道区且邻近第二栅极部件412形成第二源极426。可以邻近第二源极426形成第二背栅接触扩散区428，以便与第二沟道区电连接。在延伸漏极中紧靠第一有源间隙区416和第二有源间隙区420且紧靠场氧化物元件408形成漏极接触扩散区430。
在漏极接触扩散区430上邻近第一有源间隙区416和第二有源间隙区420形成漏极触点432，使得每个漏极触点432提供漏极电流给对应的邻近有源间隙区416或420以及与有源间隙区相对的对应的场间隙漂移区。在本实施例的一个版本中，邻近每个第一有源间隙区416和每个第二有源间隙区420形成漏极触点432。在第一源极422上并且可选地在第一背栅接触扩散区424(如果存在)上形成第一源极触点434。在第二源极426上并且可选地在第二背栅接触扩散区428(如果存在)上形成第二源极触点436。可以调整场氧化物元件408、第一有源间隙区416和第二有源间隙区420、第一场间隙漂移区和第二场间隙漂移区以及漏极接触扩散区430的尺寸和位置，从而降低延伸漏极MOS晶体管402的总面积，同时提供期望的导通电流、期望的击穿电压和期望的热载流子可靠性。
参考图4B，延伸漏极438在衬底440中形成，并且包括第一部分404中的第一漂移区442和第二部分406中的第二漂移区444。第一栅极部件410在第一栅极介电层446上形成，第二栅极部件412在第二栅极介电层448上形成。
在本实施例的一个版本中，延伸漏极MOS晶体管402可以是n沟道，如图4B中示出。在另一个版本中，延伸漏极MOS晶体管402可以是p沟道。
本发明涉及的本领域技术人员应该理解，在不背离本发明的范围的情况下，所描述的示例实施例可以变化，且其它实施例可以实现。

Claims (10)

1.一种集成电路，其包括：
衬底；
延伸漏极金属氧化物半导体(MOS)晶体管，所述延伸漏极MOS晶体管包括：
延伸漏极，其在所述衬底中，所述延伸漏极包括漂移区，所述漂移区包括交替的场间隙漂移区和有源间隙区；
沟道区域，其在所述衬底中，所述沟道区紧靠所述漂移区；
场氧化物元件，其在所述延伸漏极中，邻近所述场间隙漂移区且与所述沟道区相对，使得所述延伸漏极在所述场氧化物元件下面延伸；
栅极介电层，其在所述衬底上，在所述沟道区和所述漂移区上方；
栅极，其在所述栅极介电层上，在所述沟道区上方，所述栅极包括在所述场间隙漂移区上方的场板，所述场板延伸到所述场氧化物元件上；以及
源极，其在所述衬底中，紧靠所述沟道区且邻近所述栅极。
2.根据权利要求1所述的集成电路，其中邻近每个所述有源间隙区存在至少一个漏极触点，并且邻近每个所述场氧化物元件、与重叠所述场氧化物元件的场板相对地存在至少一个漏极触点。
3.根据权利要求1所述的集成电路，其中所述场板具有锥形形状，使得每个所述场板在所述场氧化物元件上方的漏极末端宽度比每个所述场板在所述场板的与所述场氧化物元件相对的一侧上的源极末端宽度小至少100纳米。
4.根据权利要求1所述的集成电路，其中所述场板具有倒锥形形状，使得每个所述场板在所述场氧化物元件上方的漏极末端宽度比每个所述场板在所述场板的与所述场氧化物元件相对的一侧上的源极末端宽度大至少100纳米。
5.根据权利要求1所述的集成电路，其中所述延伸漏极MOS晶体管还包括：
漏极接触扩散区，其在所述延伸漏极中，紧靠所述有源间隙区和所述场氧化物元件；
漏极触点，其在所述漏极接触扩散区上；以及
源极触点，其在所述源极上。
6.一种集成电路，其包括：
衬底；
延伸漏极MOS晶体管，其为对称嵌套配置，所述延伸漏极MOS晶体管包括：
延伸漏极，其在所述衬底中，所述延伸漏极包括所述延伸漏极MOS晶体管的第一部分中的第一漂移区和所述延伸漏极MOS晶体管的第二部分中的第二漂移区，所述第一漂移区包括交替的第一场间隙漂移区和第一有源间隙区，并且所述第二漂移区包括交替的第二场间隙漂移区和第二有源间隙区；
第一沟道区，其在所述第一部分中的所述衬底中，所述第一沟道区紧靠所述第一漂移区；
第二沟道区，其在所述第二部分中的所述衬底中，所述第二沟道区紧靠所述第二漂移区，使得所述第二沟道区位于所述延伸漏极的与所述第一沟道区相对的一侧上；
场氧化物元件，其以交替线性配置设置在所述延伸漏极中，使得所述延伸漏极在所述场氧化物元件下面延伸，并且所述场氧化物元件邻近所述第一场间隙漂移区，与所述第一沟道区相对，且邻近所述第二场间隙漂移区，与所述第二沟道区相对；
栅极介电层，其在所述衬底上，在所述第一沟道区和所述第一漂移区上方，且在所述第二沟道区和所述第二漂移区上方；
第一栅极部件，其在所述栅极介电层上，在所述第一沟道区上方，所述第一栅极部件包括在所述第一场间隙漂移区上方的第一场板，所述第一场板延伸到所述场氧化物元件上；
第二栅极部件，其在所述栅极介电层上，在所述第二沟道区上方，所述第二栅极部件包括在所述第二场间隙漂移区上方的第二场板，所述第二场板延伸到所述场氧化物元件上；
第一源极，其在所述衬底上，紧靠所述第一沟道区且邻近所述第一栅极部件；以及
第二源极，其在所述衬底上，紧靠所述第二沟道区且邻近所述第二栅极部件；
漏极触点，其在所述漏极接触扩散区上，邻近所述第一有源间隙区和所述第二有源间隙区；
第一源极触点，其在所述第一源极上；以及
第二源极触点，其在所述第二源极上。
7.根据权利要求6所述的集成电路，其中所述漏极触点邻近每个所述第一有源间隙区和每个所述第二有源间隙区而形成。
8.根据权利要求7所述的集成电路，其中所述延伸漏极MOS晶体管还包括：
漏极接触扩散区，其在所述延伸漏极中，紧靠所述第一有源间隙区、所述第二有源场区和所述场氧化物元件；
漏极触点，其在所述漏极接触扩散区域上，邻近所述第一有源间隙区和所述第二有源间隙区；
第一源极触点，其在所述第一源极上；以及
第二源极触点，其在所述第二源极上。
9.一种形成集成电路的工艺，其包括：
提供衬底；
通过包括以下步骤的工艺形成延伸漏极MOS晶体管：
在所述衬底中形成延伸漏极，使得所述延伸漏极包括具有交替的场间隙漂移区和有源间隙区的漂移区域，并且所述延伸漏极紧靠所述延伸漏极MOS晶体管的沟道区；
在所述衬底中形成沟道区，使得沟道区紧靠所述漂移区；
在所述延伸漏极中邻近所述场间隙漂移区且与所述沟道区相对地形成场氧化物元件，使得所述延伸漏极在所述场氧化物元件下面延伸；
在所述衬底上所述沟道区和所述漂移区的上方形成栅极介电层；
在所述栅极介电层上所述沟道区的上方形成栅极，使得所述栅极包括在所述场间隙漂移区上方延伸到所述场氧化物元件上的场板；以及
在所述衬底中紧靠所述沟道区且邻近所述栅极形成源极。
10.根据权利要求9所述的工艺，其中邻近每个所述有源间隙区存在至少一个漏极触点，并且邻近每个所述场氧化物元件、与重叠所述场氧化物元件的场板相对地存在至少一个漏极触点。
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