CN106030781A - 柔软包裹的集成电路管芯 - Google Patents

柔软包裹的集成电路管芯 Download PDF

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Publication number
CN106030781A
CN106030781A CN201380081060.4A CN201380081060A CN106030781A CN 106030781 A CN106030781 A CN 106030781A CN 201380081060 A CN201380081060 A CN 201380081060A CN 106030781 A CN106030781 A CN 106030781A
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integrated circuit
circuit lead
soft
substrate
coupled
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CN201380081060.4A
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CN106030781B (zh
Inventor
S·阿尔伯斯
M·斯金纳
H-J·巴斯
P·包姆加特纳
H·戈斯纳
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Intel Corp
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Intel Corp
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Abstract

公开了柔软包裹的集成电路管芯器件以及用于将柔软包裹的集成电路管芯安装到衬底中的方法的各实施例。在一些实施例中，柔软包裹的集成电路管芯器件包括衬底以及以相对于衬底的表面基本上垂直的朝向耦合到衬底的柔软集成电路管芯。

Description

柔软包裹的集成电路管芯
技术领域
此处所描述的各实施例一般涉及集成电路。一些实施例涉及集成电路接合。
背景技术
随着制造商试图缩小电子设备的大小，他们可能发现组合集成电路管芯以便使设备的电子器件更紧凑的方式。连接多个集成电路管芯的一种典型的方式可以是作为层，垂直地层叠管芯，使用通道连接管芯的层之间的电路。这可以导致由较低衬底的电路产生的热量通过层叠的管芯向上扩散。这可能与已经由较高层管芯的电路产生的热量相加，如此，降低了较高层管芯的可靠性。
另一方法可以并排定位管芯，并使用引线接合来连接每一管芯之间的电路。这可能会导致比较长的接合线，这会容易损坏，以及总的封装大小更大。
一般需要在相对较小的封装中组合多个集成电路。
附图简述
图1示出了柔软包裹的集成电路管芯的实施例。
图2示出了围绕集成电路管芯的叠层形成的柔软包裹的集成电路管芯的实施例。
图3示出了带有天线的柔软包裹集成电路管芯的实施例。
图4示出了带有护罩的柔软包裹集成电路管芯的实施例。
图5示出了带有边缘连接的柔软包裹集成电路管芯的实施例。
图6示出了用于将柔软包裹的集成电路管芯连接到另一衬底的方法的实施例。
图7A-7D示出了柔软包裹的集成电路管芯上的层叠的螺柱连接的实施例。
图8示出了对准柱的实施例。
具体实施方式
下列描述和图形充分示出了特定的实施例以使所属领域的技术人员实践它们。其他实施例可以包括结构、逻辑、电的，过程，及其他变化。一些实施例的部分和特征可以被包括在其他实施例的那些部分和特征中，或被它们代替。在权利要求书中阐述的实施例包含那些权利要求书的所有可用的等效内容。
随后的讨论引用了集成电路管芯。术语“集成电路管芯”可以不仅表示电路，而且还表示任何薄膜、衬底(例如，硅)，和/或用于安装电路的其他材料。如此，如此处所使用的，集成电路管芯可包括在衬底、薄膜和/或用于安装电路的任何其他材料上形成的或作为其一部分的电路。
可以通过在分层的结构中垂直地层叠集成电路管芯，组合多个集成电路管芯。然后，集成电路管芯可以使用通道来将第一层上的电路连接到高于和/或低于第一层的其他层上的电路。
此朝向可以导致在较低集成电路管芯上操作的电路的热量传播通过较高的集成电路管芯。当此额外的热量与较高的集成电路管芯的操作电路的热量相加时，可能会导致热量相关的问题以及较高的集成电路管芯中的电路元件的故障率提高。
可以通过在一个或多个水平朝向的集成电路管芯周围包裹相对薄的、垂直朝向的集成电路管芯来减少这些问题。例如，通过将柔软包裹的集成电路管芯的厚度缩小到使它能弯曲和伸缩的厚度(例如，对于Si管芯，小于50μm厚；对于其他管芯或管芯衬底材料，可以应用不同的厚度限制)，可以在一个或多个水平朝向的集成电路管芯的边缘周围外围地以垂直的朝向接合柔软包裹的集成电路管芯。由柔软包裹的集成电路管芯上的电路产生的热量可以向上发出，并离开水平朝向的集成电路管芯。
尽管此处引用了垂直朝向的、柔软包裹的集成电路管芯和水平朝向的集成电路管芯(以及管芯连接到的衬底)，但是，各实施例不限于两个管芯之间的正好垂直的关系。例如，垂直朝向、柔软包裹的集成电路管芯可以相对于它被安装到的衬底或封装以及相对于柔软包裹的集成电路管芯可以外围地包裹的集成电路管芯成90°之外的某一角度。
图1示出了柔软包裹的集成电路管芯100器件的实施例。器件可包括安装在衬底或封装115上的柔软包裹的集成电路管芯100。
柔软包裹的集成电路管芯100可以具有缩小的厚度，以便使它能足够弯曲的以形成弧形、圆弓形、圆圈、椭圆，或某种其他形状。柔软包裹的集成电路管芯100可以包括在薄膜、衬底(例如，硅、锗)，或某种其他管芯材料上形成或作为其一部分的电路(例如，迹线、通道、电子组件)。
柔软包裹的集成电路管芯100可以在封装115内形成，封装115可以提供结构保护、环境保护、护罩，和/或散热器能力中的一项或多项。封装115的底部可以是衬底或可以附接到衬底。封装115可以基本上封闭柔软包裹的集成电路管芯100器件。
图1还示出了水平朝向的集成电路管芯不能用于一些实施例中。例如，可以基本上如图所示那样形成柔软包裹的集成电路管芯100，不用水平朝向的集成电路管芯。在一个实施例中，接合线121可以将柔软包裹的集成电路管芯100中的电路耦合到可以在其上安装电路的衬底或封装115。
可以以完整的电路形成柔软包裹的集成电路管芯100，以便柔软包裹的集成电路管芯100的末端汇合并可以连接在一起。另一实施例可在柔软包裹的集成电路管芯100的末端之间包括间隔，诸如图1所示出的间隔。在这样的实施例中，如果一个或多个电路需要被完成的话，可以使用一个或多个接合线120来跨接间隔并连接电路。在另一个实施例中，柔软包裹的集成电路管芯100可以只形成弧形或弯曲的形状。
在另一个实施例中，柔软包裹的集成电路管芯100可以包括分段的衬底材料(例如，多个链接的较短的段)，其中，每一段可以不足够薄，以分别地柔软，但是一起可以模仿柔软包裹的集成电路管芯100。另一实施例可以使用最初柔软但是然后可以硬化为弧形、弯曲或圆形形状的集成电路管芯100，一旦以所需形状以及位置形成，就不再柔软。
柔软包裹的集成电路管芯100的一侧可以是有源侧111，而另一侧可以是无源侧110。有源侧可包括大部分电子电路，包括电路迹线，和/或电路元件(例如，晶体管、互连、电容器、电阻器，逻辑元件)。无源侧110可包括少量的电子电路。
图2示出了在水平朝向的集成电路管芯200(例如，集成电路管芯叠层、衬底和/或电组件)周围形成的柔软包裹的集成电路管芯100的实施例。集成电路管芯叠层200可以通过焊球以及接合线205，以机械方式以及以电的方式耦合在一起。通道可以以电的方式连接不同的层的管芯和/或衬底的电路。如果封装115的底部包括带有电路的衬底，则水平朝向的集成电路管芯200可以利用一个或多个接合线205耦合到该电路。
柔软包裹的集成电路管芯100的有源侧111的电路可以通过一个或多个接合线203，耦合到水平朝向的集成电路管芯200。柔软包裹集成电路管芯100的有源侧111的电路也可以通过一个或多个接合线121，耦合到衬底和/或封装115上的电路。
图3示出了具有天线300的柔软包裹的集成电路管芯100的实施例。可以将天线300安装在柔软包裹的集成电路管芯100的无源侧110(例如，外侧)。天线300可以通过通道或跳线，以电的方式耦合到有源侧111的电路。天线300也可以通过耦合到通道的接合线310，以电的方式耦合到水平朝向的集成电路管芯200。
天线300可以被配置成向外辐射信号，使水平朝向的集成电路管芯200不受干扰。这可以通过在柔软包裹的集成电路管芯100的天线300和无源侧110之间形成屏蔽层来实现。在一个实施例中，天线300可以是护罩400的一部分或与护罩400相结合，如图4所示。
天线300可以是通过刻蚀过程或金属沉积过程在柔软包裹的集成电路管芯100上形成的金属。天线300也可以是以电的方式和/或以机械方式接合到柔软包裹的集成电路管芯100的表面的天线元件。
图4示出了具有护罩400、401的柔软包裹的集成电路管芯100的实施例。护罩400、401可以是金属护罩，并包括屏蔽柔软包裹的集成电路管芯100的无源表面110以及覆盖柔软包裹的集成电路管芯100的顶部401。
在一个实施例中，只有柔软包裹的集成电路管芯100的无源表面110包括护罩400。在另一个实施例中，只有柔软包裹的集成电路管芯100的顶部401包括护罩401。如前面参考图3所讨论的，顶部护罩401或侧面护罩400可包括形成为屏蔽材料的天线300。
在一些实施例中，柔软包裹的集成电路管芯100可以以某种方式粘结、焊接或接合到封装115，如前面所示。图5示出了使用边缘连接附接到衬底或封装115的柔软包裹的集成电路管芯100的实施例。
例如，多个焊接区域(例如，焊球)可以以特定图案附接到衬底或封装115的顶表面。柔软包裹的集成电路管芯100的下边缘可以具有相同特定图案的多个焊垫501，以便每一焊垫对应于焊球位置。然后，柔软包裹的集成电路管芯100可以降低到衬底或封装115的顶表面上或附近，对应的焊垫501与焊球500匹配。当组件被加热时，焊球500可能会熔化，并当冷却时，熔合到其相关联的焊垫时，如此，将柔软包裹的集成电路管芯100附接到衬底或封装115。
图6示出了用于将柔软包裹的集成电路管芯100连接到衬底或封装115或另一衬底的方法的实施例。可以使用管600来基本上围绕柔软包裹的集成电路管芯100，在柔软包裹的集成电路管芯100附接到封装115的过程中临时地或永久地接合到衬底或者封装115。在引线接合过程中可以使用管600来减少在接合过程中可能发生的断裂。
管600可包括使它能充当散热器的材料。例如，如果管600是金属材料或者利用金属材料作为其表面，管600可以以机械方式耦合到柔软包裹的集成电路管芯100，并从柔软包裹的集成电路管芯100辐射热量。
图7A-7D示出了用于在柔软包裹的集成电路管芯100上创建层叠的螺柱连接705并在层叠的螺柱705和水平朝向的集成电路管芯710之间放置接合线的方法的各实施例。层叠的螺柱连接705可以降低复杂性，并提高引线接合过程的可靠性，因为引线接合机制可能只需要在垂直方向移动。然而，这样的实施例只用于说明目的，因为另一实施例可以在基本上水平的方向将引线接合到柔软包裹的集成电路管芯100。
图7A示出了初始步骤，柔软包裹的集成电路管芯100平放。柔软包裹的集成电路管芯100包括多个焊接垫700-702。在一个实施例中，多个焊接垫700-702位于柔软包裹的集成电路管芯100的有源侧111。
图7B示出了在焊接垫701中的一个上形成的多个焊球(例如，焊球点)的叠层705。在一个实施例中，可以使用金属柱体或单个焊料柱体，而不是多个焊球。
图7C示出了柔软包裹的集成电路管芯100基本上是垂直的朝向并被置于基本上水平的集成电路管芯710的附近。基本上水平的集成电路管芯710可以包括多个焊接垫711、712。
图7D示出了接合线被附接到基本上水平的集成电路管芯710上的叠层705以及焊接垫711之一。线路的结合可以使用已知的使焊料加热，放置线路，并让焊料冷却的过程。
图7A-7D的引线接合过程只用于说明目的。可以使用其他引线接合过程。
图8示出了用于将柔软包裹的集成电路管芯100对齐到柔软包裹的集成电路管芯100耦合到的衬底或封装115的对准柱的实施例。对准柱可以包括位于封装115的角部的多个柱800-803。其他实施例可以放置多于四个的柱800-803和/或放置在封装115的角部之外的不同的位置。
在柔软包裹的集成电路管芯100与其他衬底或封装115的接合过程中，柔软包裹的集成电路管芯100可以被定位在对准柱800-803内。然后，对准柱800-803可以将柔软包裹的集成电路管芯100保持在该位置，直到它永久地附接到封装115。例如，参考图5，由于焊球500和焊垫501的布局，可能需要柔软包裹的集成电路管芯100的准确对准。在柔软包裹的集成电路管芯100永久地附接或留在封装115上之后，可以移除对准柱800-803。
如果对准柱800-803永久地留下，则它们可以用于对准之外的目的。例如，对准柱800-803可以充当散热器，以从柔软包裹的集成电路管芯100、衬底或封装115中去除热量。也可以使用对准柱800-803作为天线、有选择性的护罩和/或改变围绕组件的气流(例如，冷却风扇气流)。
示例：
以下示例关于进一步的实施例。
示例1是集成电路管芯器件，包括衬底以及以相对于衬底的表面基本上垂直的朝向耦合到衬底的柔软集成电路管芯。
在示例2中，示例1的主题可以可任选地包括，其中，所述弯曲的集成电路管芯包括分段的衬底材料，其中包括多个链接的段。
在示例3中，示例1-2的主题可以可任选地包括，其中，所述弯曲的集成电路管芯包括有源侧和无源侧。
在示例4中，示例1-3的主题可以可任选地包括，其中，所述有源侧相对于所述无源侧包括额外的电子电路。
在示例5中，示例1-4的主题可以可任选地包括，将所述弯曲的集成电路管芯上的电子电路耦合到所述衬底上的电路的接合线。
在示例6中，示例1-5的主题可以可任选地包括，以相对于所述柔软集成电路管芯的基本上水平的朝向耦合到所述衬底的至少一个集成电路管芯，其中，所述弯曲的集成电路管芯围绕所述至少一个集成电路管芯的所述周边的至少一部分包裹。
在示例7中，示例1-6的主题可以可任选地包括，其中，所述弯曲的集成电路管芯上的电子电路利用一个或多个接合线，耦合到所述至少一个集成电路管芯。
在示例8中，示例1-7的主题可以可任选地包括，其中，所述弯曲的集成电路管芯以围绕所述至少一个集成电路管芯的所述周边的圆形模式耦合到所述衬底。
在示例9中，示例1-8的主题可以可任选地包括，其中，所述弯曲的集成电路管芯的末端耦合在一起。
在示例10中，示例1-9的主题可以可任选地包括，在所述弯曲的集成电路管芯的无源侧形成的护罩。
示例11是一种柔软包裹的集成电路管芯器件，包括：衬底，耦合到所述衬底的集成电路管芯，以及，柔软集成电路管芯，所述柔软集成电路管芯以相对于所述衬底的表面基本上垂直的朝向耦合到所述衬底，其中，所述柔软集成电路管芯基本上外围地围绕所述集成电路管芯。
在示例12中，示例11的主题可以可任选地包括，其中，耦合到所述衬底的所述集成电路管芯包括多个层叠集成电路管芯。
在示例13中，示例11-12的主题可以可任选地包括，耦合到所述衬底并基本上围绕所述柔软集成电路管芯的管。
在示例14中，示例11-13的主题可以可任选地包括，其中，所述柔软集成电路管芯进一步包括以特定图案围绕所述柔软集成电路管芯的下边缘排列的多个焊垫，每一焊垫都耦合到以所述特定图案耦合到所述衬底的多个焊球中的对应的一个焊球。
在示例15中，示例11-14的主题可以可任选地包括，其中，所述衬底是基本上封闭所述柔软包裹的集成电路管芯器件的封装的一部分。
在示例16中，示例11-15的主题可以可任选地包括，耦合到所述衬底并被配置成将所述柔软集成电路管芯对齐到所述衬底的对准柱。
示例17是一种用于将柔软包裹的集成电路管芯安装到衬底的方法，所述方法包括：在所述衬底上以特定图案提供多个焊料区域；将以所述特定图案在所述柔软包裹的集成电路管芯的下边缘形成的多个焊垫中的每一个与所述多个焊料区域中的相关联的一个对齐；以及，使所述多个焊垫中的每一个与所述多个焊料区域中的与其相关联的一个熔合。
在示例18中，示例17的主题可以可任选地包括，所述柔软包裹的集成电路管芯上的层叠的螺柱；以及，将接合线从所述层叠的螺柱附接到所述衬底。
在示例19中，示例17-18的主题可以可任选地包括，其中，形成所述层叠的螺柱中的每一个都包括在所述柔软包裹的集成电路管芯的焊盘上层叠多个焊球。
在示例20中，示例17-19的主题可以可任选地包括，其中，对齐所述多个焊垫中的每一个都包括使用所述衬底上的对准柱来将所述柔软包裹的集成电路管芯与所述衬底上的焊料区域的所述特定图案对齐。
在示例21中，示例17-20的主题可以可任选地包括，其中，对齐所述多个焊垫中的每一个都包括在附接到所述衬底的管内形成所述柔软包裹的集成电路管芯。
在示例22中，示例17-21的主题可以可任选地包括，用一个或多个接合线将所述柔软集成电路管芯的末端耦合到一起。
示例23是一种柔软包裹的集成电路管芯器件，包括：在底表面上具有衬底的封装；柔软集成电路管芯，所述柔软集成电路管芯以相对于所述衬底的表面基本上垂直的朝向耦合到所述衬底；以及，耦合到所述柔软集成电路管芯的护罩。
在示例24中，示例23的主题可以可任选地包括，其中，所述封装基本上围绕所述柔软集成电路管芯。
在示例25中，示例23-24的主题可以可任选地包括，其中，所述封装包括散热器能力。
在示例26中，示例23-25的主题可以可任选地包括，其中，所述封装包括屏蔽能力。
在示例27中，示例23-26的主题可以可任选地包括，其中，所述护罩包括在所述柔软集成电路管芯的无源侧围绕所述柔软集成电路管芯包裹的护罩。
在示例28中，示例23-27的主题可以可任选地包括耦合到围绕所述柔软集成电路管芯包裹的所述护罩的顶部边缘的顶部护罩。
在示例29中，示例23-28的主题可以可任选地包括耦合到所述衬底的对准柱，所述对准柱包括散热器能力。
在示例30中，示例23-29的主题可以可任选地包括耦合到所述衬底的对准柱，所述对准柱包括所述柱中的至少一个上的天线。
在示例31中，示例23-30的主题可以可任选地包括耦合到所述衬底的对准柱，其中，所述对准柱被配置成围绕所述器件引导冷却空气。
示例32是一种柔软包裹的集成电路管芯器件，包括：在底表面上具有衬底的封装；以一种图案耦合在所述衬底的顶表面上的用于安装的第一装置；以及，柔软集成电路管芯，所述柔软集成电路管芯具有用于安装的第二装置，该第二装置以所述图案沿着下边缘定位，以便所述用于安装的第二装置中的每一个都对应于所述用于安装的第一装置中的一个，所述柔软集成电路管芯以相对于所述衬底的所述顶表面基本上垂直的朝向，耦合到所述衬底。
在示例33中，示例32的主题可以可任选地包括，其中，用于安装的所述第一装置包括多个焊球，用于安装的所述第二装置包括多个焊垫。
在示例34中，示例32-33的主题可以可任选地包括，其中，所述柔软集成电路管芯具有2–25mm的范围的厚度。
在示例35中，示例32-34的主题可以可任选地包括，其中，所述柔软集成电路管芯包括天线。

Claims (20)

1.一种集成电路管芯器件，包括：
衬底；以及
以相对于所述衬底的表面基本上垂直的朝向耦合到所述衬底的弯曲的集成电路管芯。
2.如权利要求1所述的集成电路管芯器件，其中，所述弯曲的集成电路管芯包括分段的衬底材料，所述分段的衬底材料包括多个链接的段。
3.如权利要求1所述的集成电路管芯器件，其中，所述弯曲的集成电路管芯包括有源侧和无源侧。
4.如权利要求3所述的集成电路管芯器件，其中，所述有源侧相对于所述无源侧包括额外的电子电路。
5.如权利要求1所述的集成电路管芯器件，进一步包括将所述弯曲的集成电路管芯上的电子电路耦合到所述衬底上的电路的接合线。
6.如权利要求1所述的集成电路管芯器件，进一步包括以相对于所述弯曲的集成电路管芯的基本上水平的朝向耦合到所述衬底的至少一个集成电路管芯，其中，所述弯曲的集成电路管芯围绕所述至少一个集成电路管芯的周边的至少一部分进行包裹。
7.如权利要求6所述的集成电路管芯器件，其中，所述弯曲的集成电路管芯上的电子电路利用一个或多个接合线，耦合到所述至少一个集成电路管芯。
8.如权利要求6所述的集成电路管芯器件，其中，所述弯曲的集成电路管芯以围绕所述至少一个集成电路管芯的所述周边的圆形模式耦合到所述衬底。
9.如权利要求8所述的集成电路管芯器件，其中，所述弯曲的集成电路管芯的末端耦合在一起。
10.如权利要求1所述的集成电路管芯器件，进一步包括在所述弯曲的集成电路管芯的无源侧形成的护罩。
11.一种柔软包裹的集成电路管芯器件，包括：
衬底；
耦合到所述衬底的集成电路管芯；以及
柔软集成电路管芯，所述柔软集成电路管芯以相对于所述衬底的表面基本上垂直的朝向耦合到所述衬底，其中，所述柔软集成电路管芯基本上外围地围绕所述集成电路管芯。
12.如权利要求11所述的柔软包裹的集成电路管芯器件，其中，耦合到所述衬底的所述集成电路管芯包括多个层叠集成电路管芯。
13.如权利要求11所述的柔软包裹的集成电路管芯器件，进一步包括耦合到所述衬底并基本上围绕所述柔软集成电路管芯的管。
14.如权利要求11所述的柔软包裹的集成电路管芯器件，其中，所述柔软集成电路管芯进一步包括以特定图案围绕所述柔软集成电路管芯的下边缘排列的多个焊垫，每一焊垫都耦合到以所述特定图案耦合到所述衬底的多个焊球中的对应的一个焊球。
15.如权利要求11所述的柔软包裹的集成电路管芯器件，其中，所述衬底是基本上封闭所述柔软包裹的集成电路管芯器件的封装的一部分。
16.如权利要求11所述的柔软包裹的集成电路管芯器件，进一步包括耦合到所述衬底并被配置成将所述柔软集成电路管芯对齐到所述衬底的对准柱。
17.一种用于将柔软包裹的集成电路管芯安装到衬底的方法，所述方法包括：
在所述衬底上以特定图案提供多个焊料区域；
将以所述特定图案在所述柔软包裹的集成电路管芯的下边缘形成的多个焊垫中的每一个与所述多个焊料区域中的相关联的一个对齐；以及
使所述多个焊垫中的每一个与所述多个焊料区域中的与其相关联的一个熔合。
18.如权利要求17所述的方法，进一步包括：
在所述柔软包裹的集成电路管芯上形成层叠的螺柱；以及
将接合线从所述层叠的螺柱附接到所述衬底。
19.如权利要求18所述的方法，其中，形成所述层叠的螺柱中的每一个都包括在所述柔软包裹的集成电路管芯的焊盘上层叠多个焊球。
20.如权利要求17所述的方法，其中，对齐所述多个焊垫中的每一个都包括使用所述衬底上的对准柱来将所述柔软包裹的集成电路管芯与所述衬底上的焊料区域的所述特定图案对齐。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015094259A1 (en) 2013-12-19 2015-06-25 Intel Corporation Flexibly-wrapped integrated circuit die
KR102157942B1 (ko) 2014-09-26 2020-09-21 인텔 코포레이션 플렉시블 패키징 아키텍처
GB2566029B (en) * 2017-08-30 2022-11-02 Pragmatic Printing Ltd Methods and apparatus for manufacturing a plurality of electronic circuits
WO2020092683A1 (en) * 2018-10-31 2020-05-07 Avery Dennison Retail Information Services, Llc Wafer-scale integration with wafers that can be folded into three-dimensional packages

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755891A (en) * 1971-06-03 1973-09-04 S Hawkins Three dimensional circuit modules for thick-film circuits and the like and methods for making same
JPS5228067U (zh) * 1975-08-20 1977-02-26
JPS60109358U (ja) * 1983-12-28 1985-07-25 アルプス電気株式会社 ブロツク基板の接続構造
US4810917A (en) * 1985-05-28 1989-03-07 Autotech Corporation Digital resolver/encoder assembly
JPH08321580A (ja) * 1995-05-25 1996-12-03 Rohm Co Ltd 混成集積回路装置の構造及びその製造方法
JP2001118982A (ja) * 1999-10-19 2001-04-27 Fujitsu Ltd 半導体装置及び半導体集積装置の製造方法
US20010049155A1 (en) * 2000-06-05 2001-12-06 Kabushiki Kaisha Toshiba Semiconductor device using substrate having cubic structure and method of manufacturing the same
CN1338195A (zh) * 1999-01-20 2002-02-27 高压马达乌普萨拉有限公司 柔性微型系统及其制造技术
US6417027B1 (en) * 1999-06-10 2002-07-09 Micron Technology, Inc. High density stackable and flexible substrate-based devices and systems and methods of fabricating
CN1633704A (zh) * 2002-08-09 2005-06-29 富士通株式会社 半导体装置及其制造方法
JP2005183498A (ja) * 2003-12-17 2005-07-07 Fuji Electric Device Technology Co Ltd Ｍｏｓ型半導体装置および該半導体装置の製造方法
US20070001282A1 (en) * 2005-07-01 2007-01-04 Sun-Won Kang Three-dimensional semiconductor module having multi-sided ground block
US7972650B1 (en) * 2005-07-13 2011-07-05 Nscrypt, Inc. Method for manufacturing 3D circuits from bare die or packaged IC chips by microdispensed interconnections

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6714336A (zh) 1967-10-21 1969-04-23
JPH0770681B2 (ja) * 1990-03-29 1995-07-31 三洋電機株式会社 混成集積回路装置
JP2894071B2 (ja) * 1992-03-09 1999-05-24 株式会社日立製作所 半導体装置
JPH08102586A (ja) * 1994-09-30 1996-04-16 Sanyo Electric Co Ltd 混成集積回路装置
JP4604307B2 (ja) 2000-01-27 2011-01-05 ソニー株式会社 撮像装置とその製造方法及びカメラシステム
JP3580749B2 (ja) 2000-02-18 2004-10-27 シャープ株式会社 粒状半導体装置の実装方法
JP4439090B2 (ja) * 2000-07-26 2010-03-24 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
JP3822040B2 (ja) * 2000-08-31 2006-09-13 株式会社ルネサステクノロジ 電子装置及びその製造方法
JP2003347355A (ja) * 2002-05-28 2003-12-05 Matsushita Electric Works Ltd 半導体チップの実装構造
US7439158B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
KR101486984B1 (ko) * 2008-10-30 2015-01-30 삼성전자주식회사 가변 저항 메모리 소자 및 그 형성방법
KR20100058909A (ko) 2008-11-25 2010-06-04 삼성전자주식회사 가변저항 메모리 소자의 형성방법
GB0915473D0 (en) * 2009-09-07 2009-10-07 St Microelectronics Res & Dev Improvements in or relating to CMOS sensors
JP5907633B2 (ja) 2011-05-06 2016-04-26 イリディウム メディカル テクノロジー カンパニー リミテッドＩｒｉｄｉｕｍ Ｍｅｄｉｃａｌ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．，Ｌｔｄ． 非平面チップの組立品
GB201210151D0 (en) * 2012-06-08 2012-07-25 Wfs Technologies Ltd Antenna system
WO2015094259A1 (en) 2013-12-19 2015-06-25 Intel Corporation Flexibly-wrapped integrated circuit die

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755891A (en) * 1971-06-03 1973-09-04 S Hawkins Three dimensional circuit modules for thick-film circuits and the like and methods for making same
JPS5228067U (zh) * 1975-08-20 1977-02-26
JPS60109358U (ja) * 1983-12-28 1985-07-25 アルプス電気株式会社 ブロツク基板の接続構造
US4810917A (en) * 1985-05-28 1989-03-07 Autotech Corporation Digital resolver/encoder assembly
JPH08321580A (ja) * 1995-05-25 1996-12-03 Rohm Co Ltd 混成集積回路装置の構造及びその製造方法
CN1338195A (zh) * 1999-01-20 2002-02-27 高压马达乌普萨拉有限公司 柔性微型系统及其制造技术
US6417027B1 (en) * 1999-06-10 2002-07-09 Micron Technology, Inc. High density stackable and flexible substrate-based devices and systems and methods of fabricating
JP2001118982A (ja) * 1999-10-19 2001-04-27 Fujitsu Ltd 半導体装置及び半導体集積装置の製造方法
US20010049155A1 (en) * 2000-06-05 2001-12-06 Kabushiki Kaisha Toshiba Semiconductor device using substrate having cubic structure and method of manufacturing the same
CN1633704A (zh) * 2002-08-09 2005-06-29 富士通株式会社 半导体装置及其制造方法
JP2005183498A (ja) * 2003-12-17 2005-07-07 Fuji Electric Device Technology Co Ltd Ｍｏｓ型半導体装置および該半導体装置の製造方法
US20070001282A1 (en) * 2005-07-01 2007-01-04 Sun-Won Kang Three-dimensional semiconductor module having multi-sided ground block
US7972650B1 (en) * 2005-07-13 2011-07-05 Nscrypt, Inc. Method for manufacturing 3D circuits from bare die or packaged IC chips by microdispensed interconnections

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