CN105390476A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN105390476A
CN105390476A CN201510514578.3A CN201510514578A CN105390476A CN 105390476 A CN105390476 A CN 105390476A CN 201510514578 A CN201510514578 A CN 201510514578A CN 105390476 A CN105390476 A CN 105390476A
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Prior art keywords
assembly
chip
semiconductor package
package part
layer
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CN201510514578.3A
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CN105390476B (zh
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苏安治
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/470,999 external-priority patent/US9502364B2/en
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Abstract

根据示例性实施例，提供了半导体封装件。半导体封装件包括：芯片，具有多个连接焊盘；组件，在一侧上具有多个金属盖，并且在另一侧上具有研磨表面，其中，金属盖与芯片的连接焊盘接触。本发明的实施例还提供了半导体封装件的形成方法。

Description

半导体封装件及其形成方法
相关申请的交叉引用
本申请是2014年8月28日提交的美国专利申请第14/470,999号的部分继续申请案，其全部内容结合于此作为参考。
技术领域
本发明的实施例涉及集成电路，更具体地，涉及半导体封装件及其形成方法。
背景技术
对于移动应用，形状因数指的是移动设备的尺寸、形状和样式以及组件的布局和位置。消费者更喜欢具有较薄形状因数的设备，从而使设备的制造更困难。因此，需要满足以上需求。
发明内容
本发明的实施例提供了一种半导体封装件，包括：芯片，具有多个连接焊盘；多个柱，连接至所述芯片；组件，具有多个金属盖，所述金属盖与所述芯片的所述连接焊盘接触；以及再分布层，通过所述柱连接至所述芯片。
本发明的另一实施例提供了一种半导体封装件，包括：芯片，具有多个连接焊盘；以及组件，在一侧上具有多个金属盖，并且在另一侧上具有研磨的表面，其中，所述金属盖与所述芯片的所述连接焊盘接触。
本发明的又一实施例一种形成半导体封装件的方法，所述半导体封装件包括芯片和组件，所述方法包括：在载体上方提供临时接合层；在所述临时接合层上方形成绝缘层；在所述绝缘层上方提供粘合层；在所述粘合层上方提供所述芯片；在所述芯片上方提供多个连接焊盘；将具有多个金属凸块和金属盖的所述组件连接至所述连接焊盘；在所述组件上方和邻近所述芯片处过模制模塑料；以及研磨所述模塑料和所述组件以减小所述组件的厚度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的示出示例性半导体封装件的截面图。
图2至图10是根据一些实施例的示出示例性半导体封装件的截面图。
图10是根据一些实施例的示出示例性半导体封装件的截面图。
图11至图19是根据一些实施例的示出示例性半导体封装件的截面图。
图20(a)、图20(b)是根据一些实施例的顶视图，该顶视图示出示例性半导体封装件的后侧再分布层中的焊盘的形状以及通过使用焊料的焊盘与SMD组件的接触。
图21(a)、图21(b)是根据一些实施例的顶视图，该顶视图示出示例性半导体封装件的后侧再分布层中的焊盘的形状以及通过使用焊料的焊盘与SMD组件的接触。
图22(a)、图22(b)是根据一些实施例的顶视图，该顶视图示出示例性半导体封装件的后侧再分布层中的焊盘的形状以及通过使用焊料的焊盘与SMD组件的接触。
图23、图24是根据一些实施例的示出示例性半导体封装件的后侧再分布层中的焊盘的形状的顶视图。
图25是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。
图26是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。
图27至图32是根据一些实施例的示出示例性半导体封装件的截面图。
图33是根据一些实施例的示出示例性半导体封装件的截面图。
图34是根据一些实施例的示出示例性半导体封装件的截面图。
图35至图38是根据一些实施例的示出示例性半导体封装件的芯片和IPD组件之间的连接的截面图。
图39是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。
图40是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
对于移动应用，形状因数指的是移动设备的尺寸、形状和样式以及组件(诸如嵌入式SMD组件和芯片)的布局和位置。消费者更喜欢具有较薄形状因数的设备，这使设备的制造更困难。
本发明提供了将集成无源器件(IPD)集成到集成扇出型(INFO)结构内的新的封装件结构。代替在芯片上方拾取和放置薄IPD组件(例如，50微米)，本发明在芯片上方拾取和放置较厚的IPD组件(例如，100微米)，并且进一步研磨IPD组件以产生较薄IPD组件(例如，50微米)。本发明克服了处理薄IPD组件的问题，薄IPD组件在拾取和放置期间容易损坏。此外，在可靠性不折衷的情况下，IPD组件和芯片之间的短距离将产生更好的电性能。
为了在不牺牲信号完整性的情况下达到较薄的封装件形状因数，可以在衬底(例如，PCB)和芯片之间以及在球栅阵列(“BGA”)球的旁边放置SMD组件。衬底和芯片之间的距离由BGA球确定。SMD组件的高度应该小于BGA球的焊点高度。在一个实施例中，SMD组件的高度为约130-150微米；预焊料的高度为约20微米；并且BGA球的焊点高度为约140-170微米。已经证明，用于放置SMD组件的设计裕度非常紧。因此，为了扩大设计裕度，本发明将SMD嵌入在模塑中。
在一个实施例中，公开了新的封装件结构。封装件中的后侧再分布层(B/SRDL)的一些焊盘设计为具有开口结构。通过使用开口结构，模制材料可以流入SMD组件下方的空间内。芯片可以选自由硅半导体或III-V族半导体组成的组。芯片可以包括微电子机械系统(MEMS)。
图1是根据一些实施例的示出示例性半导体封装件的截面图。如图1所示，在载体102上方涂布临时接合层104。例如，载体102可以由金属或玻璃形成。例如，临时接合层104由胶形成。
在临时接合层104上方形成绝缘层106。例如，绝缘层106可以由环氧化物或聚合物形成。在绝缘层106上方形成后侧再分布层108，然后，通过使用掩模(未示出)图案化后侧再分布层108。例如，用于后侧再分布层108的材料可以包括但不限于Cu、Al、AlCu、Al合金、Cu合金或其他导电材料。
图2是根据一些实施例的示出示例性半导体封装件的截面图。如图2所示，在后侧再分布层108的部分202上方提供预焊料(未示出)。在后侧再分布层108上方提供SMD组件204。预焊料(未示出)设置在SMD组件204和后侧再分布层108的部分202之间。例如，SMD组件204可以是诸如电阻器、电感器或电容器的无源组件。
图3是根据一些实施例的示出示例性半导体封装件的截面图。如图3所示，在后侧再分布层108上方提供芯片302。具体地，芯片302通过粘合层310粘合至后侧再分布层108。芯片302包括管芯303、互连层304、钝化层305和牺牲层306。互连层304包括互连件314。钝化层305包括焊盘315。牺牲层306包括铜(Cu)柱316。管芯303通过互连件314和焊盘315连接至Cu柱316。互连层304可以由低k材料制成。牺牲层306可以由聚合物制成。在实施例中，芯片302可以选自由硅半导体或III-V族半导体组成的组。芯片可以包括微电子机械系统(MEMS)。图4是根据一些实施例的示出示例性半导体封装件的截面图。如图4所示，模塑料402提供在SMD组件204上方并且邻近芯片302。模塑料402可以由二氧化硅、有机材料或环氧树脂制成。可以实施模制步骤以形成围绕SMD组件204并且邻近芯片302的模塑料402。可以从芯片302的顶部部分地去除模塑料402以暴露芯片302的上表面。
图5是根据一些实施例的示出示例性半导体封装件的截面图。如图5所示，在模塑料402中开导通孔502。在实施例中，导通孔502暴露后侧再分布层108。
图6是根据一些实施例的示出示例性半导体封装件的截面图。如图6所示，在模塑料402的导通孔502中提供通孔602，并且通孔602电连接至后侧再分布层108。例如，通孔602可以由铜或锡制成。在实施例中，模塑料402和通孔602的形成包括：首先形成模塑料402；在模塑料402中开导通孔502以暴露后侧再分布层108；以及然后在导通孔502中形成通孔602。在一些实施例中，这种形成可以包括：首先形成通孔602；以及然后形成模塑料402。即，可以改变模塑料402和通孔602的形成顺序。
图7是根据一些实施例的示出示例性半导体封装件的截面图。如图7所示，后侧再分布层108的部分202和后侧再分布层108的部分704是连接的，然后在芯片302和通孔602上方提供前部再分布层702，以通过使用后侧再分布层108、通孔602和前部再分布层702连接芯片302和SMD组件204。由聚苯并恶唑(PBO)层706围绕的前部再分布层702可以包括迹线711和凸块下金属(UBM)712。迹线711的端部可以提供接合焊盘(未示出)。
迹线711和PBO层706可以是单层或堆叠的多层。在具有堆叠的多层的迹线711和PBO层706的实施例中，PBO层706和迹线711的形成可以包括：在芯片302和模塑料402上方形成第一PBO层；蚀刻第一PBO层以及在蚀刻的部分中形成第一迹线层；重复该形成和蚀刻工艺；以及在迹线711的端部(接合焊盘)上方形成UBM712。例如，用于前部再分布层702的材料可以包括但不限于Cu、Al、AlCu、Al合金、Cu合金或其他导电材料。由此，提供了半导体封装件700。SMD组件204放置在模塑料402中并且不放置在BGA球之间。因此SMD组件204不再受到高度的约束，该高度小于BGA球的焊点高度。当不牺牲信号完整性的情况下具有较薄的封装件形状因数时，用于放置SMD组件204的设计裕度松弛。
图8是根据一些实施例的示出示例性半导体封装件的截面图。如图8所示，提供多个金属凸块802，并且金属凸块802通过前部再分布层702连接至芯片302和SMD组件204。例如，可以通过球栅阵列(BGA)焊料凸起实现在前部再分布层702上形成金属凸块802，BGA焊料凸起是表面安装封装的一种类型。
图9是根据一些实施例的示出使用示例性半导体封装件的示例性半导体器件的截面图。如图9所示，从载体102分离半导体封装件700。开半导体封装件700的绝缘层106和临时接合层104。翻转半导体封装件700，并且将半导体封装件700连接至印刷电路板914。
在实施例中，半导体封装件902包括两个堆叠的移动DDR(或LPDDR)904、905和封装衬底903。封装衬底903包括与上述类似的再分布层(未示出)并且通过接合引线906连接至两个移动DDR904、905。金属凸块910提供后侧再分布层108和封装衬底903之间的电连接。因此，半导体封装件902接合至半导体封装件700的后侧再分布层，从而提供了包括半导体封装件700、902的叠层封装件结构900。
图10是根据一些实施例的示出示例性半导体封装件的截面图。如图10所示，在载体1002上方涂布临时接合层1004。例如，载体1002可以由金属或玻璃形成。例如，临时接合层1004由胶形成。
在临时接合层1004上方形成第一绝缘层1006。例如，第一绝缘层1006可以由环氧化物或聚合物形成。在第一绝缘层1006上方形成后侧再分布层1008，然后，通过使用掩模(未示出)图案化后侧再分布层1008。例如，用于后侧再分布层1008的材料可以包括但不限于Cu、Al、AlCu、Al合金、Cu合金或其他导电材料。
图11是根据一些实施例的示出示例性半导体封装件的截面图。如图11所示，在后侧再分布层1008和第一绝缘层1006上方形成第二绝缘层1102。然后，图案化第二绝缘层1102以形成凹槽1106，凹槽1106暴露部分后侧再分布层1008。例如，第二绝缘层1102可以由环氧化物或聚合物形成。将描述用于焊料润湿的细节部分1104。
图12是根据一些实施例的示出示例性半导体封装件的细节部分1104的截面图。如图12所示，在第二绝缘层1102的凹槽1106中提供预焊料1202。另一预焊料1203附接至SMD组件1204。
图13是根据一些实施例的示出示例性半导体封装件的截面图。如图13所示，预焊料1202、1203结合以产生焊料连接，该焊料连接设置在SMD组件1204和后侧再分布层1008的部分1206之间，所以SMD组件1204与第二绝缘层1102的凹槽中的预焊料1202、1203接触。SMD组件1204可以是诸如电阻器、电感器或电容器的无源组件。
图14是根据一些实施例的示出示例性半导体封装件的截面图。如图14所示，在第二绝缘层1102上方提供芯片1402。芯片1402可以选自由硅半导体或III-V族半导体组成的组。芯片可以包括微电子机械系统(MEMS)。
图15是根据一些实施例的示出示例性半导体封装件的截面图。如图15所示，模塑料1502提供在SMD组件1204上方并且邻近芯片1402。模塑料1502可以由二氧化硅、有机材料或环氧树脂制成。可以实施模制步骤以形成围绕SMD组件1204并且邻近芯片1402的模塑料1502。可以从芯片1402的顶部部分地去除模塑料1502以暴露芯片1402的上表面。
在提供模塑料1502之前，去除部分第二绝缘层1102以形成凹槽以及暴露后侧再分布层1008的部分1506，并且在凹槽中填充导电材料1504以用于进一步的电连接。
图16是根据一些实施例的示出示例性半导体封装件的截面图。如图16所示，在模塑料1502中开导通孔1602。
图17是根据一些实施例的示出示例性半导体封装件的截面图。如图17所示，在模塑料1502的导通孔1602中提供通孔1702。
图18是根据一些实施例的示出示例性半导体封装件的截面图。如图18所示，连接后侧再分布层1008的部分1206和部分1506，然后在芯片1402和通孔1702上方提供前部再分布层1802以通过使用后侧再分布层1008、通孔1702和前部再分布层1802来连接芯片1402和SMD组件1204。例如，用于前部再分布层1802的材料可以包括但不限于Cu、Al、AlCu、Al合金、Cu合金或其他导电材料。由此，提供了半导体封装件1800。
SMD组件1204放置在模塑料1502中并且不放置在BGA球之间。所以SMD组件1204不再受到小于BGA球的焊点高度的高度的约束。同时在不牺牲信号完整性的情况下具有较薄的封装件形状因数，用于放置SMD组件1204的设计裕度松弛。
图19是根据一些实施例的示出示例性半导体封装件的截面图。如图19所示，提供多个金属凸块1902，并且多个金属凸块1902通过前部再分布层1802连接至芯片1402和SMD组件1204。此外，从载体1002分离半导体封装件1800。半导体封装件1800可以提供在印刷电路板(未示出)上方并且连接至印刷电路板。
在实施例中，上述工艺的顺序提供了实例并且不限制本发明的范围。存在实现半导体封装件及其形成方法的其他可能性，诸如在模塑料1502之前制造通孔1702的可选顺序。
图20(a)、图20(b)是根据一些实施例的顶视图，该顶视图示出示例性半导体封装件的后侧再分布层中的焊盘的形状以及该焊盘通过使用焊料与SMD组件的接触。如图20(a)所示，在后侧再分布层中提供具有凹口2003的焊盘2002。凹口2003设计为限定焊盘2002的位置。焊盘2002的宽度为约450微米；焊盘2002的长度为约400微米。凹口2003的宽度和长度为约2-10微米。如图20(b)所示，预焊料2006放置在焊盘2002上方以用于连接焊盘2002和SMD组件2004。预焊料2006由凹口2003限制。
图21(a)、图21(b)是根据一些实施例的顶视图，该顶视图示出示例性半导体封装件的后侧再分布层中的焊盘的形状以及该焊盘通过使用焊料与SMD组件的接触。如图21(a)所示，在后侧再分布层中提供具有狭槽2103的焊盘2102。狭槽2103设计为限定焊盘2102的位置。焊盘2102的宽度为约450微米；焊盘2102的长度为约400微米。狭槽2103的宽度为约30-60微米；狭槽2103的长度为约20微米。狭槽的数量不受限制并且基于焊盘设计而改变。如图21(b)所示，预焊料2106放置在焊盘2102上方以用于连接焊盘2102和SMD组件2104。预焊料2106由狭槽2103限制。此外，狭槽的不同形状可以适用于停止焊料润湿扩展。
图22(a)、图22(b)是根据一些实施例的顶视图，该顶视图示出示例性半导体封装件的后侧再分布层中的焊盘的形状以及该焊盘通过使用焊料与SMD组件的接触。如图22(a)所示，在后侧再分布层中提供具有开口结构2203的u形焊盘2202。开口结构2203设计为限定u形焊盘2202的位置。开口结构2203的宽度为约450微米；开口结构2203的长度为约50微米。如图22(b)所示，在u形焊盘2202上方放置预焊料2206以连接u形焊盘2202和SMD组件2204。通过使用开口结构2203，模制材料可以流入SMD组件2204下方的空间内。
图23、图24是根据一些实施例的示出示例性半导体封装件的后侧再分布层中的焊盘的形状的顶视图。为了停止焊料润湿扩展，可以应用狭槽的不同形状和组合，诸如图23中的具有三个对准的狭槽的焊盘2302以及甚至图24中的具有四个狭槽的焊盘2402。
图25是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。如图25所示，提供方法2500。方法2500包括以下操作：在载体上方提供临时接合层(2502)；在临时接合层上方形成绝缘层(2504)；在绝缘层上方形成后侧再分布层(2506)；在部分后侧再分布层上方提供预焊料(2508)；在后侧再分布层上方提供芯片和组件以及使组件与预焊料接触(2510)。
操作2506还包括在后侧再分布层中形成具有凹口的焊盘。操作2506还包括在后侧再分布层中形成具有狭槽的焊盘。操作2506还包括在后侧再分布层中形成具有开口结构的u形焊盘。方法2500还包括提供多个金属凸块，多个金属凸块通过前部再分布层连接至芯片和组件。方法2500还包括：在组件上方并且邻近芯片提供模塑料；在模塑料中开导通孔；在模塑料的导通孔中提供通孔；以及在芯片和通孔上方提供前部再分布层以通过使用后侧再分布层、通孔和前部再分布层连接芯片和组件；从载体分离半导体封装件；以及在印刷电路板上方提供半导体封装件，并且半导体封装件连接至印刷电路板。操作2510还包括在后侧再分布层上方提供表面安装器件(SMD)。操作2504还包括在临时接合层上方形成由聚合物制成的绝缘层。
图26是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。如图26所示，提供方法2600。方法2600包括以下操作：在载体上方提供临时接合层(2602)；在临时接合层上方形成第一绝缘层(2604)；在第一绝缘层上方形成后侧再分布层(2606)；在后侧再分布层上方形成第二绝缘层(2608)；图案化第二绝缘层以形成凹槽，该凹槽暴露部分后侧再分布层(2610)；在第二绝缘层的凹槽中提供预焊料(2612)；在第二绝缘层上方提供芯片和组件以及使组件与第二绝缘层的凹槽中的预焊料接触(2614)。
操作2606还包括在后侧再分布层中形成具有凹口的焊盘。操作2606还包括在后侧再分布层中形成具有狭槽的焊盘。操作2606还包括在后侧再分布层中形成具有开口结构的u形焊盘。方法2600还包括提供多个金属凸块，多个金属凸块通过前部再分布层连接至芯片和组件。方法2600还包括：在组件上方并且邻近芯片提供模塑料；在模塑料和第二绝缘层中开导通孔；在模塑料和第二绝缘层的导通孔中提供通孔；以及在芯片和通孔上方提供前部再分布层以通过使用后侧再分布层、通孔和前部再分布层连接芯片和组件；从载体分离半导体封装件；以及在印刷电路板上方提供半导体封装件，并且半导体封装件连接至印刷电路板。操作2614还包括在第二绝缘层上方提供表面安装器件(SMD)。
根据示例性实施例，提供了一种形成半导体封装件的方法，半导体封装件包括芯片和组件。该方法包括以下操作：在载体上方提供临时接合层；在临时接合层上方形成第一绝缘层；在第一绝缘层上方形成后侧再分布层；在后侧再分布层上方形成第二绝缘层；图案化第二绝缘层以形成凹槽，该凹槽暴露部分后侧再分布层；在第二绝缘层的凹槽中提供预焊料；在第二绝缘层上方提供芯片和组件以及使组件与第二绝缘层的凹槽中的预焊料接触。
根据示例性实施例，提供了一种形成半导体封装件的方法，半导体封装件包括芯片和组件。该方法包括以下操作：在载体上方提供临时接合层；在临时接合层上方形成绝缘层；在绝缘层上方形成后侧再分布层；在部分后侧再分布层上方提供预焊料；在后侧再分布层上方提供芯片和组件以及使组件与预焊料接触。
根据示例性实施例，提供了一种半导体封装件。该半导体封装件包括：后侧再分布层；至少一个组件，设置在后侧再分布层上方并且连接至后侧再分布层；至少一个芯片，邻近至少一个组件；模塑料，设置在至少一个芯片和至少一个组件之间；通孔，设置在模塑料中并且连接至后侧再分布层；以及前部再分布层，设置在芯片和通孔上方，其中，通过使用后侧再分布层、通孔和前部再分布层连接芯片和至少一个组件。
图27是根据一些实施例的示出示例性半导体封装件的截面图。如图27所示，在载体2702上方涂布临时接合层2704。例如，载体2702可以由金属或玻璃形成。例如，临时接合层2704由胶形成。临时接合层2704的厚度可以为约1微米。
在临时接合层2704上方形成绝缘层2706。例如，绝缘层2706可以由环氧化物或聚合物形成。对于每个再分布层(未示出)，绝缘层2706的厚度可以为约4微米至15微米。在绝缘层2706上方形成粘合层2708。例如，粘合层2708可以由聚合物形成。粘合层2708的厚度可以为约10微米至50微米。在粘合层2708上方提供芯片2710。芯片2710通过粘合层2708粘合至绝缘层2706。在实施例中，芯片2710可以选自由硅半导体或III-V族半导体组成的组。芯片2710可以包括微电子机械系统(MEMS)。芯片2710的厚度可以为约50微米至500微米。
在芯片2710上方形成由金属材料制成的连接焊盘2712、柱2714和通孔2716。在实施例中，连接焊盘2712、柱2714和通孔2716由包含铜(Cu)的金属材料制成。连接焊盘2712的厚度可以为约1微米至8微米。连接焊盘2712的宽度可以为约20微米至400微米。柱2714的厚度可以为约70微米至200微米。柱2714的宽度可以为约50微米至300微米。通孔2716的厚度可以为约100微米至250微米。通孔2716的宽度可以为约80微米至300微米。
图28是根据一些实施例的示出示例性半导体封装件的截面图。如图28所示，在连接焊盘2712上方提供集成无源器件(IPD)组件2806，IPD组件2806有金属盖2802和金属凸块2804。在实施例中，金属凸块2804由铜或含铜合金制成。在实施例中，金属盖2802由焊料、镍、金、铜或它们的合金制成。金属盖2802的厚度可以为约10微米至20微米。金属凸块2804的厚度可以为约20微米。IPD组件2806通过金属盖2802、金属凸块2804和连接焊盘2712电连接至芯片2710。IPD组件2806的厚度可以为约100微米至300微米。底部填充物2808围绕连接焊盘2712、IPD组件2806的金属盖2802和金属凸块2804。
图29是根据一些实施例的示出示例性半导体封装件的截面图。如图29所示，在IPD组件2806上并且邻近芯片2710和底部填充物2808过模制模塑料2902。模塑料2902至少覆盖IPD组件2806的顶部、柱2714的顶部和通孔2716的顶部。模塑料2902的厚度可以为约200微米至350微米。例如，模塑料2902的材料可以是环氧化物。
图30是根据一些实施例的示出示例性半导体封装件的截面图。如图30所示，对模塑料2902、IPD组件2806、柱2714和通孔2716实施研磨工艺以在IPD组件2806的顶侧上产生研磨表面3002。研磨工艺减小了模塑料2902的厚度、IPD组件2806的厚度、柱2714的厚度和通孔2716的厚度。例如，IPD组件2806的厚度从约100微米减小至50微米。由此，代替在芯片2710上方拾取和放置薄IPD组件(例如，50微米)，本发明在芯片2710上方拾取和放置较厚的IPD组件(例如，100微米)，并且将IPD组件进一步研磨至较薄的IPD组件(例如，50微米)。本发明克服了处理薄IPD组件的问题，薄IPD组件在拾取和放置期间容易损坏。此外，在可靠性不折衷的情况下，IPD组件2806和芯片2710之间的短距离将产生更好的电性能。
图31是根据一些实施例的示出示例性半导体封装件的截面图。如图31所示，在位于IPD组件2806、柱2714和通孔2716上方的绝缘层3101中提供前部再分布层3102。芯片2710通过柱2714连接至前部再分布层3102。例如，用于前部再分布层3102的材料可以包括但不限于Cu、Al、AlCu、Al合金、Cu合金或其他导电材料。金属凸块3106通过凸块下金属(UBM)3104连接至前部再分布层3102。例如，可以通过球栅阵列(BGA)焊料凸起实现在前部再分布层3102上形成金属凸块3106，BGA焊料凸起是表面安装封装的一种类型。IPD组件2806放置在模塑料2902中并且通过连接焊盘2712连接至芯片2710。IPD组件2806不放置在金属凸块3106之间。因此，IPD组件2806不再受到小于金属凸块3106的焊点高度的高度的约束。
在实施例中，上述工艺的顺序提供了实例并且不限制本发明的范围。存在实现半导体封装件及其形成方法的其他可能性，诸如在模塑料2902之前制造通孔2716的可选顺序。
图32是根据一些实施例的示出示例性半导体封装件的截面图。如图32所示，从图31中的载体2702分离半导体封装件3201。开半导体封装件3201的绝缘层2706。半导体封装件3201被翻转并且连接至另一半导体封装件3202。在实施例中，半导体封装件3202包括两个堆叠的移动DDR(或LPDDR)3204、3205和封装衬底3203。封装衬底3203包括再分布层(未示出)并且通过接合引线3206连接至两个芯片3204、3205。例如，两个芯片3204、3205是移动DDR。金属凸块3210提供通孔2716和封装衬底3203之间的电连接。因此，提供了包括半导体封装件3201、3202的叠层封装件结构3200。
图33是根据一些实施例的示出另一示例性半导体封装件的截面图。如图33所示，提供了类似于结构3200的叠层封装件结构3300。与图32相比，叠层封装件结构3300还包括具有再分布层3304的印刷电路板3306。此外，金属凸块3310通过另一再分布层3318连接至通孔3316。而且，IPD组件3324和芯片3322之间的连接结构3320不利用任何底部填充物，并且模塑料3326围绕金属盖3328。
图34是根据一些实施例的示出另一示例性半导体封装件的截面图。如图34所示，提供了类似于结构3300的另一叠层封装件结构3400。叠层封装件结构3400与结构3300的区别在于具有底部填充物3430的连接结构3420。连接结构3420包括围绕金属盖3428和连接焊盘3432的底部填充物3430。
图35是根据一些实施例的示出示例性半导体封装件的芯片和IPD组件之间的连接的截面图。如图35所示，提供了具有I/O焊盘3512的芯片3510。芯片3510可以选自由硅半导体或III-V族半导体组成的组。芯片3510可以包括微电子机械系统(MEMS)。在芯片3510和I/O焊盘3512上方形成由聚合物制成的绝缘层3520。然后，在绝缘层3520上溅射晶种金属层3530。晶种金属层3530可以由Ti或Cu制成。
图36是根据一些实施例的示出示例性半导体封装件的芯片和IPD组件之间的连接的截面图。如图36所示，在晶种金属层3530上方形成连接焊盘3602。连接焊盘3602的形成可以包括光刻胶涂布、光刻胶曝光、电镀和剥离。连接焊盘3602的厚度可以为约4微米。
图37是根据一些实施例的示出示例性半导体封装件的芯片和IPD组件之间的连接的截面图。如图37所示，在晶种金属层3530上方形成I/O柱3702。I/O柱3702的形成可以包括干光刻胶涂布、光刻胶曝光、电镀和剥离。I/O柱3702的厚度可以为约90微米。
图38是根据一些实施例的示出示例性半导体封装件的芯片和IPD组件之间的连接的截面图。如图38所示，去除晶种金属层3530的除了由连接焊盘3602和I/O柱3702覆盖的那些晶种金属层3530之外的部分，从而暴露绝缘层3520。可以对图38中的连接结构3800实施从图28开始的以下步骤。
图39是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。如图39所示，提供方法3900。方法3900包括以下操作：在载体上方提供临时接合层(3902)；在临时接合层上方形成绝缘层(3904)；在绝缘层上方提供粘合层(3906)；在粘合层上方提供芯片(3908)；在芯片上方提供多个连接焊盘(3910)；将具有多个金属凸块和金属盖的组件连接至连接焊盘(3912)；在组件上方和邻近芯片过模制模塑料(3914)；以及研磨模塑料和组件以减小组件的厚度(3916)。
图40是根据一些实施例的形成包括芯片和组件的半导体封装件的方法的流程图。如图40所示，提供方法4000。方法4000包括以下操作：在载体上方提供临时接合层(4002)；在临时接合层上方形成绝缘层(4004)；通过使用粘合层将芯片附接至绝缘层(4006)；在芯片上方提供多个连接焊盘(4008)；将具有多个金属凸块和金属盖的组件连接至连接焊盘(4010)；提供底部填充物，底部填充物围绕连接焊盘、组件的金属凸块和金属盖(4012)；在组件上方和邻近芯片过模制模塑料(4014)；以及研磨模塑料和组件以减小组件的厚度(4016)。
根据示例性实施例，提供了一种形成半导体封装件的方法，半导体封装件包括芯片和组件。该方法包括以下操作：在载体上方提供临时接合层；在临时接合层上方形成绝缘层；在绝缘层上方提供粘合层；在粘合层上方提供芯片；在芯片上方提供多个连接焊盘；将具有多个金属凸块和金属盖的组件连接至连接焊盘；在组件上方和邻近芯片过模制模塑料；以及研磨模塑料和组件以减小组件的厚度。
根据示例性实施例，提供了一种形成半导体封装件的方法，半导体封装件包括芯片和组件。该方法包括以下操作：在载体上方提供临时接合层；在临时接合层上方形成绝缘层；通过使用粘合层将芯片附接至绝缘层；在芯片上方提供多个连接焊盘；将具有多个金属凸块和金属盖的组件连接至连接焊盘；提供底部填充物，底部填充物围绕连接焊盘、组件的金属凸块和金属盖；在组件上方和邻近芯片过模制模塑料；以及研磨模塑料和组件以减小组件的厚度。
在上述方法中，还包括：在所述芯片上方提供柱；在所述柱上方过模制所述模塑料；以及研磨所述模塑料以暴露所述柱。
在上述方法中，其中，将具有所述金属凸块和所述金属盖的所述组件连接至所述连接焊盘还包括：在所述连接焊盘上方拾取和放置所述组件。
在上述方法中，还包括：在所述芯片上方提供柱；在所述柱上方过模制所述模塑料；以及研磨所述模塑料以暴露所述柱，提供连接至所述柱的再分布层。
在上述方法中，其中，将具有所述金属凸块和所述金属盖的所述组件连接至所述连接焊盘还包括：将集成无源器件连接至所述连接焊盘。
在上述方法中，其中，在所述临时接合层上方形成所述绝缘层还包括：在所述临时接合层上方形成由聚合物制成的所述绝缘层。
在上述方法中，还包括：提供底部填充物，所述底部填充物围绕所述连接焊盘、所述组件的所述金属凸块和所述金属盖。
在上述方法中，其中，将具有所述金属凸块和所述金属盖的所述组件连接至所述连接焊盘还包括：提供厚度为约100微米至300微米的所述组件。
在上述方法中，其中，研磨所述模塑料和所述组件以减小所述组件的厚度还包括：
在上述方法中，还包括：通过球栅阵列金属凸块将堆叠存储器封装件连接至所述芯片。
根据示例性实施例，提供了一种半导体封装件。半导体封装件包括：芯片，具有多个连接焊盘；组件，在一侧上具有多个金属盖，并且在另一侧上具有研磨表面，其中，金属盖与芯片的连接焊盘接触。
在上述半导体封装件中，其中，所述组件包括集成无源器件。
在上述半导体封装件中，还包括：底部填充物，围绕所述连接焊盘和所述组件的所述金属盖。
在上述半导体封装件中，其中，所述组件的厚度为约30微米至80微米。
在上述半导体封装件中，其中，所述组件通过所述金属盖和所述连接焊盘电连接至所述芯片。
根据示例性实施例，提供了一种半导体封装件。半导体封装件包括：芯片，具有多个连接焊盘；多个柱，连接至芯片；组件，具有多个金属盖，金属盖与芯片的连接焊盘接触；以及再分布层，通过柱连接至芯片。
在上述半导体封装件中，其中，所述组件包括集成无源器件。
在上述半导体封装件中，还包括：底部填充物，围绕所述连接焊盘和所述组件的所述金属盖。
在上述半导体封装件中，其中，所述组件的厚度为约30微米至80微米。
在上述半导体封装件中，其中，所述组件在一侧上具有所述金属盖且在另一侧上具有研磨的表面。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体封装件，包括：
芯片，具有多个连接焊盘；
多个柱，连接至所述芯片；
组件，具有多个金属盖，所述金属盖与所述芯片的所述连接焊盘接触；以及
再分布层，通过所述柱连接至所述芯片。
2.根据权利要求1所述的半导体封装件，其中，所述组件包括集成无源器件。
3.根据权利要求1所述的半导体封装件，还包括：
底部填充物，围绕所述连接焊盘和所述组件的所述金属盖。
4.根据权利要求1所述的半导体封装件，其中，所述组件的厚度为约30微米至80微米。
5.根据权利要求1所述的半导体封装件，其中，所述组件在一侧上具有所述金属盖且在另一侧上具有研磨的表面。
6.一种半导体封装件，包括：
芯片，具有多个连接焊盘；以及
组件，在一侧上具有多个金属盖，并且在另一侧上具有研磨的表面，其中，所述金属盖与所述芯片的所述连接焊盘接触。
7.根据权利要求6所述的半导体封装件，其中，所述组件包括集成无源器件。
8.根据权利要求6所述的半导体封装件，还包括：
底部填充物，围绕所述连接焊盘和所述组件的所述金属盖。
9.根据权利要求6所述的半导体封装件，其中，所述组件的厚度为约30微米至80微米。
10.一种形成半导体封装件的方法，所述半导体封装件包括芯片和组件，所述方法包括：
在载体上方提供临时接合层；
在所述临时接合层上方形成绝缘层；
在所述绝缘层上方提供粘合层；
在所述粘合层上方提供所述芯片；
在所述芯片上方提供多个连接焊盘；
将具有多个金属凸块和金属盖的所述组件连接至所述连接焊盘；
在所述组件上方和邻近所述芯片处过模制模塑料；以及
研磨所述模塑料和所述组件以减小所述组件的厚度。
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