CN106024582B - 使用公共释放材料形成多堆叠纳米线 - Google Patents

使用公共释放材料形成多堆叠纳米线 Download PDF

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CN106024582B
CN106024582B CN201610176673.1A CN201610176673A CN106024582B CN 106024582 B CN106024582 B CN 106024582B CN 201610176673 A CN201610176673 A CN 201610176673A CN 106024582 B CN106024582 B CN 106024582B
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E·里欧班端
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Abstract

本公开涉及使用公共释放材料形成多堆叠纳米线。一种用于形成多堆叠纳米线器件的方法，包括在衬底上形成公共释放层，公共释放层包含公共释放材料。方法还包括：在公共释放层的第一部分上形成第一多层堆叠，第一多层堆叠包括通过包含公共释放材料的至少一个层分离的至少两个层；以及在公共释放层的第二部分上形成第二多层堆叠，第二多层堆叠包括通过包含公共释放材料的至少一个层分离的至少两个层。方法还包括：将第一多层堆叠和第二多层堆叠中的每个多层堆叠图案化成一个或多个鳍；以及通过使用公共蚀刻工艺去除公共释放材料来从一个或多个鳍形成两个或更多个堆叠纳米线。

Description

使用公共释放材料形成多堆叠纳米线
技术领域
本申请涉及半导体器件制造领域，并且更特别地涉及形成纳米线。
背景技术
半导体纳米线正在成为纳米技术的主要研究焦点。已经探索了形成包括纳米线的金属氧化物半导体场效应晶体管(MOSFET)的各种方法，包括双材料纳米线的使用，其中使用不同材料的纳米线用于N沟道场效应晶体管(NFET)和P沟道场效应晶体管(PFET)器件。例如，可以使用硅(Si)纳米线作为用于NFET器件的沟道材料，而可以使用硅锗(SiGe)纳米线作为用于PFET器件的沟道材料。作为另一示例，在形成NFET和PFET器件时已经使用多堆叠式(“多堆叠”)纳米线，从而具有增加这些器件的电流承载能力的优点。
发明内容
本发明的实施例提供用于形成纳米线的技术。
例如，在一个实施例中，一种方法包括在衬底上形成公共释放层，公共释放层包含公共释放材料。方法还包括：在公共释放层的第一部分上形成第一多层堆叠，第一多层堆叠包括通过包含公共释放材料的至少一个层分离的至少两个层；以及在公共释放层的第二部分上形成第二多层堆叠，第二多层堆叠包括通过包含公共释放材料的至少一个层分离的至少两个层。方法还包括：将第一多层堆叠和第二多层堆叠中的每个多层堆叠图案化成一个或多个鳍；以及通过使用公共蚀刻工艺去除公共释放材料来从一个或多个鳍形成两个或更多个多堆叠纳米线。在另一示例中，根据以上方法形成多堆叠纳米线器件。在另外的示例中，一种集成电路包括根据以上方法形成的两个或更多个多堆叠纳米线器件。
有利地，本发明的实施例提供使用公共释放层形成双材料纳米线的方法。
本发明的这些以及其它特征、目的和优点根据本发明的说明性实施例的以下详细描述将会变得很清楚，该详细描述将要结合附图来阅读。
附图说明
图1A和1B分别图示根据本发明的实施例的其上沉积有公共释放层的硅衬底的侧视图和俯视图；
图2A和2B分别图示根据本发明的实施例的在公共释放层之上沉积掩模并且选择性地去除其中将要形成PFET的区域之上的掩模之后图1A和1B的结构的侧视图和俯视图；
图3A和3B分别图示根据本发明的实施例的在PFET纳米线堆叠的生长之后图2A和2B的器件的侧视图和俯视图；
图4A和4B分别图示根据本发明的实施例的在NFET纳米线堆叠的生长之后图3A和3B的器件的侧视图和俯视图；
图5A和5B分别图示根据本发明的实施例的在利用硬掩模对鳍的图案化之后图4A和4B的器件的截面和俯视图；
图6A和6B分别图示根据本发明的实施例的在公共释放层的蚀刻之后图5A和5B的器件的截面图和俯视图；
图7A和7B分别图示根据本发明的实施例的在沉积氧化物以隔离纳米线之后图6A和6B的器件的截面图和俯视图；
图8A至图8C分别图示根据本发明的实施例的在硬掩模的去除以及虚设栅极的沉积之后图7A和7B的器件的沿着截面AA截取的截面图、俯视图、以及沿着截面CC截取的截面图；
图9图示根据本发明的实施例的在薄的间隔物在虚设栅极上的沉积之后图8A至图8C的器件的截面图；
图10图示根据本发明的实施例的在蚀刻氧化物的未被虚设栅极覆盖的部分之后图9的器件的截面图；
图11图示根据本发明的实施例的在沉积另一薄的间隔物以填充蚀刻氧化物的未被虚设栅极覆盖的部分所留下的间隙之后的图10的器件的截面图；
图12A至图12C分别图示根据本发明的实施例的在源极/漏极区域的掺杂之后图11的器件的沿着截面AA截取的截面图、俯视图、以及沿着截面CC截取的截面图；
图13A至图13C分别图示根据本发明的实施例的在对绝缘体进行平坦化以及虚设栅极的去除之后图12A至图12C的器件的沿着截面AA截取的截面图、俯视图、以及沿着截面CC截取的截面图；
图14A至图14C分别图示根据本发明的实施例的在氧化物的剩余部分的去除之后图13A至图13C的器件的沿着截面AA截取的截面图、俯视图、以及沿着截面CC截取的截面图；
图15A至图15C分别图示根据本发明的实施例的在栅极的形成之后图14A至图14C的器件的沿着截面AA截取的截面图、俯视图、以及沿着截面CC截取的截面图；以及
图16图示根据本发明的实施例的包括一个或多个多堆叠纳米线器件的集成电路。
具体实施方式
本文中将参考特定方法和装置来描述本发明的说明性实施例。然而，应当理解，本发明不限于本文中说明性地示出和描述的具体方法和装置。相反，本发明的实施例更广泛地涉及用于生成NFET和PFET多堆叠纳米线器件的技术。另外，具有本文中的教示的本领域技术人员将很清楚，可以对所示出的实施例做出在本发明的范围内的大量修改。也就是，并非意图或者应当推断关于本文中所描述的具体实施例的任何限制。
多堆叠Si/SiGe结构可以用于生成多堆叠纳米线器件。这样的多堆叠纳米线器件可以包括一个或多个PFET器件以及一个或多个NFET器件，其中PFET器件包括SiGe纳米线，NFET器件包括Si纳米线。然而，很难使用传统方法形成双材料纳米线器件，因为所使用的释放层(其通常为SiGe)与PFET器件的沟道材料相同。如果使用SiGe释放NFET器件中的Si纳米线，则很难在PFET器件中形成SiGe纳米线。本文中所描述的说明性实施例利用使用公共释放材料用于Si和SiGe纳米线二者的集成方案。
下面将参考图1至图15描述用于形成多堆叠纳米线器件的说明性实施例。结构100到1500中的每个结构图示可以在形成多堆叠纳米线器件的过程中使用的步骤。
图1A和1B是分别图示结构100的形成的侧视图和俯视图，结构100包括具有公共释放层104的Si衬底102。在图1A和1B中，公共释放层104包括沉积到Si衬底102上的磷化镓(GaP)。GaP的晶格结构匹配Si衬底102的晶格结构。然而，实施例不仅仅限于包括GaP的公共释放层104。更一般地，可以使用其它材料，只要公共释放层104的晶格结构匹配Si衬底102的晶格结构，使得公共释放层104能够关于Si和SiGe被选择性地蚀刻。
图2A和2B描绘在形成多堆叠纳米线器件时的下一步骤，其中在结构100的公共释放层104的部分之上形成氧化物硬掩模(HM)106，从而得到结构200。氧化物HM 106初始可以形成在整个公共释放层104之上，并且在其中将要形成PFET堆叠式纳米线器件的区域中被选择性地去除。虽然所得到的氧化物HM 106在图2A和2B中被示出为在公共释放层104的左侧，然而实施例不限于此。所得到的氧化物HM 106在其它实施例中可以在公共释放层104的右侧或中间部分。另外，所得到的氧化物HM 106可以被形成为使得所得到的氧化物HM 106保持公共释放层104的多个非连续的区域被暴露。被氧化物HM 106覆盖的公共释放层104的一个或多个部分在本文中称为NFET区域，而通过所得到的氧化物HM 106保持暴露的公共释放层104的一个或多个部分在本文中称为PFET区域。
如图3A和3B中的结构300的侧视图和俯视图中所示，在结构200的暴露的公共释放层104(即在未被氧化物HM 106覆盖的区域)之上生长PFET堆叠110。在本实施例中，PFET堆叠110包括通过公共释放层116分离的两个SiGe层112和114，公共释放层116包含与公共释放层104相同的材料。应当注意，虽然图3A示出包括两个SiGe层的多堆叠，然而多堆叠在其它实施例中可以包括通过公共释放层分离的三层或更多层SiGe。
在下面的步骤中，如图4A和4B中的结构400的侧视图和俯视图中所示，从NFET区域去除氧化物HM 106并且在PFET区域之上形成氧化物层136。然后在NFET区域中的公共释放层104的暴露部分之上生长NFET堆叠120。在本实施例中，NFET堆叠包括通过公共释放层126分离的两个Si层122和124，公共释放层126包含与公共释放层104和116相同的材料。应当注意，虽然图4A示出包括两个Si层的多堆叠，然而在其它实施例中可以使用具有通过公共释放层分离的三层或多层Si的多堆叠。
重要的是，应当注意，虽然方法到现在为止描述形成PFET堆叠之后形成NFET堆叠，然而实施例不限于此。在其它实施例中，NFET堆叠可以先于PFET堆叠形成。另外，可以形成多个PFET和/或NFET堆叠，而非单个PFET堆叠和单个NFET堆叠。另外，PFET和NFET堆叠不仅仅限于分别由SiGe和Si来形成。相反，可以使用各种其它材料，包括但不限于铟、镓、砷、其它III-V周期材料以及II-IV族材料。
图5A和图5B分别示出在从PFET区域去除氧化物层136并且使用包括例如氮化物的硬掩模140图案化鳍160-1、160-2、162-1和162-2之后结构500的沿着截面AA截取的截面图以及俯视图。在蚀刻之后，NFET区域中的所得到的鳍结构160-1和160-2均包括通过公共释放层126分离的Si层122和124。类似地，PFET区域中的所得到的鳍结构162-1和162-2均包括通过公共释放层116分离的SiGe层112和114。氮化物HM 140留在鳍结构160-1、160-2、162-1和162-2中的每个鳍结构的顶部。虽然图5A中示出为形成两个NFET鳍160-1和160-2以及两个PFET鳍162-1和162-2，然而实施例不仅仅限于具有两个NFET鳍和两个PFET鳍的多堆叠结构。在其它实施例中，可以形成多于或少于两个NFET和两个PFET鳍。
接着，图6A和6B分别示出结构600的沿着截面AA截取的截面图以及俯视图。如所示，去除公共释放层104、116和126，保留悬置在鳍162-1中的PFET纳米线112-1和114-1、悬置在鳍162-2中的PFET纳米线112-2和114-2、悬置在鳍160-1中的NFET纳米线122-1和124-1以及悬置在鳍160-2中的NFET纳米线122-2和124-2。悬置部的典型长度L可以为大致250nm，但是可以取决于特定器件的需要而更长或者更短。公共释放层104、116和126的去除可以使用对于Si/SiGe具有选择性的湿法蚀刻来执行，例如使用等量的盐酸、醋酸和过氧化氢的复合物(HCL:CH3COOH:H2O2(1:1:1))。然而，实施例不仅仅限于这一具体湿法蚀刻的使用。相反，可以使用各种其它类型的蚀刻和工艺来去除公共释放层104、116和126。
如图6B所示，在鳍160-1、160-2、162-1和162-2的端部沉积锚定层170以保持悬置的纳米线就位。也就是，当经由湿法蚀刻去除公共释放层104、116和126时，NFET纳米线122-1、124-1、122-2和124-2以及PFET纳米线112-1、114-1、112-2和114-2从其相应中部而非从其相应端部被释放，NFET纳米线122-1、124-1、122-2和124-2以及PFET纳米线112-1、114-1、112-2和114-2经由锚定层170被锚定。锚定层170可以是绝缘体，诸如氧化物或氮化物，其被沉积、图案化和蚀刻以使得其仅在锚定位置保留。也可以使用其它锚定材料，只要其不干扰器件。为了说明的清楚，图6A的截面图中未示出锚定层170以示出通过公共释放层104、116和126的去除而留下的空间。
随后，如图7A和图7B(其分别示出结构700的沿着截面AA截取的截面图以及俯视图)中所描绘的，通过现有技术中已知的任何技术图案化锚定层170。在图7B的俯视图中，锚定层170用粗体虚线轮廓示出以表示它们实际上从图7B的俯视图不可见，但是为了说明的清楚而示出。氮化物HM 140保持在每个鳍160-1、160-2、162-1和162-2的顶部，并且沉积氧化物172以在通过公共释放层104、116和126的去除保持空白的NFET纳米线122-1、124-1、122-2和124-2与PFET纳米线112-1、114-1、112-2和114-2之间的空间中形成隔离。另外，使用各项异性蚀刻使氧化物172在鳍160-1、160-2、162-1和162-2的基部处凹陷到衬底102中。
图8A至图8C分别示出结构800的沿着截面AA截取的截面图、俯视图以及沿着截面CC截取的截面图。在本步骤，去除氮化物HM 140并且在鳍结构160-1、160-2、162-1和162-2的部分之上沉积虚设栅极177。虚设栅极177可以包括薄的氧化物(未示出)、Si层171以及氧化物或氮化物硬掩模176。也可以使用其它材料。可以将虚设栅极177沉积为毯式层，并且然后使用现有技术中已知的光刻和蚀刻工艺对其图案化。作为示例，图8B示出沉积在NFET区域160-1和160-2中的两个纳米线的部分之上以及沉积在PFET区域162-1和162-2中的两个纳米线之上的五行虚设栅极177(硬掩模176在图8B的俯视图中示出)。虚设栅极177被示出为覆盖纳米线的部分。在图8C中，鳍160-2中的纳米线122-2和124-2的堆叠层通过所示的NFET区域中的氧化物172被隔离。锚定层170被示出为在端部，从而锚定纳米线122-2和124-2。类似地，鳍160-1、162-1和162-2中的纳米线的堆叠层通过氧化物层172被隔离并且通过锚定层170被锚定。
图9示出结构900，其为在虚设栅极177的两侧的薄的间隔物178的形成之后沿着截面CC截取的图8C中的结构800的截面图。薄的间隔物178的厚度可以在1nm到20nm的范围内，但是可以是任何其它合适的厚度。薄的间隔物178通过沉积薄的绝缘体层(诸如氧化物或氮化物)并且然后从水平表面各向异性地蚀刻来形成。过蚀刻可以从鳍侧壁去除间隔物。薄的间隔物也可以形成在用于鳍160-1、162-1和162-2的虚设栅极的侧面。
图10示出结构1000，其为在选择性地去除纳米线122-2与纳米线124-2之间的氧化物172并且去除纳米线122-2与Si衬底102之间的氧化物172之后与图9中的结构900相同的截面图。也就是，去除未被虚设栅极177保护的区域中的氧化物172，留下如图10所示的间隙173。可以使用各向异性氧化物蚀刻工艺选择性地去除氧化物172。类似地，选择性地去除在纳米线122-1与纳米线124-1之间以及在纳米线122-1与Si衬底之间的用于FIN 160-1的氧化物172以及在纳米线112与114之间以及在纳米线112与Si衬底之间的用于鳍162-1和162-2的氧化物172。
图11示出结构1100，其为在薄的间隔物179的形成之后与图10中的结构1000相同的截面图。沉积可以与薄的间隔物178具有相同材料的薄的间隔物179以填充通过氧化物蚀刻留下的间隙173，如图11所示。
图12A至图12C分别示出结构1200的沿着截面AA截取的截面图、俯视图以及沿着截面CC截取的截面图，其图示形成源极/漏极区域180-1和180-2的纳米线的掺杂。使用例如外延或等离子体掺杂来掺杂纳米线的部分，以便形成源极/漏极区域180-1和180-2。使用n型掺杂用于鳍160-1和160-2中的NFET器件，使用p型掺杂用于鳍162-1和162-2中的PFET器件。如图12B所示，区域188和186为源极/漏极生长，其如图12C所示将未被虚设栅极177覆盖的纳米线扩散或变换成源极/漏极区域180-1和1802。如图12C所示，使用掩盖沟道区域182的虚设栅极177掺杂纳米线的源极/漏极区域180-1和180-2。
图13A至图13C分别示出结构1300的沿着截面AA截取的截面图、俯视图以及沿着截面CC截取的截面图。如所示，形成多堆叠纳米线器件的过程中的下一步骤包括在虚设栅极177之间的空间之上以及在源极/漏极区域180-2上方形成绝缘体184。绝缘体184可以是例如氧化物。对结构1300的顶表面进行平坦化。在平坦化之后，去除虚设栅极177，但是薄的间隔物178保留。为了说明的清楚，图13A的视图中未示出绝缘体184和薄的间隔物178。
图14A至图14C分别示出结构1400的沿着截面AA截取的截面图、俯视图以及沿着截面CC截取的截面图。在虚设栅极177的去除之后，去除纳米线122-2和124-2之间的剩余氧化物172，从而留下空间175。可以使用湿法蚀刻工艺来去除留在沟道区域中的纳米线122-2和124-2之间的氧化物172。虽然没有明确示出，但是也去除留在鳍160-1的纳米线122-1和124-1之间的氧化物172以及留在鳍162-1和162-2的纳米线112和114之间的氧化物172。为了说明的清楚，在图14A的视图中再次未示出绝缘体184和薄的间隔物178。
图15A至15C分别示出结构1500的沿着截面AA截取的截面图、俯视图以及沿着截面CC截取的截面图。通过氧化物172的去除而留下的图14C所示的空间175被图15A至图15C所示的栅极190取代。栅极190可以是例如高k栅极材料(诸如氧化铪(HfO2)、氧化锆(ZrO2)或氧化镧(La2O3))、功函数金属(诸如氮化钛(TiN)或氮化钽(TaN))、和/或栅极金属(诸如钨或铝)。栅极190填充围绕纳米线的空间，从而完全包围沟道区域中的纳米线112-1、112-2、114-1、114-2、122-1、122-2、124-1和124-2，如图15A所示。然后向栅极190上沉积栅极帽192。栅极帽192可以包括电介质，诸如例如氮化硅和氧化硅。最后，使用现有技术中已知的工艺形成到栅极/源极/漏极的触点(未示出)。
图16示出根据本发明的实施例的集成电路1600，其包括一个或多个多堆叠纳米线器件201-1到201-n，其中n为整数。
以上描述的各种结构可以被实现在集成电路中。所得到的集成电路芯片可以由制造商用未加工的晶片的形式(也就是作为具有多个未封装芯片的单个晶片)，作为裸片，或者用封装形式来分布。在用封装形式来分布的情况下，芯片安装在单个芯片封装件(诸如塑料载体，其具有固定到母板或其它更高层载体的引线)中或者安装在多芯片封装件(诸如具有表面互连或掩埋互连中的一者或二者的陶瓷载体)中。在任何情况下，然后将芯片与其它芯片、分立电路元件和/或其它信号处理器件集成作为(a)中间产品(诸如母板)的部分，或者作为(b)最终产品的部分。最终产品可以是包括集成电路芯片(从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品)的任何产品。
应当认识到并且应当理解，以上描述的本发明的示例性实施例可以用大量不同方式来实施。给定本文中所提供的本发明的教示，相关领域的普通技术人员能够想到本发明的其它实施方式。虽然本文中参考附图描述本发明的说明性实施例，然而应当理解，本发明不限于这些明确的实施例，本领域技术人员可以在不偏离本发明的范围或精神的情况下做出各种其它变化和修改。

Claims (19)

1.一种方法，包括：
在衬底上形成公共释放层，所述公共释放层包含公共释放材料；
在所述公共释放层的第一部分上形成第一材料的第一多层堆叠，所述第一多层堆叠包括至少两个层，通过包含所述公共释放材料的至少一个层分离；
在所述公共释放层的第二部分上形成第二材料的第二多层堆叠，所述第二多层堆叠包括至少两个层，通过包含所述公共释放材料的至少一个层分离，其中所述第一材料不同于所述第二材料；
将所述第一多层堆叠和所述第二多层堆叠中的每个多层堆叠图案化成一个或多个鳍；以及
通过使用公共蚀刻工艺去除所述公共释放材料来从所述一个或多个鳍形成两个或更多个多堆叠纳米线。
2.根据权利要求1所述的方法，其中所述第一多层堆叠包括：
包含第一材料的第一层；
形成在所述第一层之上的第二层，所述第二层包含所述公共释放材料；以及
形成在所述第二层之上的第三层，所述第三层包含所述第一材料；以及
其中所述第二多层堆叠包括：
包含第二材料的第四层；
形成在所述第四层之上的第五层，所述第四层包含所述公共释放材料；以及
形成在所述第五层之上的第六层，所述第六层包含所述第二材料。
3.根据权利要求2所述的方法，其中所述公共释放材料为磷化镓，所述第一材料为硅锗，并且所述第二材料为硅。
4.根据权利要求1所述的方法，其中形成所述第一多层堆叠包括：
在所述公共释放层的所述第二部分上沉积氧化物层；以及
在所述公共释放层的所述第一部分上形成所述第一多堆叠层。
5.根据权利要求4所述的方法，其中形成所述第二多层堆叠包括：
去除沉积在所述公共释放层的所述第二部分上的所述氧化物层；
在所述第一多层堆叠上沉积另一氧化物层；以及
在所述公共释放层的所述第二部分上形成所述第二多层堆叠。
6.根据权利要求1所述的方法，其中图案化所述第一多层堆叠和所述第二多层堆叠中的每个多层堆叠包括使用形成在所述第一多层堆叠和所述第二多层堆叠的部分之上的硬掩模。
7.根据权利要求6所述的方法，还包括：
在所述一个或多个鳍中的每个鳍的端部处沉积锚定层；以及
去除在所述衬底上、在所述第一多层堆叠中以及在所述第二多层堆叠中的所述公共释放材料。
8.根据权利要求7所述的方法，还包括在通过所述公共释放材料的去除而形成的一个或多个空间中沉积氧化物。
9.根据权利要求8所述的方法，还包括：
去除形成在所述第一多层堆叠和所述第二多层堆叠的部分之上的所述硬掩模；以及
在所述两个或更多个多堆叠纳米线的部分上形成多个虚设栅极。
10.根据权利要求9所述的方法，还包括在所述多个虚设栅极中的每个虚设栅极的侧面上形成薄的间隔物。
11.根据权利要求10所述的方法，还包括：
选择性地去除所述氧化物的在所述两个或更多个多堆叠纳米线之间的未被所述多个虚设栅极覆盖的区域中以及在所述两个或更多个多堆叠纳米线与所述衬底之间的未被所述多个虚设栅极覆盖的区域中的第一部分；以及
沉积薄的间隔物以填充在通过所述氧化物的所述第一部分的去除而留下的一个或多个空间中。
12.根据权利要求11所述的方法，还包括通过掺杂所述两个或更多个多堆叠纳米线的未被所述多个虚设栅极覆盖的部分来形成源极/漏极区域。
13.根据权利要求12所述的方法，使用n型掺杂用于在从所述第一多层堆叠图案化的所述一个或多个鳍中的所述两个或更多个多堆叠纳米线的部分中形成源极/漏极区域，并且其中使用p型掺杂用于在从所述第二多层堆叠图案化的所述一个或多个鳍中的所述两个或更多个多堆叠纳米线的部分中形成源极/漏极区域。
14.根据权利要求12所述的方法，还包括：
在所述多个虚设栅极之间的空间中以及在所述源极/漏极区域上方形成绝缘体；
对所述绝缘体的顶表面进行平坦化；以及
去除所述多个虚设栅极。
15.根据权利要求14所述的方法，还包括去除所述氧化物的在所述两个或更多个多堆叠纳米线之间的未被所述绝缘体覆盖的区域中的第二部分。
16.根据权利要求15所述的方法，还包括通过沉积栅极材料以填充在围绕所述两个或更多个多堆叠纳米线的空间中来形成栅极堆叠，其中所述栅极堆叠完全被所述两个或更多个多堆叠纳米线包围。
17.根据权利要求16所述的方法，还包括向所述栅极堆叠上沉积栅极帽。
18.一种多堆叠纳米线器件，包括：
两个或更多个鳍，每个鳍包括包含两个或更多个纳米线的多层堆叠，其中所述两个或更多个纳米线的部分被掺杂以形成多个源极/漏极区域；以及
两个或更多个栅极，形成在所述多个源极/漏极区域之间的所述两个或更多个鳍的部分之上，所述栅极填充在每个所述鳍中的所述两个或更多个纳米线之间的空间中；以及
锚定层，位于所述两个或更多个纳米线的每一个的每个端部锚定所述两个或更多个纳米线，其中所述锚定层为绝缘体；
其中所述两个或更多鳍中的第一个包括第一材料的两个或更多个纳米线的多层堆叠；
其中所述两个或更多鳍中的第二个包括第二材料的两个或更多个纳米线的多层堆叠，其中所述第一材料不同于所述第二材料；
每个所述鳍中的所述两个或更多个纳米线之间的所述空间使用公共蚀刻工艺去除公共释放材料来形成。
19.一种集成电路，包括：
一个或多个多堆叠纳米线器件；其中所述一个或多个多堆叠纳米线器件中的每个多堆叠纳米线器件包括：
两个或更多个鳍，每个鳍包括包含两个或更多个纳米线的多层堆叠，其中所述两个或更多个纳米线的部分被掺杂以形成多个源极/漏极区域；以及
两个或更多个栅极，形成在所述多个源极/漏极区域之间的所述两个或更多个鳍的部分之上，所述栅极填充在每个所述鳍中的所述两个或更多个纳米线之间的空间中；以及
锚定层，位于所述两个或更多个纳米线的每一个的每个端部锚定所述两个或更多个纳米线，其中所述锚定层为绝缘体；
其中所述两个或更多鳍中的第一个包括第一材料的两个或更多个纳米线的多层堆叠；
其中所述两个或更多鳍中的第二个包括第二材料的两个或更多个纳米线的多层堆叠，其中所述第一材料不同于所述第二材料；
其中每个所述鳍中的所述两个或更多个纳米线之间的所述空间使用公共蚀刻工艺去除公共释放材料来形成。
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