CN107210225A - pFET区域中的应变释放 - Google Patents

pFET区域中的应变释放 Download PDF

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CN107210225A
CN107210225A CN201680005565.6A CN201680005565A CN107210225A CN 107210225 A CN107210225 A CN 107210225A CN 201680005565 A CN201680005565 A CN 201680005565A CN 107210225 A CN107210225 A CN 107210225A
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fin
germanium
grid structure
layer
silicon layer
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CN107210225B (zh
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B·多里斯
K·里姆
A·雷茨尼采克
D·D·鲁
A·卡基菲鲁兹
程慷果
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International Business Machines Corp
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Abstract

一种用于制造半导体器件的方法包括：提供绝缘体上应变硅(SSOI)结构，该SSOI结构包括设置在衬底(10)上的电介质层(20)、设置在电介质层(20)上的硅锗层(30)、以及直接设置在硅锗层(30)上的应变半导体材料层(40)；在SSOI结构上形成多个鳍(43、45)；在nFET区域中的至少一个鳍的部分之上形成栅极结构(50)；在pFET区域中的至少一个鳍的部分之上形成栅极结构(60)；去除pFET区域中的至少一个鳍的部分之上的栅极结构(60)；去除通过上述去除而被暴露的硅锗层(30)；以及在pFET区域中的至少一个鳍的部分之上形成新的栅极结构(90)，以使得新的栅极结构(90)在全部四侧包围该部分。

Description

pFET区域中的应变释放
技术领域
本发明一般而言涉及半导体器件，更具体地，涉及将绝缘体上应变硅(SSOI)衬底用于nFET区域而在pFET区域中应变释放。
背景技术
互补金属氧化物半导体器件(CMOS)使用被设置在硅或绝缘体上硅(SOI)衬底上的互补且对称取向的p型和n型金属氧化物半导体场效应晶体管(MOSFET)的对。用于放大或切换逻辑功能用电子信号的MOSFET具有通过沟道而连接的源极区和漏极区。源极区是多数载流子(电子或空穴)形式的电流进入沟道所经过的端子，而漏极区是多数载流子形式的电流离开沟道所经过的端子。在p型MOSFET(下文中称为“pFET”)中，多数载流子是流过沟道的空穴，而在n型MOSFET(下文中称为“nFET”)中，多数载流子是流过沟道的电子。栅极覆盖沟道并控制源极区与漏极区之间的电流的流动。沟道可以由提供一个以上表面的薄“鳍”限定，通过该表面，栅极控制电流的流动，从而使pFET和nFET为“finFET”器件。一般而言，鳍的长度比宽度大几个数量级。
在pFET和nFET的制造中所使用的衬底可以包括绝缘体上应变硅(SSOI)衬底。这样的衬底通常具有数千兆帕斯卡(GPa)的内在拉伸应力，这通常提高了电子迁移率，从而提高器件性能。即使在与典型的平面MOSFET相比沟道的长度和宽度较短的短沟道finFET器件中，这些衬底中的应变也可以在不导致静电特性劣化的情况下提高器件性能。
然而，当SSOI衬底中的整体内在应力超过预定的最大值(例如，大于约1GPa)时，pFET finFET器件的性能可能损失8至15％。这是由SSOI衬底中的拉伸应力的存在导致的空穴迁移率降低的结果。因此，希望释放pFET器件的沟道中的拉伸应力，并且使其性能提高/恢复到SOI衬底水平。如果这一点可以实现，则可以在不使互补pFET器件劣化的情况下制造出具有更高性能的nFET器件。
发明内容
本发明的优选实施例涉及一种用于制造半导体器件的方法，包括：提供绝缘体上应变硅(SSOI)结构，其中所述SSOI结构至少包括衬底、设置在所述衬底上的电介质层、设置在所述电介质层上的硅锗层、以及直接设置在所述硅锗层上的应变半导体材料层。所述方法进一步包括通过将所述应变半导体材料层和所述硅锗层向下蚀刻到所述电介质层而在所述SSOI结构上形成多个鳍，其中所述多个鳍中的至少一个鳍位于所述SSOI结构的nFET区域中，并且所述多个鳍中的至少一个鳍位于所述SSOI结构的pFET区域中。所述方法进一步包括在所述多个鳍中的位于所述nFET区域中的所述至少一个鳍的第一部分之上形成第一栅极结构。所述方法进一步包括在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的第二部分之上形成第二栅极结构，以使得所述第二栅极结构在三侧包围所述第二部分。所述方法进一步包括去除所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的所述第二部分之上的所述第二栅极结构。所述方法进一步包括去除通过去除所述第二部分之上的所述第二栅极结构而被暴露的所述硅锗层。所述方法进一步包括在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的所述第二部分之上形成第三栅极结构，以使得所述第三栅极结构在全部四侧包围所述第二部分。
本发明的另一优选实施例涉及一种具有绝缘体上应变硅(SSOI)结构的半导体器件，其中所述SSOI结构至少包括衬底、设置在所述衬底上的电介质层、设置在所述电介质层上的硅锗层、以及直接设置在所述硅锗层上的应变半导体材料层。所述半导体器件进一步包括在所述应变半导体材料层和所述硅锗层中向下形成的在所述SSOI结构上的多个鳍，其中所述多个鳍中的至少一个鳍位于所述SSOI结构的nFET区域中，并且所述多个鳍中的至少一个鳍位于所述SSOI结构的pFET区域中。所述半导体器件进一步包括在所述多个鳍中的位于所述nFET区域中的所述至少一个鳍的第一部分之上的第一栅极结构，其中所述第一栅极结构在三侧包围所述第一部分，并且其中所述硅锗层被设置在所述第一部分的底面与所述电介质层之间。所述半导体器件进一步包括在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的第二部分之上的第二栅极结构，其中所述第二栅极结构在全部四侧包围所述第二部分。
附图说明
将结合附图最好地理解以下详细的描述，该描述通过举例的方式被给出且并非旨在将本公开仅限于此，其中：
图1示出根据本发明的一个实施例的绝缘体上应变硅(SSOI)结构的横截面图；
图2A示出通过与已从图1所示的绝缘体上应变硅(SSOI)结构制造出的栅极结构垂直的鳍(沿沟道方向)之间的区域(与鳍平行)的nFET器件和pFET器件的横截面图；
图2B示出通过图2A所示的剖面线2B-2B截取的横截面图，该横截面图通过栅极结构、垂直于鳍地示出了pFET器件；
图3A示出在已去除pFET器件的栅极结构之后的、通过与nFET器件的栅极结构垂直的鳍(沿沟道方向)之间的区域(与鳍平行)的nFET器件和pFET器件的横截面图；
图3B示出通过图3A所示的剖面线3B-3B截取的横截面图，该横截面图通过由去除栅极结构而形成的栅极沟槽、垂直于鳍地示出了pFET器件；
图4A示出在已去除通过去除pFET器件的栅极结构而被暴露的硅锗层的部分之后的、通过与nFET器件的栅极结构垂直的鳍(沿沟道方向)之间的区域(与鳍平行)的nFET器件和pFET器件的横截面图；
图4B示出通过图4A所示的剖面线4B-4B截取的横截面图，该横截面图通过在已去除经去除栅极结构而被暴露的硅锗层的部分之后的栅极沟槽、垂直于鳍地示出了pFET器件；
图5A示出在pFET器件中形成新的栅极结构之后的、通过与nFET器件的栅极结构垂直的鳍(沿沟道方向)之间的区域(与鳍平行)的图4A的nFET器件和pFET器件的横截面图；以及
图5B示出通过图5A所示的剖面线5B-5B截取的横截面图，该横截面图通过在形成新的栅极结构之后的栅极沟槽、垂直于鳍地示出了pFET器件。
具体实施方式
本文中公开了所要求保护的结构和方法的详细的实施例；然而，将理解的是，所公开的实施例仅仅是可以通过各种形式体现的所要求保护的结构和方法的示例。此外，结合各种实施例给出的每个实例旨在是示例性的，而非限制性的。另外，附图不一定是按比例绘制的，一些特征可能被放大以示出特定组件的细节。因此，此处公开的具体的结构和功能细节不应当被解释为限制性的，而仅仅是用于教导本领域的技术人员以各种方式采用本公开的方法和结构的代表性基础。
说明书中提到的“一个实施例”、“实施例”、“示例性实施例”等是指所描述的实施例可以包括特定的特征、结构或特性，但不是每一个实施例都必须包括所述特定的特征、结构或特性。此外，这样的措词未必指同一个实施例。此外，当结合某实施例描述特定的特征、结构或特性时，认为结合其他实施例实现这样的特征、结构或特性在本领域技术人员的知识范围内，而不管是否进行了明确说明。
为了下文的描述，术语“上”、“下”、“右”、“左”、“竖直”、“水平”、“顶部”、“底部”及其派生词应当涉及如附图中所取向的所公开的本发明。术语“覆于……之上”、“伏于……之下”、“在……顶上”、“在……顶部”、“位于……上”、“位于……顶部”表示诸如第一结构的第一要素位于诸如第二结构的第二要素之上，其中诸如界面结构的中间要素可以存在于第一要素与第二要素之间。术语“直接接触”表示诸如第一结构的第一要素和诸如第二结构的第二要素连接，在这两个要素的界面处没有任何中间的导电、绝缘或半导体层。
本文中描述的电路可以是集成电路芯片设计的一部分。该芯片设计可以以图形计算机编程语言生成，并存储在计算机存储介质(例如磁盘、磁带、实体硬盘驱动器、或例如存储访问网络中的虚拟硬盘驱动器)中。若设计者不制造芯片或用于制造芯片的光刻掩模，设计者可以直接或间接地将所产生的设计通过物理装置(例如，通过提供存储该设计的存储介质的副本)、或以电子方式(例如，通过网络)传送至该实体。然后将所存储的设计转换成用于光刻掩模制造的适当格式(例如，GDSII)，光刻掩模典型地包括所关注的要在晶片上形成的芯片设计的多个副本。光刻掩模被用于界定待蚀刻或待处理的晶片(和/或其上的层)的区域。
本文中描述的方法可以被用于制造集成电路芯片。所得到的集成电路芯片可以以原始晶片的形式(即，作为具有多个未封装的芯片的单个晶片)、作为裸管芯或者以封装的形式由制造商分配。在后一情况下，芯片安装在单个芯片封装体(例如塑料载体，具有固定到主板或其它更高级的载体上的引线)中或者安装在多芯片封装体(例如具有表面互连和掩埋互连中的一者或两者的陶瓷载体)中。在任一情况下，然后将芯片与其它芯片、分立电路元件和/或其他信号处理器件集成，作为(a)诸如主板的中间产品或(b)最终产品的一部分。所述最终产品可以是包括集成电路芯片的任何产品，范围从玩具和其它低端应用到具有显示器、键盘或其它输入装置以及中央处理器的高级计算机产品。
本发明的某些实施例认识到为了提高FinFET性能，需要应变沟道材料。使用SSOI衬底作为起始晶片将产生应变鳍。拉伸应变鳍(SSOI)对于nFET器件是有益的，但对于pFET器件不是有益的。因此，需要释放pFET鳍中的拉伸应变。
本发明的实施例一般而言提供一种在具有用于nFET器件的拉伸应变鳍和用于pFET器件的弛豫鳍的绝缘体上应变硅(SSOI)衬底上的FinFET器件的结构以及形成方法。该结构可以通过在pFET区域中的鳍下方选择性地蚀刻牺牲SiGe层而形成。
现在将参考附图详细地描述本发明。
图1示出根据本发明的一个实施例的绝缘体上应变硅(SSOI)结构的横截面图。在一个实施例中，对于包括被构建在SSOI前体上的finFET结构的实施例，SSOI结构包括衬底10、电介质层20、硅锗层30和应变半导体材料层40。在另一实施例中，衬底10、电介质层20和硅锗层30可以由绝缘体上热混合硅锗(TMSGOI)衬底或绝缘体上应变硅锗(SSGOI)衬底替代。
衬底10由任何常规的半导体衬底材料构成。常规的半导体衬底材料包括但不限于硅(Si)、锗(Ge)、硅锗(SiGe)、碳化硅、III-V族化合物半导体、II-VI族化合物半导体、以及它们的组合和多层。
电介质层20覆于衬底10之上。电介质层20可以包括掩埋氧化物(BOX)或其它电介质材料。BOX材料可以包括任何常规的氧化物材料，例如，二氧化硅(SiO2)。电介质层20具有约10nm至约500nm的典型厚度。电介质层20可以通过热氧化衬底10的暴露表面而形成，或者可以使用例如化学气相沉积(CVD)或原子层沉积(ALD)而被沉积在衬底10上。如在本文中所用的，并且除非另有说明，否则术语“沉积”可以包括适用于要被沉积的材料的任何现在已知的或以后开发的技术，所述技术包括但不限于，例如：化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)、半大气压CVD(SACVD)和高密度等离子体CVD(HDPCVD)、快速热CVD(RTCVD)、超高真空CVD(UHVCVD)、限制反应处理CVD(LRPCVD)、金属有机CVD(MOCVD)、溅射沉积、离子束沉积、电子束沉积、激光辅助沉积、热氧化、热氮化、旋涂法、物理气相沉积(PVD)、原子层沉积(ALD)、化学氧化、分子束外延(MBE)、镀敷、蒸发。
硅锗层30覆于电介质层20之上。硅锗层30在电介质层20之上形成。硅锗层30形成在电介质层20的顶上。硅锗层30或者通过晶片接合以及之后的已知的smart 工艺而形成，或者通过在SOI晶片上沉积硅锗以及之后的热混合和冷凝处理而形成。硅锗层30的Ge含量的按原子重量％的典型范围为5％至60％，优选地25％至50％。典型地，所形成的硅锗层30的厚度范围为约6nm至约10nm，优选地为10nm至20nm。
应变半导体材料层40覆于硅锗层30之上。应变半导体材料层40可以包括硅、硅锗或任何适合的半导体材料。在一个实施例中，应变半导体材料层40包括外延生长的双轴拉伸应变含Si材料，该材料的晶格尺寸小于下伏的硅锗层30的晶格尺寸。应变半导体材料层40可以生长到小于其临界厚度的厚度。典型地，应变半导体材料层40可以生长到范围为约10nm至约100nm的厚度。
在形成图1所示的绝缘体上应变硅(SSOI)结构之后，使用常规的MOSFET处理步骤形成pFET和nFET“finFET”器件，这些处理步骤包括但不限于：常规的栅极氧化预清洁和栅极电介质形成；栅极导体形成和图案化；栅极再氧化；源漏极延伸形成；通过沉积和蚀刻的侧壁间隔物(spacer)形成；以及源漏极形成。在典型的FinFET制造流程中，首先在整个晶片上图案化鳍，并且一旦形成栅极堆叠、间隔物和抬升式源/漏极结构，便分离各个器件。如下所述，本发明的实施例修改特定的处理步骤，或者将特定的处理步骤添加到常规的MOSFET处理中。为了清楚起见，该讨论省去了某些常规的MOSFET处理步骤。
图2A示出根据本发明的一个实施例，通过与已从图1所示的绝缘体上应变硅(SSOI)结构制造出的栅极结构50和栅极结构60垂直的鳍(沿沟道方向)之间的区域(与鳍43和45平行)的nFET器件和pFET器件的横截面图。
通过使用光刻并且将应变半导体材料层40和硅锗层30向下蚀刻到电介质层20而在应变半导体材料层40中形成鳍43和45。鳍43位于nFET区域中，鳍45位于pFET区域中。一旦形成，一示例性鳍的厚度为约4nm至约20nm，优选地为6-10nm，并且一示例性鳍的高度为约20nm至约100nm，优选地为30-70。鳍的长度可以处于从约100nm至数微米的范围内。然而，栅极间距可以为40nm至500nm。应变半导体材料层40和硅锗层30可以使用干式蚀刻技术(例如，诸如反应离子蚀刻(RIE)等的等离子体干式蚀刻或使用例如含氟气体的非等离子体蚀刻技术)而被蚀刻。
nFET区域和pFET区域中的栅极区域由分别横断鳍43和45堆叠的一个或多个层界定。在形成栅极结构50和60时，栅极电介质材料和栅极导体被沉积在鳍43和45之间以及鳍43和45之上，然后使用光刻和蚀刻步骤对栅极电介质材料和栅极导体图案化以界定分别横断鳍43和45延伸的栅极叠层(构成栅极结构50和栅极结构60的层)。在一个实施例中，栅极结构50和60可以至少包括栅极电介质材料和栅极导体。栅极电介质材料可以包括例如二氧化硅、氧氮化硅、高k电介质等等。栅极导体可以包括多晶硅、金属或者这两者的组合等等。pFET和nFET器件可以根据需要而接收相同或不同的栅极叠层以设定阈值电压(鳍43位于nFET区域中，鳍45位于pFET区域中)。
间隔物70在栅极结构50和栅极结构60的相反两侧形成。间隔物70通过在栅极结构50和栅极结构60的侧壁上沉积并图案化绝缘体材料而形成。绝缘体材料可以是任何电介质材料，该电介质材料包括但不限于SiN、Si3N4、SiO2、硅碳氮化物等等。
在栅极结构50和60以及间隔物70形成之后，通过诸如CVD的任何适当的工艺，在nFET器件和pFET器件之上(例如，在栅极结构50和60之上，在间隔物70之上，在鳍43和45之上，在电介质层20的任何暴露部分之上)形成层间电介质(ILD)层80。ILD层80包括电介质材料。电介质材料可以包括氧化硅、氮化硅、氧氮化硅、旋涂玻璃(SOG)、氟化石英玻璃(FSG)、掺碳氧化硅(例如，SiCON)、干凝胶、气凝胶、非晶氟化碳、聚对二甲苯、BCB(二苯并环丁烯)、Flare、SiLK(Dow Chemical，Midland，Mich.)、聚酰亚胺、无孔材料、多孔材料和/或它们的组合。在某些实施例中，ILD层80可以包括高密度等离子体(HDP)电介质材料(例如，HDP氧化物)和/或高纵横比工艺(HARP)电介质材料(例如，HARP氧化物)。ILD层80包括任何适当的厚度。优选地，ILD层80包括大约的厚度。将理解，ILD层80可以包括一种或多种电介质材料和/或一个或多个电介质层。
接下来，ILD层80通过化学机械抛光(CMP)工艺而被平面化，直到至少栅极结构60的顶部被暴露。在一个实施例中，ILD层80的顶面与栅极结构50和60的顶面以及间隔物70的顶面共面，如图2A所示例。
图2B示出根据本发明的一个实施例，通过图2A所示的剖面线2B-2B截取的横截面图，该横截面图通过栅极结构60、垂直于鳍45(例如，硅锗层30和应变半导体材料层40)地示出了pFET器件。图2B示出在三侧包围鳍45(例如，硅锗层30和应变半导体材料层40)的栅极结构60。鳍45当前被示出为由硅锗层30和应变半导体材料层40构成。
图3A示出在已去除栅极结构60之后，通过与栅极结构50垂直的鳍(沿沟道方向)之间的区域(与鳍43和45平行)的图2A的nFET器件和pFET器件的横截面图。
在一个实施例中，使用替代金属栅极工艺去除栅极结构60。进行该去除工艺以蚀刻栅极结构60并将其完全去除。如图3A所示，栅极结构60的去除在侧壁间隔物70之间形成栅极沟槽，该沟槽暴露被栅极结构60覆盖的鳍45的一部分(例如，应变半导体材料层40和硅锗层30的一部分)。电介质层20充当蚀刻停止层。
可以采用常规的技术来去除栅极结构60。在一个实施例中，将掩膜(未示出)沉积在nFET区域之上(例如，沉积在之上以保护栅极结构50，同时使栅极结构60的顶面暴露)。在一个实施例中，掩膜是氮化物硬掩膜。在各种实施例中，掩膜可以是例如使用低压化学气相沉积(LPCVD)而被沉积的具有约10nm的典型厚度的氮化硅(SiN)。在其它实施例中，掩膜可以是能够在栅极结构60的去除期间充当蚀刻掩膜的任何掩膜材料(例如，氮化物、氧化物/氮化物叠层、氮化钛、氮化硅、二氧化硅、碳化硅、硅碳氮化物等)。
在一个实施例中，在保护栅极结构50之后，使用诸如TMAH的湿式化学蚀刻或诸如RIE的干式蚀刻去除被暴露的栅极结构60，从而暴露电介质层20、间隔物70的侧壁、以及应变半导体材料层40的一部分和硅锗层30的一部分。本领域的普通技术人员将认识到，所使用的蚀刻类型取决于构成栅极结构60的材料，可以使用其它蚀刻工艺，例如湿式化学蚀刻、激光烧蚀等等。
图3B示出根据本发明的一个实施例，通过图3A所示的剖面线3B-3B截取的横截面图，该横截面图通过经去除栅极结构60而形成的栅极沟槽、垂直于鳍45(例如，硅锗层30和应变半导体材料层40)地示出了pFET器件。图3B示出通过去除栅极结构60而形成的栅极沟槽。鳍45(例如，硅锗层30和应变半导体材料层40)现在在三侧被暴露。鳍45当前被示出为由硅锗层30和应变半导体材料层40构成。
图4A示出根据本发明的一个实施例，在已去除通过去除栅极结构60而被暴露的硅锗层30的部分之后，通过与栅极结构50垂直的鳍(沿沟道方向)之间的区域(与鳍43和45平行)的图3A的nFET器件和pFET器件的横截面图。
在一个实施例中，去除通过去除栅极结构60而被暴露的硅锗层30的部分。通过去除栅极结构60而被暴露的硅锗层30的部分例如可以使用HCl气体蚀刻工艺而从应变半导体材料层40下方被去除。硅锗层30的该部分的去除暴露了通过移除栅极结构60而被暴露的应变半导体材料层40的部分的底面。
图4B示出根据本发明的一个实施例，通过图4A所示的剖面线4B-4B截取的横截面图，该横截面图通过已去除经去除栅极结构60而被暴露的硅锗层30的部分之后的栅极沟槽、垂直于鳍45(例如，应变半导体材料层40)地示出了pFET器件。图4B示出已去除经去除栅极结构60而被暴露的硅锗层32的部分之后的栅极沟槽。鳍45(例如，应变半导体材料层40)现在在全部四侧被暴露。鳍45现在被示出为由应变半导体材料层40构成。此外，鳍45的四侧通过去除经去除栅极结构60而被暴露的硅锗层30的部分而被暴露，从而形成延伸穿过栅极沟槽的鳍。
图5A示出根据本发明的一个实施例，在形成栅极结构90之后，通过与栅极结构50垂直的鳍(沿沟道方向)之间的区域(与鳍43和45平行)的图4A的nFET器件和pFET器件的横截面图。
在一个实施例中，栅极结构90包括本领域的技术人员已知的例如使用CVD或ALD而沉积的材料的叠层，并且可以包括高k电介质材料。在各种实施例中，栅极结构90的形成包括栅极电介质材料的沉积。在一个实施例中，栅极电介质材料由高k电介质材料构成，高k电介质材料包括但不限于二氧化铪(HfO2)、硅酸铪(HfSiOx)、氧化铝(Al2O3)、氧化锆(ZrO3)或氧化镧(La2O3)。栅极电介质材料被沉积在ILD层80的表面、间隔物70的被暴露的顶部和侧壁表面、电介质层20的被暴露部分、以及鳍45(例如，应变半导体材料层40)的被暴露部分的四侧。
在一个实施例中，栅极结构90包括功函数设定金属和栅极导体材料。功函数设定金属可以是沉积在栅极电介质材料之上的诸如氮化钛(TiN)或氮化钽(TaN)的材料。本领域的技术人员将理解，功函数设定金属的选择和使用是基于finFET器件的所希望的电特性的。栅极导体材料被沉积在功函数设定金属之上，从而使用例如钨(W)或铝(Al)填充栅极沟槽。栅极结构90的各种层和材料作为例子而被给出，并非意味着限制。用于形成栅极结构90的多余材料可以从ILD层80的表面去除。例如，可以使用CMP去除包括栅极电介质材料、功函数设定金属和栅极导体材料的用于形成栅极结构90的多余材料。结果是，栅极结构90被掩埋在鳍45(例如，应变半导体材料层40)的一部分的下方，并且在四侧包围鳍45的一部分。
在另一实施例中，栅极结构90包括可流动的氧化物部分。可流动的氧化物部分被设置在鳍45(例如，应变半导体材料层40)的被暴露的部分的底面与电介质层20之间。在一个实施例中，可流动的氧化物可以是能够从栅极沟槽的底部向上填充到鳍45(例如，应变半导体材料层40)的被暴露的部分的底面高度的任何类型的可流动的氧化物。结果是，栅极结构90的一部分(可流动的氧化物)被掩埋在鳍45(例如，应变半导体材料层40)的一部分的下方，栅极结构90的另一部分在三侧包围鳍45的部分。
图5B示出根据本发明的一个实施例，通过图5A所示的剖面线5B-5B截取的横截面图，该横截面图通过形成栅极结构90之后的栅极沟槽、垂直于鳍45(例如，应变半导体材料层40)地示出了pFET器件。图5B示出形成栅极结构90之后的栅极沟槽。鳍45(例如，应变半导体材料层40)现在在全部四侧被栅极结构90包围。在另一实施例中，栅极结构90具有被掩埋在鳍45(例如，应变半导体材料层40)的一部分的下方的部分(可流动的氧化物)，并且具有在三侧包围鳍45的该部分的另一部分。

Claims (20)

1.一种用于制造半导体器件的方法，包括：
提供绝缘体上应变硅(SSOI)结构，其中所述SSOI结构至少包括衬底、设置在所述衬底上的电介质层、设置在所述电介质层上的硅锗层、以及直接设置在所述硅锗层上的应变半导体材料层；
通过将所述应变半导体材料层和所述硅锗层向下蚀刻到所述电介质层而在所述SSOI结构上形成多个鳍，其中所述多个鳍中的至少一个鳍位于所述SSOI结构的nFET区域中，并且所述多个鳍中的至少一个鳍位于所述SSOI结构的pFET区域中；
在所述多个鳍中的位于所述nFET区域中的所述至少一个鳍的第一部分之上形成第一栅极结构；
在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的第二部分之上形成第二栅极结构，以使得所述第二栅极结构在三侧包围所述第二部分；
去除所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的所述第二部分之上的所述第二栅极结构；
去除通过去除所述第二部分之上的所述第二栅极结构而被暴露的所述硅锗层；以及
在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的所述第二部分之上形成第三栅极结构，以使得所述第三栅极结构在全部四侧包围所述第二部分。
2.根据权利要求1所述的方法，其中所述硅锗层的锗含量处于5％至60％的原子重量百分比范围内。
3.根据权利要求1所述的方法，其中所述硅锗层的锗含量处于25％至50％的原子重量百分比范围内。
4.根据权利要求1所述的方法，其中所述硅锗层具有从约5nm至约100nm的范围内的厚度。
5.根据权利要求1所述的方法，其中所述硅锗层具有从约10nm至20nm的范围内的厚度。
6.根据权利要求1所述的方法，其中所述硅锗层通过晶片接合工艺而被设置在所述电介质层上。
7.根据权利要求1所述的方法，其中所述衬底和所述电介质层是绝缘体上硅(SOI)衬底的组件，并且其中所述硅锗层是通过在所述SOI衬底上沉积硅锗，然后进行热混合和冷凝处理而形成的。
8.根据权利要求1所述的方法，其中所述电介质层包括掩埋氧化物(BOX)。
9.根据权利要求1所述的方法，其中所述电介质层包括二氧化硅。
10.根据权利要求1所述的方法，其中所述去除通过去除所述第二部分之上的所述第二栅极结构而被暴露的所述硅锗层包括：
使用HCl气体蚀刻来蚀刻通过去除所述第二部分之上的所述第二栅极结构而被暴露的所述硅锗层。
11.根据权利要求1所述的方法，其中所述衬底包括以下一种或多种：硅；锗；硅锗；碳化硅；III-V族化合物半导体；II-VI族化合物半导体；以及它们的组合和多层。
12.根据权利要求1所述的方法，其中所述多个鳍具有从约6nm至约10nm的范围内的厚度。
13.根据权利要求1所述的方法，其中所述多个鳍具有从30nm至70nm的范围内的高度。
14.根据权利要求1所述的方法，其中所述第三栅极结构包括可流动的氧化物部分，其中所述可流动的氧化物部分被设置在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的所述第二部分的底面与所述电介质层之间。
15.一种半导体器件，包括：
绝缘体上应变硅(SSOI)结构，其中所述SSOI结构至少包括衬底、设置在所述衬底上的电介质层、设置在所述电介质层上的硅锗层、以及直接设置在所述硅锗层上的应变半导体材料层；
在所述应变半导体材料层和所述硅锗层中向下形成的在所述SSOI结构上的多个鳍，其中所述多个鳍中的至少一个鳍位于所述SSOI结构的nFET区域中，并且所述多个鳍中的至少一个鳍位于所述SSOI结构的pFET区域中；
在所述多个鳍中的位于所述nFET区域中的所述至少一个鳍的第一部分之上的第一栅极结构，其中所述第一栅极结构在三侧包围所述第一部分，并且其中所述硅锗层被设置在所述第一部分的底面与所述电介质层之间；以及
在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的第二部分之上的第二栅极结构，其中所述第二栅极结构在全部四侧包围所述第二部分。
16.根据权利要求15所述的半导体器件，其中所述第二栅极结构包括可流动的氧化物部分，其中所述可流动的氧化物部分被设置在所述多个鳍中的位于所述pFET区域中的所述至少一个鳍的所述第二部分的底面与所述电介质层之间。
17.根据权利要求15所述的半导体器件，其中所述硅锗层的锗含量处于5％至60％的原子重量百分比范围内。
18.根据权利要求15所述的半导体器件，其中所述硅锗层的锗含量处于25％至50％的原子重量百分比范围内。
19.根据权利要求15所述的半导体器件，其中所述第一栅极结构和所述第二栅极结构分别至少包括栅极电介质材料和栅极导体。
20.根据权利要求19所述的半导体器件，
其中所述栅极电介质材料为二氧化硅、氧氮化硅或高k电介质，并且
其中所述栅极导体为多晶硅或金属。
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US9761610B2 (en) 2017-09-12
DE112016000183B4 (de) 2020-09-10
CN107210225B (zh) 2020-07-07
JP2018506174A (ja) 2018-03-01
US9543323B2 (en) 2017-01-10
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GB2550740A (en) 2017-11-29
DE112016000183T5 (de) 2017-08-24
US20170053943A1 (en) 2017-02-23
US20160204131A1 (en) 2016-07-14
US20160359003A1 (en) 2016-12-08
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US9966387B2 (en) 2018-05-08
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