JP2018506174A - 半導体デバイスを製作するための方法および半導体デバイス - Google Patents
半導体デバイスを製作するための方法および半導体デバイス Download PDFInfo
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- JP2018506174A JP2018506174A JP2017531719A JP2017531719A JP2018506174A JP 2018506174 A JP2018506174 A JP 2018506174A JP 2017531719 A JP2017531719 A JP 2017531719A JP 2017531719 A JP2017531719 A JP 2017531719A JP 2018506174 A JP2018506174 A JP 2018506174A
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Abstract
Description
Claims (20)
- 半導体デバイスを製作するための方法であって、
歪みシリコン・オン・インシュレータ(SSOI)構造を用意するステップであって、前記SSOI構造は、少なくとも基板と、前記基板上に配設される誘電体層と、前記誘電体層上に配設されるシリコン・ゲルマニウム層と、前記シリコン・ゲルマニウム層上に直接配設される歪み半導体材料層とを備える、前記用意するステップと、
前記歪み半導体材料層、および下の前記シリコン・ゲルマニウム層を前記誘電体層までエッチングすることにより、複数のフィンを前記SSOI構造上に形成するステップであって、前記複数のフィンのうちの少なくとも1つのフィンは、前記SSOI構造のnFET領域内にあり、前記複数のフィンのうちの少なくとも1つのフィンは、前記SSOI構造のpFET領域内にある、前記形成するステップと、
第1のゲート構造を、前記nFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの第1の部分の上方に形成するステップと、
第2のゲート構造が前記pFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの第2の部分を三方から包囲するように、前記第2のゲート構造を前記第2の部分の上方に形成するステップと、
前記pFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの前記第2の部分の上方の前記第2のゲート構造を除去するステップと、
前記第2の部分の上方の前記第2のゲート構造を除去することにより露出される前記シリコン・ゲルマニウム層を除去するステップと、
第3のゲート構造が、前記pFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの前記第2の部分の四方すべてを包囲するように、前記第3のゲート構造を前記第2の部分の上方に形成するステップと
を含む、方法。 - 前記シリコン・ゲルマニウム層のゲルマニウム含有量は、原子量パーセント単位で、5%から60%の範囲にある、請求項1に記載の方法。
- 前記シリコン・ゲルマニウム層のゲルマニウム含有量は、原子量パーセント単位で、25%から50%の範囲にある、請求項1に記載の方法。
- 前記シリコン・ゲルマニウム層は、約5nmから約100nmの範囲にある厚さを有する、請求項1に記載の方法。
- 前記シリコン・ゲルマニウム層は、約10nmから20nmの範囲にある厚さを有する、請求項1に記載の方法。
- 前記シリコン・ゲルマニウム層は、前記誘電体層上に、ウェハ・ボンディング・プロセスにより配設される、請求項1に記載の方法。
- 前記基板および前記誘電体層は、シリコン・オン・インシュレータ(SOI)基板の構成要素であり、前記シリコン・ゲルマニウム層は、熱混合および凝縮プロセスが後に続く、シリコン・ゲルマニウムを前記SOI基板上に堆積させることにより形成される、請求項1に記載の方法。
- 前記誘電体層は、埋め込み酸化物(BOX)を含む、請求項1に記載の方法。
- 前記誘電体層は、二酸化ケイ素を含む、請求項1に記載の方法。
- 前記第2の部分の上方の前記第2のゲート構造を除去することにより露出される前記シリコン・ゲルマニウム層を除去する前記ステップは、
前記第2の部分の上方の前記第2のゲート構造を除去することにより露出される前記シリコン・ゲルマニウム層を、HClガス・エッチを使用してエッチングするステップ
を含む、請求項1に記載の方法。 - 前記基板は、以下のもの、すなわち、シリコン、ゲルマニウム、シリコン・ゲルマニウム、炭化ケイ素、III−V型化合物半導体、II−VI型化合物半導体、ならびに、それらの組合せおよび多層のうちの1つまたは複数を含む、請求項1に記載の方法。
- 前記複数のフィンは、約6nmから約10nmの範囲にある厚さを有する、請求項1に記載の方法。
- 前記複数のフィンは、30nmから70nmの範囲にある高さを有する、請求項1に記載の方法。
- 前記第3のゲート構造は、流動性酸化物部分を含み、前記流動性酸化物部分は、前記誘電体層と、前記pFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの前記第2の部分の下部表面との間に配設される、請求項1に記載の方法。
- 半導体デバイスであって、
歪みシリコン・オン・インシュレータ(SSOI)構造であって、少なくとも基板と、前記基板上に配設される誘電体層と、前記誘電体層上に配設されるシリコン・ゲルマニウム層と、前記シリコン・ゲルマニウム層上に直接配設される歪み半導体材料層とを備える、前記SSOI構造と、
前記歪み半導体材料層、および下の前記シリコン・ゲルマニウム層に形成される、前記SSOI構造上の複数のフィンであって、前記複数のフィンのうちの少なくとも1つのフィンは、前記SSOI構造のnFET領域内にあり、前記複数のフィンのうちの少なくとも1つのフィンは、前記SSOI構造のpFET領域内にある、前記複数のフィンと、
前記nFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの第1の部分の上方の第1のゲート構造であって、前記第1の部分を三方から包囲し、前記シリコン・ゲルマニウム層が、前記誘電体層と、前記第1の部分の下部表面との間に配設される、前記第1のゲート構造と、
前記pFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの第2の部分の上方の第2のゲート構造であって、前記第2の部分の四方すべてを包囲する、前記第2のゲート構造と
を備える、半導体デバイス。 - 前記第2のゲート構造は、流動性酸化物部分を含み、前記流動性酸化物部分は、前記誘電体層と、前記pFET領域内の前記複数のフィンのうちの前記少なくとも1つのフィンの前記第2の部分の下部表面との間に配設される、請求項15に記載の半導体デバイス。
- 前記シリコン・ゲルマニウム層のゲルマニウム含有量は、原子量パーセント単位で、5%から60%の範囲にある、請求項15に記載の半導体デバイス。
- 前記シリコン・ゲルマニウム層のゲルマニウム含有量は、原子量パーセント単位で、25%から50%の範囲にある、請求項15に記載の半導体デバイス。
- 前記第1のゲート構造および前記第2のゲート構造は各々、少なくともゲート誘電体材料およびゲート導体を備える、請求項15に記載の半導体デバイス。
- 前記ゲート誘電体材料は、二酸化ケイ素、酸窒化ケイ素、または高誘電率誘電体であり、
前記ゲート導体は、ポリシリコン、または金属である、
請求項19に記載の半導体デバイス。
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