CN108172549A - 一种堆叠式围栅纳米线cmos场效应管结构及制作方法 - Google Patents

一种堆叠式围栅纳米线cmos场效应管结构及制作方法 Download PDF

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CN108172549A
CN108172549A CN201711446763.9A CN201711446763A CN108172549A CN 108172549 A CN108172549 A CN 108172549A CN 201711446763 A CN201711446763 A CN 201711446763A CN 108172549 A CN108172549 A CN 108172549A
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尚恩明
胡少坚
陈寿面
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Shanghai IC R&D Center Co Ltd
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Abstract

本发明公开了一种堆叠式围栅纳米线CMOS场效应管结构，包括：半导体衬底，上下堆叠设于所述半导体衬底上的围栅纳米线N型场效应管和围栅纳米线P型场效应管，所述围栅纳米线N型场效应管和围栅纳米线P型场效应管之间以介质层相隔离。本发明可实现独立控制CMOS中的N型场效应管和P型场效应管，能有效消除短沟道效应和量子效应产生的不利影响，避免平行CMOS器件中可能存在的闩锁效应，提高器件的性能，并可明显缩小CMOS器件的面积占比。本发明还公开了一种堆叠式围栅纳米线CMOS场效应管结构的制作方法。

Description

一种堆叠式围栅纳米线CMOS场效应管结构及制作方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及一种堆叠式围栅纳米线CMOS场效应管结构及制作方法。
背景技术
按照摩尔定律，场效应管的尺寸在不断的缩小。到了40nm工艺节点后，平面器件出现了栅控能力不足，短沟道效应严重等问题，不能满足产业要求。三维器件FinFET通过三面栅控提高了栅控能力，减小了短沟道效应。半导体发展到7nm工艺节点后，沟道长度缩短到20nm以下，半导体材料输运的量子效应逐渐凸显，势必需要寻找其他途径来改善和消除量子效应带来的不利影响。纳米线场效应管采用围栅包围的方式，可最大限度提高栅控能力，改善亚阈值特性。
从平面CMOS器件到三维FinFET器件，场效应管的尺寸缩小，功耗面积比大大减小，器件性能大大提高。一般来说，CMOS场效应管中N型场效应管和P型场效应管在组成的反相器中是共用一个栅极的；但是在不同的器件应用中，并不是所有器件都需要N、P型场效应管共用一个栅极。
同时，平行式的N、P型场效应管需要占用两个场效应管的面积，面对摩尔定律的追求，芯片占用的面积需要越小越好。
此外，平行式的CMOS器件还存在闩锁效应。随着器件尺寸的缩小，其影响会更加明显。
发明内容
本发明的目的在于克服现有技术存在的上述缺陷，提供一种堆叠式围栅纳米线CMOS场效应管结构及制作方法。
为实现上述目的，本发明的技术方案如下：
本发明提供了一种堆叠式围栅纳米线CMOS场效应管结构，包括：半导体衬底，上下堆叠设于所述半导体衬底上的围栅纳米线N型场效应管和围栅纳米线P型场效应管，所述围栅纳米线N型场效应管和围栅纳米线P型场效应管之间以介质层相隔离。
优选地，所述半导体衬底为SOI衬底。
优选地，所述围栅纳米线N型场效应管和围栅纳米线P型场效应管分别包括：由纳米线形成的沟道，横跨沟道的栅极，以及位于沟道两侧纳米线端部的源漏极。
优选地，所述沟道由一至多个纳米线平行排布所构成，所述栅极为高K材料金属栅极，所述介质层为低K材料。
优选地，所述纳米线材料为Si、SiGe或III-V族材料，所述围栅纳米线N型场效应管的源漏极由设于纳米线两端的掺杂C的Si材料形成，所述围栅纳米线P型场效应管的源漏极由设于纳米线两端的SiGe材料形成。
优选地，所述高K材料为二氧化铪，所述金属栅极材料为钨，所述低K材料为SiOC。
优选地，所述栅极两侧具有侧墙。
优选地，所述围栅纳米线N型场效应管位于围栅纳米线P型场效应管的下方或上方。
本发明还提供了一种堆叠式围栅纳米线CMOS场效应管结构的制作方法，包括围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片的制作和连接；其中
所述围栅纳米线N型场效应管芯片的制作包括：
提供一第一体硅衬底，在所述第一体硅衬底上依次淀积底层SiGe层、中间Si层和上层SiGe层，构成超晶格；
刻蚀超晶格，形成一至多个Fin结构，并形成横跨Fin的赝栅极；
从Fin的两端向内刻蚀Fin的底层SiGe层和上层SiGe层材料，直至赝栅极的边缘，使Fin的中间Si层露出，形成Si纳米线；
在赝栅极两侧形成侧墙，并在侧墙两侧生长掺杂C的Si材料，将露出的Si纳米线两端包围，以形成N型场效应管的源漏极；
将赝栅极剥离，并去除赝栅极位置上Fin的底层SiGe层和上层SiGe层材料，使Fin的中间Si层露出，形成作为沟道的Si纳米线；
在沟道位置的Si纳米线表面依次形成栅氧层和高K材料层，并形成横跨Fin的金属栅极；
所述围栅纳米线P型场效应管芯片的制作包括：
提供一第二体硅衬底，在所述第一体硅衬底上依次淀积底层SiGe层、中间Si层和上层SiGe层，构成超晶格；
刻蚀超晶格，形成一至多个Fin结构，并形成横跨Fin的赝栅极；
从Fin的两端向内刻蚀Fin的底层SiGe层和上层SiGe层材料，直至赝栅极的边缘，使Fin的中间Si层露出，形成Si纳米线；
在赝栅极两侧形成侧墙，并在侧墙两侧生长SiGe材料，将露出的Si纳米线两端包围，以形成P型场效应管的源漏极；
将赝栅极剥离，并去除赝栅极位置上Fin的底层SiGe层和上层SiGe层材料，使Fin的中间Si层露出，形成作为沟道的Si纳米线；
在沟道位置的Si纳米线表面依次形成栅氧层和高K材料层，并形成横跨Fin的金属栅极；
将形成的围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片以上下堆叠方式移植到一SOI衬底上，去除第一体硅衬底和第二体硅衬底，并在围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片之间形成低K材料介质层作为隔离层；
将围栅纳米线N型场效应管芯片、围栅纳米线P型场效应管芯片和SOI衬底通过键合进行连接。
优选地，将所述围栅纳米线N型场效应管或围栅纳米线P型场效应管与SOI衬底直接相连。
从上述技术方案可以看出，本发明通过将N型场效应管和P型场效应管采用围栅纳米线场效应管结构堆叠形成上下结构，并以较厚的低K材料介质层进行隔离，从而可以独立控制CMOS中的N型场效应管和P型场效应管，能够有效消除短沟道效应和量子效应产生的不利影响，避免平行CMOS器件中可能存在的闩锁效应，提高器件的性能，并可将CMOS器件面积占比缩小到平行式CMOS器件的50％。
附图说明
图1是本发明一较佳实施例的一种堆叠式围栅纳米线CMOS场效应管结构外形示意图；
图2是图1中隐去侧墙和源漏后的器件结构示意图；
图3是图1中A-A’向的器件结构示意图；
图4是图2中B-B’向的器件结构示意图。
具体实施方式
下面结合附图，对本发明的具体实施方式作进一步的详细说明。
需要说明的是，在下述的具体实施方式中，在详述本发明的实施方式时，为了清楚地表示本发明的结构以便于说明，特对附图中的结构不依照一般比例绘图，并进行了局部放大、变形及简化处理，因此，应避免以此作为对本发明的限定来加以理解。
在以下本发明的具体实施方式中，请参阅图1-图4，图1是本发明一较佳实施例的一种堆叠式围栅纳米线CMOS场效应管结构外形示意图，图2是图1中隐去侧墙和源漏后的器件结构示意图，图3是图1中A-A’向的器件结构示意图，图4是图2中B-B’向的器件结构示意图。如图1-图4所示，本发明的一种堆叠式围栅纳米线CMOS场效应管结构，包括按照上下堆叠方式设置在半导体衬底10和11上的围栅纳米线N型场效应管20和围栅纳米线P型场效应管40。其中，围栅纳米线N型场效应管20可如图1-图4所示的位于围栅纳米线P型场效应管40的下方，或者也可以位于围栅纳米线P型场效应管的上方。围栅纳米线N型场效应管20和围栅纳米线P型场效应管40之间采用介质层30进行器件隔离；介质层隔离结构将围栅纳米线N型场效应管的栅极和围栅纳米线P型场效应管的栅极有效隔离，因而可以独立控制CMOS中的N型场效应管和P型场效应管。
半导体衬底10和11可以采用SOI衬底；SOI衬底可包含下层的Si衬底10和上层的埋氧层(Berried Oxide Layer)11；围栅纳米线N型场效应管20和围栅纳米线P型场效应管40即建立在SOI衬底的埋氧层11上。
围栅纳米线N型场效应管20包括：由纳米线24形成的沟道，横跨沟道的栅极22，以及位于沟道两侧的纳米线端部的源漏极21。其中，定义沟道位于纳米线24的中间位置，纳米线24的两端位置用于设置源漏极21。
同样地，围栅纳米线P型场效应管40也包括：由纳米线44形成的沟道，横跨沟道的栅极42，以及位于沟道两侧的纳米线端部的源漏极41。其中，定义沟道位于纳米线44的中间位置，纳米线44的两端位置用于设置源漏极41。
围栅纳米线N型场效应管20和围栅纳米线P型场效应管40各自的沟道可由一至多个纳米线24、44平行排布所构成。其中，当纳米线为多个时，可将纳米线平行排布，并可按照一排或者堆叠多排形式进行排列。
纳米线24、44的材料可采用Si，也可以采用高迁移率沟道材料如SiGe或III-V族材料(InGaAs GaAs等)。纳米线可采用常规方法制作。
栅极22、44可采用高K材料金属栅极(HKMG)；例如，高K材料金属栅极结构中的高K材料26、46可采用二氧化铪，金属栅极材料可采用钨等。高K材料金属栅极与Si纳米线之间还设有栅氧层25、45，例如可设置二氧化硅栅氧层。栅极22、42的两侧还可具有侧墙23、43，例如可在栅极的两侧设置氮化物侧墙。
用作围栅纳米线N型场效应管和围栅纳米线P型场效应管之间隔离层的介质层30可采用厚度较厚的低K材料形成。例如，可采用SiOC(掺碳二氧化硅)来降低介电常数。
围栅纳米线N型场效应管的源漏极21可由设于例如Si纳米线24两端的掺杂C的Si材料形成。围栅纳米线P型场效应管的源漏极41可由设于例如Si纳米线44两端的SiGe材料形成。
以下通过具体实施方式及附图，对本发明的一种堆叠式围栅纳米线CMOS场效应管结构的制作方法进行详细说明。
请参阅图1-图4。本发明的一种堆叠式围栅纳米线CMOS场效应管结构的制作方法，可用于制作上述的堆叠式围栅纳米线CMOS场效应管结构。其制作方法包括围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片的制作和连接。具体可包括以下步骤：
围栅纳米线N型场效应管芯片的制作包括：
首先，在一个体硅衬底(第一体硅衬底)上依次淀积底层SiGe层、中间Si层和上层SiGe层，例如在体硅衬底上依次淀积约10nm的SiGe层、约5nm的Si层和约10nm的SiGe层，构成由底层SiGe层、中间Si层和上层SiGe层组成的超晶格层。
然后，刻蚀超晶格，形成一至多个Fin(鳍)结构，例如形成宽度约为5nm的一至多个Fin形状。接着，形成横跨Fin的赝栅极，例如，可通过在Fin的中间位置填充宽度约为20nm的多晶硅材料作为赝栅极。
接下来，可从Fin的左右两端向内方向刻蚀Fin结构上的底层SiGe层和上层SiGe层材料，直至赝栅极的边缘。这样，就使得位于Fin结构上、下层之间的中间Si层完全裸露出来，从而形成尺寸约为5nm的Si纳米线24。
接下来，可在赝栅极的两侧形成侧墙23，例如，可在赝栅极的两侧形成厚度约为5nm的氮化物侧墙。然后，在侧墙外的两侧生长掺杂少量C的Si材料(或者先在侧墙外的两侧生长Si材料，再对该Si材料进行掺杂少量的C)，将露出侧墙外的Si纳米线两端包围，从而利用此掺杂少量C的Si材料形成N型场效应管的源漏极21。
之后，将多晶硅赝栅极从器件上剥离掉，并刻蚀去除赝栅极原有位置上Fin的底层SiGe层和上层SiGe层材料，只剩下位于Fin结构上、下层之间的中间Si层完全裸露出来，从而在侧墙内侧也形成尺寸约为5nm的Si纳米线24，作为N型场效应管的沟道。
接下来，可在侧墙内侧沟道位置的Si纳米线表面依次形成栅氧层25和高K材料层26，并形成横跨Fin的金属栅极22；例如，可通过氧化在Si纳米线表面生长约0.7nm的二氧化硅栅氧层，再通过ALD技术淀积约1nm的高K材料如二氧化铪，并采用填充方式在原有的赝栅极位置填充钨作为金属栅极。此时，围栅纳米线N型场效应管20结构即形成。
所述围栅纳米线P型场效应管芯片的制作包括：
首先，同样也在一个体硅衬底(第二体硅衬底)上依次淀积底层SiGe层、中间Si层和上层SiGe层，例如在该体硅衬底上依次淀积约10nm的SiGe层、约5nm的Si层和约10nm的SiGe层，构成由底层SiGe层、中间Si层和上层SiGe层组成的超晶格层。
然后，刻蚀该超晶格，形成一至多个Fin(鳍)结构，例如形成宽度约为5nm的一至多个Fin形状。接着，形成横跨Fin的赝栅极，例如，可通过在Fin的中间位置填充宽度约为20nm的多晶硅材料作为赝栅极。
接下来，可从Fin的左右两端向内方向刻蚀Fin结构上的底层SiGe层和上层SiGe层材料，直至赝栅极的边缘。这样，就使得位于Fin结构上、下层之间的中间Si层完全裸露出来，从而形成尺寸约为5nm的Si纳米线44。
接下来，可在赝栅极的两侧形成侧墙43，例如，可在赝栅极的两侧形成厚度约为5nm的氮化物侧墙。然后，可在侧墙外的两侧生长SiGe材料，将露出侧墙外的Si纳米线两端包围，从而利用此SiGe材料形成P型场效应管的源漏极41。
之后，将多晶硅赝栅极从器件上剥离掉，并刻蚀去除赝栅极原有位置上Fin的底层SiGe层和上层SiGe层材料，只剩下位于Fin结构上、下层之间的中间Si层完全裸露出来，从而在侧墙内侧也形成尺寸约为5nm的Si纳米线44，作为P型场效应管的沟道。
接下来，可在侧墙内侧沟道位置的Si纳米线表面依次形成栅氧层45和高K材料层46，并形成横跨Fin的金属栅极42；例如，可通过氧化在Si纳米线表面生长约0.7nm的二氧化硅栅氧层，再通过ALD技术淀积约1nm的高K材料如二氧化铪，并采用填充方式在原有的赝栅极位置填充钨作为金属栅极。此时，围栅纳米线P型场效应管40结构即形成。
在另一个Si衬底10上通过氧化生长一层二氧化硅埋氧层11作为SOI衬底10和11，例如，可在Si衬底上生长厚度约为10nm的二氧化硅埋氧层作为SOI衬底。进行围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片的连接时，将形成的上述围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片以上下堆叠方式移植到该SOI衬底上，可将围栅纳米线N型场效应管或围栅纳米线P型场效应管与SOI衬底直接相连，不限定其上下。例如，可将上述围栅纳米线N型场效应管芯片倒置放置在SOI衬底的埋氧层11上，使其体硅衬底(第一体硅衬底)朝上，并磨去第一体硅衬底，形成CMOS结构的第一层结构。接着，在上述第一层结构上淀积例如厚度约为30nm的低介电常数材料作为N型场效应管与上层P型场效应管之间的隔离层30。然后，将上述围栅纳米线P型场效应管芯片倒置放置在隔离层30上，使其体硅衬底(第二体硅衬底)朝上，并磨去第二体硅衬底，形成CMOS结构的第二层结构。
最后，可通过键合方式，将围栅纳米线N型场效应管芯片20、围栅纳米线P型场效应管芯片40和SOI衬底埋氧层11进行连接，并使得各部分的电路之间相连接。
综上所述，本发明通过将N型场效应管和P型场效应管采用围栅纳米线场效应管结构堆叠形成上下结构，并以较厚的低K材料介质层进行隔离，实现了CMOS中N型场效应管和P型场效应管的有效隔离，并实现了N型场效应管和P型场效应管的分栅独立控制，根据器件设计的需要，可以在中后道连线过程中决定是否需要分栅控制还是共栅控制。同时，本发明能够有效消除短沟道效应和量子效应产生的不利影响，避免平行CMOS器件中可能存在的闩锁效应，提高CMOS的工作效率和器件的性能，并可将CMOS器件面积占比缩小到平行式CMOS器件的50％。
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (10)

1.一种堆叠式围栅纳米线CMOS场效应管结构，其特征在于，包括：半导体衬底，上下堆叠设于所述半导体衬底上的围栅纳米线N型场效应管和围栅纳米线P型场效应管，所述围栅纳米线N型场效应管和围栅纳米线P型场效应管之间以介质层相隔离。
2.根据权利要求1所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述半导体衬底为SOI衬底。
3.根据权利要求1所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述围栅纳米线N型场效应管和围栅纳米线P型场效应管分别包括：由纳米线形成的沟道，横跨沟道的栅极，以及位于沟道两侧纳米线端部的源漏极。
4.根据权利要求3所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述沟道由一至多个纳米线平行排布所构成，所述栅极为高K材料金属栅极，所述介质层为低K材料。
5.根据权利要求4所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述纳米线材料为Si、SiGe或III-V族材料，所述围栅纳米线N型场效应管的源漏极由设于纳米线两端的掺杂C的Si材料形成，所述围栅纳米线P型场效应管的源漏极由设于纳米线两端的SiGe材料形成。
6.根据权利要求4所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述高K材料为二氧化铪，所述金属栅极材料为钨，所述低K材料为SiOC。
7.根据权利要求1或4所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述栅极两侧具有侧墙。
8.根据权利要求1所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，所述围栅纳米线N型场效应管位于围栅纳米线P型场效应管的下方或上方。
9.一种堆叠式围栅纳米线CMOS场效应管结构的制作方法，其特征在于，包括围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片的制作和连接；其中
所述围栅纳米线N型场效应管芯片的制作包括：
提供一第一体硅衬底，在所述第一体硅衬底上依次淀积底层SiGe层、中间Si层和上层SiGe层，构成超晶格；
刻蚀超晶格，形成一至多个Fin结构，并形成横跨Fin的赝栅极；
从Fin的两端向内刻蚀Fin的底层SiGe层和上层SiGe层材料，直至赝栅极的边缘，使Fin的中间Si层露出，形成Si纳米线；
在赝栅极两侧形成侧墙，并在侧墙两侧生长掺杂C的Si材料，将露出的Si纳米线两端包围，以形成N型场效应管的源漏极；
将赝栅极剥离，并去除赝栅极位置上Fin的底层SiGe层和上层SiGe层材料，使Fin的中间Si层露出，形成作为沟道的Si纳米线；
在沟道位置的Si纳米线表面依次形成栅氧层和高K材料层，并形成横跨Fin的金属栅极；
所述围栅纳米线P型场效应管芯片的制作包括：
提供一第二体硅衬底，在所述第一体硅衬底上依次淀积底层SiGe层、中间Si层和上层SiGe层，构成超晶格；
刻蚀超晶格，形成一至多个Fin结构，并形成横跨Fin的赝栅极；
从Fin的两端向内刻蚀Fin的底层SiGe层和上层SiGe层材料，直至赝栅极的边缘，使Fin的中间Si层露出，形成Si纳米线；
在赝栅极两侧形成侧墙，并在侧墙两侧生长SiGe材料，将露出的Si纳米线两端包围，以形成P型场效应管的源漏极；
将赝栅极剥离，并去除赝栅极位置上Fin的底层SiGe层和上层SiGe层材料，使Fin的中间Si层露出，形成作为沟道的Si纳米线；
在沟道位置的Si纳米线表面依次形成栅氧层和高K材料层，并形成横跨Fin的金属栅极；
将形成的围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片以上下堆叠方式移植到一SOI衬底上，去除第一体硅衬底和第二体硅衬底，并在围栅纳米线N型场效应管芯片和围栅纳米线P型场效应管芯片之间形成低K材料介质层作为隔离层；
将围栅纳米线N型场效应管芯片、围栅纳米线P型场效应管芯片和SOI衬底通过键合进行连接。
10.根据权利要求9所述的堆叠式围栅纳米线CMOS场效应管结构，其特征在于，将所述围栅纳米线N型场效应管或围栅纳米线P型场效应管与SOI衬底直接相连。
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