CN106020768A - 用于高基数乘法器电路的组合的加法器和预加法器 - Google Patents

用于高基数乘法器电路的组合的加法器和预加法器 Download PDF

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CN106020768A
CN106020768A CN201610179348.0A CN201610179348A CN106020768A CN 106020768 A CN106020768 A CN 106020768A CN 201610179348 A CN201610179348 A CN 201610179348A CN 106020768 A CN106020768 A CN 106020768A
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CN106020768B (zh
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M·朗哈默
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Altera Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders

Abstract

本发明涉及用于高基数乘法器电路的组合的加法器和预加法器。接受第一输入值和第二输入值，并且输出(a)涉及该第一输入值和第二输入值的第一和数，以及(b)涉及第一输入值和第二输入值的第二和数的电路装置包括第一加法器电路、第二加法器电路、压缩器电路以及预处理级。该第一输入值和第二输入值被输入到该第一加法器电路以提供第一和数。该第一输入值和第二输入值被输入到预处理级以提供至压缩器电路的输入，压缩器电路提供第一和第二经压缩的输出信号，其又被输入至第二加法器电路以提供第二和数。该预处理级可以包括将第一输入值可编程地置零的电路装置，从而使得第一和数能够被可编程地设定到第二输入值。

Description

用于高基数乘法器电路的组合的加法器和预加法器
技术领域
本发明涉及一种能够被用于使高基数乘法器的初始加法器与可选的预加法器进行组合的电路装置。
背景技术
执行数学运算的某些类型的电路可能要求多个加法器电路，诸如进位传播加法器或行波进位加法器，这是低效的。例如，在对称有限冲击响应(FIR)滤波器中，输入可能在做乘法之前就相加，这减少了乘法器的数量。然而，该加法运算要求预加法器，并且然后乘法本身可以包括压缩器以及随后的另一加法器。提供多个加法器耗费了大量的集成电路器件面积，这在诸如现场可编程门阵列(FPGA)的可编程逻辑器件中特别重要。
此外，诸如在FIR滤波器中遇到的大数乘法问题，可能要求大的压缩器树。压缩器树的尺寸可以通过增加乘法器的基数来降低，但是这又可能要求输入的非二次方操作，其不能够通过简单的移位来执行(如针对二次方操作可以进行的那样)，并且可能导致需要更多的加法器。
发明内容
根据本发明的实施例，自身可能包括多个加法器(例如加法器-复用器-加法器结构)的加法器-乘法器-加法器结构的初始加法器或预加法器可以通过提供压缩器以及随后的加法器(例如压缩器-加法器-加法器结构)来简化。并且因为加法器将是彼此相邻的，所以它们可以被组合成单个加法器。
因此，根据本发明的实施例，提供了一种电路装置，该电路装置接受第一输入值和第二输入值，并且输出(a)涉及第一输入值和第二输入值的第一和数，以及(b)涉及第一输入值和第二输入值的第二和数。该电路装置包括第一加法器电路、第二加法器电路、压缩器电路以及预处理级。该第一输入值和第二输入值被输入到该第一加法器电路以提供第一和数。该第一输入值和第二输入值被输入到预处理级以提供至压缩器电路的输入。压缩器电路提供第一和第二经压缩的输出信号。第一和第二经压缩的输出信号被输入至第二加法器电路以提供第二和数。
该预处理级可以包括将第一输入值可编程地置零的电路装置，从而使得第一和数能够被可编程地设定到第二输入值。
压缩器电路可以包括用于处理相应的位位置的相应的分开的电路装置。对于相应的位位置，相应的分开的电路装置可以具有第一和第二输入值中的每一个输入值的相应的位以及第一和第二输入值中的每一个输入值的相应的下一更低有效位作为输入，并且还可以包括组合第一和第二输入值中的每一个输入值的相应的位的异或门。在用于相应的位位置的相应的分开的电路装置中的异或门的输出可以与用于下一更高有效位的位置的相应的分开的电路装置共享。
在用于相应的位位置的相应的分开的电路装置中，第一和第二输入值中的每一个输入值的相应的下一更低有效位可以是从用于下一更低有效位的位置的相应的分开的电路装置处借位的。
第一加法器电路可以包括前缀树，该前缀树具有第一和第二输入值的相应的位作为输入，并提供用于每个位位置的相应的进位值作为输出。第一加法器电路还可以包括用于每个位位置的相应的异或门，每个相应的异或门具有用于该相应的位位置的相应的进位值、以及在用于该相应的位位置的相应的分开的电路装置中的该异或门的该输出作为输入。
附图说明
通过考虑下面的详细描述并结合附图，本发明的进一步的特点，其属性和许多优点是显而易见的。在附图中，相似的附图标记始终指代类似的部件，并且其中：
图1示出了数字信号处理(DSP)模块的简化表示；
图2示出了可以被提供在DSP模块的输入级中以提供输入和该输入与‘3’的乘积的输入处理电路装置的示例；
图3示出了根据本发明的实施例的输入处理电路装置；
图4示出了压缩器电路的一部分的内部结构的示例；
图5示出了根据本发明的压缩器电路的第一实施例的一部分的内部结构；
图6示出了根据本发明的压缩器电路的第二实施例的一部分的内部结构；
图7示出了进位传播加法器的内部结构的示例；
图8示出了Kogge-Stone前缀树的一部分；
图9示出了根据本发明的进位传播加法器的实施例的内部结构；
图10示出了在Kogge-Stone前缀树的第一层中的每个节点处可以如何确定产生输出和传播输出的示例；
图11示出了在Kogge-Stone前缀树的第一层之外的每个层中的每个节点处可以如何确定产生输出和传播输出的示例；
图12示出了图10和图11的产生和传播结构可以如何在根据本发明的实施例的特定情况中被组合；
图13示出了图12的产生和传播结构可以如何根据本发明的实施例被简化；以及
图14是采用体现本发明的可编程逻辑器件的示例性系统的简化方框图。
具体实施方式
下文中的讨论将基于诸如FPGA的可编程集成电路器件的示例。然而，应当注意，这里公开的主题可以被使用在任意类型的固定或可编程器件中。
图1示出了数字信号处理(DSP)模块100的简化表示，该类型可以在许多类型的集成电路器件中找到，包括例如：诸如FPGA的可编程器件。DSP模块100可以包括多个乘法器101以及随后的加法器/累加器电路装置102，加法器/累加器电路装置102可以包括多个加法器112和寄存器122，以及在没有进一步组合的情况下导出个体乘法结果的能力。此外，输入级103可以包括各种类型的用于输入信号的预乘法操作的电路，例如寄存器、移位器、复用器以及加法器(未示出)。
如上文讨论的，可以期望增加乘法器101的基数。具有输入X和Y的4-基数乘法器也将需要输入2X和2Y。这样的输入能够简单地通过将X和Y向左移一位位置来提供。然而，通常被用于较高基数运算的8-基数乘法器，会要求不能通过移位提供的3X和3Y。
图2示出了可以被提供在输入级103中以在不使用另外的乘法器的情况下提供输入和该输入与‘3’的乘积两者的输入处理电路装置200的示例。该示例进一步包括两个输入的预加法，这可以用于上面所讨论的对称滤波器实施方式中。因此，在图2中示出的输入A和B不应被视作上文讨论的输入X和Y的等同物。相反，在图2中的输出对应于输入X或输入Y。也就是说，输入X与输入Y两者都可以由这样的电路装置所处理。
加法器201将输入A和B相加。乘法器202选择和数211(A+B)或输入B作为其输入。因此，输入处理电路装置200的输出212根据由复用器202所做的选择而是(A+B)或B。输出212还被路由至加法器203和移位器204两者。移位器204将输出212向左移一位，从而有效地将输出202乘以‘2’。移位器输出214通过加法器203与输出212相加。因此，输出213根据由复用器202所做的选择而是3(A+B)或3B。
虽然输入处理电路装置200达到所期望的提供‘3’和另一输入的乘积的结果，其中该输入可以是单个数字或两个相加的数字(如在对称滤波器示例中的)，但是其加法器-复用器-加法器结构效率低下，耗费了可观的器件面积。
根据本发明的实施例的改进的输入处理电路装置300被示出在图3中，并且包括压缩器301以及随后的两个加法器320、303，加法器可以例如是进位传播加法器。输入处理电路装置300还具有预处理级和与(AND)门305，预处理级包括移位器304以从输入A和B提供输入2A和2B，以及与门305用于提供复用器202的选择功能。与门305具有第二输入(未示出)，第二输入使得与门305能够通过将‘0’或‘1’输入到该第二输入而被作为开关使用。
如果与门305被打开(通过将‘1’输入到其第二输入)，压缩器301压缩输入2A、A、2B和B以提供表示3(A+B)的冗余形式的和数矢量311和进位矢量321，其通过进位传播加法器302相加以提供输出3(A+B)。如果与门305被关闭(通过将‘0’输入到其第二输入，由此将‘A’输入可编程地置零)，加法器302提供输出3B。
同时，如果与门305被打开，则加法器303提供输出A+B，而如果与门305被关闭，则加法器303提供输出B。尽管加法器303可以是上文提及的标准进位传播加法器，但是其可以如在下文中更加详细地讨论的那样被更改。这样的更改可以要求A异或(XOR)B的输入，其可选地可以由压缩器301以在下文中描述的方式在331处提供。
在图3中示出的结构以更有效的压缩器-和-并联-加法器的结构取代了在图2中的加法器-复用器-加法器的结构。根据本发明的实施例的进一步的实施方式，该电路装置可以更加有效。
图4示出了根据已知的压缩器结构的、如图3中的、用于将四个输入相加的4-2压缩器的三个位401、402、403的内部结构的示例。虽然在图3中示出的压缩器架构相对有效，但是可以针对在此讨论的特定运算而改进效率，因为输入的关系使得相邻的位位置共享特定的输入。例如，异或门411和422具有相同的输入。因此，在图5中示出的结构500中，异或门411由于连接501而可以被消除。类似地，异或门412和423具有相同的输入，意味着在结构500中，异或门412由于连接502而可以被消除。并且，异或门413与在右边(在附图的方向中)的下一位中的不可见的异或门共享输入，使得异或门413由于连接503而可以被消除。以同样的方式，连接504可以消除左边的下一位的不可见的异或门。
在图6中示出的进一步的优化中，在之前的段落中涉及的公共输入可以由连接601、602、603、604来取代。具体地，代替将Ax-1和Bx-1输入到两个位401、402，Ax-1和Bx-1可以被输入到位402并且由导体601被传导至位401。类似地，代替将Ax-2和Bx-2输入到两个位402、403，Ax-2和Bx-2可以被输入到位403并且由导体602被传导至位402。类似地，导体603可以将不可见的Ax-3和Bx-3输入从位403的右边的不可见的位带到位403，以及导体604可以将Ax和Bx输入从位401带到位401的左边的不可见的位。
如上文描述的，图3包括两个进位传播加法器302、303，其中的一个(进位传播加法器302)将表示3(A+B)(或3B)的和数和进位矢量相加，以及其中一个(进位传播加法器303)将A与B相加。常规的、具有输入X和Y的加法器可具有如图7所示出的结构700，其中M(710)以及N(720)的各个位被输入到前缀树701(在图8中示出了Kogge-Stone前缀树800，尽管许多其他的前缀树架构可以是适合的并且可以被使用；前缀树的架构的选择可以取决于特定的设计)以提供进位输出711。M(710)以及N(720)的位还通过异或门702被异或在一起，并且该异或结果712通过具有进位输出711的异或门703被进一步异或。在图3中的在压缩器之后的进位传播加法器的情况下，各种M和N输入会分别是和数和进位输出S和C的位。
根据本发明的另一个实施例，进位传播加法器303可以通过消除异或门702来简化，因为用于A+B计算的异或的结果已经在压缩器301中异或门421、422、423处是可用的。因此，进位传播加法器303会具有在图9中示出的结构，其中各个M和N输入将分别是A和B的位(参阅在图6中的Ax、Bx、Ax-1、Bx-1、Ax-2、Bx-2等)，并且各个P会是A异或B的位(参阅在图6中的ABx、ABx-1、ABx-2等)。
本发明的另一实施例依赖于这样的事实，即进位传播加法器203具有相对于彼此已知的关系，也就是，第二输入是第一输入的两倍或，换言之，第二输入是向左移一位的第一输入。因此，第二输入的每个位位置可以由第一输入的下一最左边的位位置来表示，或第一输入的每个位位置可以由第二输入的下一最右边的位位置来表示。根据该实施例，进位传播加法器203可以通过改变其如下文所讨论的前缀树来简化。
再次参考在图8中示出的Kogge-Stone前缀树800，图8中的每个点表示产生节点和传播节点。通常，传播节点不是输出，而产生节点提供被输入到异或门703的进位输出711，如图7所示。图10示出了在前缀树800的第一行中使用的结构的示例。在该第一行中的每个位位置处的两个输入位被用于创建产生输出1011以及传播输出1021。如图10所示，产生输出1011可以在1010处通过对两个输入求与创建，以及传播输出1021可以在1020处通过对两个输入求或创建。图10被绘制成示出了具有输入X2和Y2的位位置2的示例，但是对于(具有输入Xn和Yn的)任意位位置也是相同的。
在前缀树800中的每个后续的节点可以包括如在图11中所示出的结构以使用图11的逻辑结构来计算其产生输出1111和其传播输出1121。(在图10和11中，索引--(0，N，N+1)--指代前缀树800的层--也就是，在图8中的行中，其中顶行具有索引0--以及下标指代位位置--也就是在图8中的列中，最右边的行是位位置0。如之前在上文中指出的，图10表示任意位位置n，其中示出n＝2。类似地，图11表示任意位位置x，其不同于图10中的输入X。)。
在其中X+Y＝A+2A的情况下，这些结构能够被简化。为了避免混淆，令A＝C，使得A+2A＝C+(C<<1),(其中“<<”表示向左移位操作，其对于二进制数来说等价于乘以2)。在这样的加法运算中，两个输出的位位置将排列成以下情况：
C5 C4 C3 C2
C5 C4 C3 C2
应当注意，在该示例中，虽然仅仅示出了每个输入的四个位(从C5至C2)，但是位向右延伸至第0个位，位向左延伸至所要求的最高位。由此，可以看出在图10中的任意Xn、Yn输入的对变为Cn、Cn-1。
然后以位位置n＝5作为示例，并且将A5以及A4(如上文说明A＝C)输入至用于前缀树800的行0的在图10中示出的结构，并且然后将该结构代入到在图11中示出的用于前缀树800的行1的结构中，产生在图12中示出的逻辑结构，用于针对行0和行1的组合的位位置n＝5。简化图12中的逻辑结构生成图13的逻辑结构。因此，对于加法器的两个输入是数字以及该数字的两倍的情况，那么在器件面积的方面，随后可以将前缀树的初始行显著地减少到图13的结构。
如从图8可以看出的，Kogge-Stone前缀树在其较早的行中相较于在其较晚的行中具有更多的节点。将理解，在加法器使用Kogge-Stone前缀树或具有相似架构的任意前缀树来构建的情况下，根据在图10-图13中实施的实施例的初始行的简化能够将由前缀树所耗费的整个器件面积减少大约在15％至25％之间，这取决于所使用的特定的前缀树架构。
因此，看出，针对实施特定类型的算术运算，诸如在用于乘法器的加法运算和预加法运算之间的选择，加法器电路装置基于逻辑简化或共享逻辑可以被提供为具有减小的面积。
被配置为包括根据本发明的任意实施方式的算术电路装置PLD180可以被使用在许多类型的电子器件中。一个可能的应用是在图14示出的示例性的数据处理系统1800中。数据处理系统1800可以包括以下组件中的一个或多个：处理器1801；存储器1802；I/O电路装置1803；以及外围设备1804。这些组件通过系统总线1805耦合在一起并且被构造在包含在终端用户系统1807中的电路板1806上。
系统1800能够被使用在广泛的多种应用中，诸如计算机网络、数据网络、仪器、视频处理、数据信号处理、远程无线电头(RRH)、或在其中使用可编程的或可重新编程的逻辑的优点是能够期望的任意其他的应用。PLD 180能够被用于执行多种不同的逻辑功能。例如，PLD 180能够被配置为处理器或控制器，其与处理器1801协同工作。PLD 180也可以被用作仲裁器以对至系统1800的共享资源的访问进行仲裁。在又一实施例中，PLD 180能够配置为在处理器1801和在系统1800中的其他组件中一个组件之间的接口。应当注意，系统1800仅仅是示例性的，本发明的真正范围和精神应当通过下面的权利要求来指明。
不同的技术能够被用于实施如上文描述的以及结合本发明的PLD 180。
将理解，前述部分仅仅说明本发明的原理，并且本领域的技术人员能够在不背离本发明的范围和精神的情况下做出修改。例如，本发明的各个元件能够以任意的所期望的数量和/或布置被提供在PLD上。本领域的技术人员应当理解，本发明能够通过除了在此描述的实施例之外的实施例来实现，这里描述的实施例被提出仅仅是处于说明的目的而非限制，并且本发明仅由下面的权利要求所限定。
电路装置可以接受第一输入值和第二输入值并且输出涉及所述第一输入值和所述第二输入值的第一和数，以及涉及所述第一输入值和所述第二输入值的第二和数。该电路装置可以包括第一加法器电路、第二加法器电路、压缩器电路以及预处理级，其中所述第一输入值和所述第二输入值被输入到所述第一加法器电路以提供所述第一和数，所述第一输入值和所述第二输入值被输入到所述预处理级以提供至所述压缩器电路的输入，所述压缩器电路提供第一经压缩的输出信号和第二经压缩的输出信号，并且所述第一经压缩的输出信号和所述第二经压缩的输出信号被输入至所述第二加法器电路以提供所述第二和数。
在一些实施例中，所述第一加法器电路以及所述第二加法器电路是进位传播加法器。
根据一些实施例，所述预处理级可以包括将所述第一输入值可编程地置零的电路装置，从而所述第一和数能够被可编程地设定到所述第二输入值。
在一些实施例中，将所述第一输入值可编程地置零的所述电路装置包括具有所述第一输入值和接地作为输入的与门。
根据一些实施例，所述预处理级可以包括使所述第一输入值和所述第二输入值中的每一个输入值加倍以与所述第一输入值和所述第二输入值一起输入到所述压缩器电路的电路装置，从而所述第二和数是所述第一和数的三倍。
在一些实施例中，所述压缩器电路可以包括用于处理相应的位位置的相应的分开的电路装置。对于相应的位位置，所述相应的分开的电路装置具有所述第一输入值和所述第二输入值中的每一个输入值的相应的位、以及所述第一输入值和所述第二输入值中的每一个输入值的相应的下一更低有效位作为输入，以及进一步包括组合所述第一输入值和所述第二输入值中的每一个输入值的所述相应的位的异或门。在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的输出与用于下一更高有效位位置的相应的分开的电路装置共享。
在一些实施例中，在用于所述相应的位位置的所述相应的分开的电路装置中，所述第一输入值和所述第二输入值中的每一个输入值的所述相应的下一更低有效位位从用于下一更低有效位位置的相应的分开的电路装置借位。
根据一些实施例，所述第一加法器电路可以包括前缀树，所述前缀树具有所述第一输入值和所述第二输入值的相应的位作为输入，并且提供用于每个位位置的相应的进位值作为输出；以及用于所述每个位位置的相应的异或门，每个相应的异或门具有用于所述相应的位位置的所述相应的进位值、以及在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的所述输出作为输入。
在一些实施例中，所述前缀树是Kogge-Stone前缀树。
用于具有彼此已知的关系的两个输入值的加法器电路装置可以包括：用于每个位位置的相应的输入异或门，每个相应的输入异或门具有所述输入值的相应的位作为输入；前缀树，具有所述输入值的相应的位作为输入，并且提供用于每个位位置的相应的进位值作为输出；以及用于每个位位置的相应的输出异或门，每个相应的输出异或门具有用于所述相应的位位置的所述相应的进位值、以及所述相应的输入异或门的所述输出作为输入；其中所述前缀树根据所述已知的关系进行自定义。
根据一些实施例，所述已知的关系包括所述输入值中的一个输入值是所述输入值中的另一输入值的两倍；以及根据所述已知的关系自定义所述前缀树包括基于所述输入值中的所述一个输入值的每个相应的位与所述输入值中的所述另一输入值的相应的下一更低有效位相同来构建所述前缀树的初始层。
在一些实施例中，所述初始层的所述构建包括折叠(collapse)所述前缀树的第一层和第二层。
根据一些实施例，所述前缀树基于Kogge-Stone前缀树。
电路装置可以接受第一输入值和第二输入值并且输出涉及所述第一输入值和所述第二输入值的第一和数，以及涉及所述第一输入值和所述第二输入值的第二和数。所述电路装置可以包括第一加法器电路；第二加法器电路；压缩器电路；以及预处理级，所述预处理级包括将所述第一输入值可编程地置零的电路装置；从而所述第一和数能够被可编程地设定到所述第二输入值，以及所述第二和数可编程为独立于所述第一输入值。
根据一些实施例，将所述第一输入置零的所述电路装置包括具有所述第一输入值和接地作为输入的与门。
在一些实施例中，所述第一输入值和所述第二输入值被输入到所述第一加法器电路以提供所述第一和数；所述第一输入值和所述第二输入值被输入到所述预处理级以提供至所述压缩器电路的输入，所述压缩器电路提供第一经压缩的输出信号和第二经压缩的输出信号；所述第一经压缩的输出信号和所述第二经压缩的输出信号被输入至所述第二加法器电路以提供所述第二和数。
根据一个实施例，所述第一加法器电路以及所述第二加法器电路是进位传播加法器。
根据一个实施例，所述预处理级包括使所述第一输入值和所述第二输入值中的每一个输入值加倍以与所述第一输入值和所述第二输入值一起输入到所述压缩器电路的电路装置；从而所述第二和数是所述第一和数的三倍。
在一个实施例中，所述压缩器电路包括用于处理相应的位位置的相应的分开的电路装置；对于相应的位位置，所述相应的分开的电路装置具有所述第一输入值和所述第二输入值中的每一个输入值的相应的位、以及所述第一输入值和所述第二输入值中的每一个输入值的相应的下一更低有效位作为输入，以及进一步包括组合所述第一输入值和所述第二输入值中的每一个输入值的所述相应的位的异或门；以及在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的输出与用于下一更高有效位位置的相应的分开的电路装置共享。
根据一个实施例，在用于所述相应的位位置的所述相应的分开的电路装置中，所述第一输入值和所述第二输入值中的每一个输入值的所述相应的下一更低有效位从用于下一更低有效位位置的相应的分开的电路装置借位。
在一个实施例中，所述第一加法器电路包括前缀树，所述前缀树具有所述第一输入值和所述第二输入值的相应的位作为输入，并且提供用于每个位位置的相应的进位值作为输出；以及用于所述每个位位置的相应的异或门，每个相应的异或门具有用于所述相应的位位置的所述相应的进位值、以及在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的所述输出作为输入。
在一个实施例中，所述前缀树为Kogge-Stone前缀树。

Claims (15)

1.一种电路装置，所述电路装置接受第一输入值和第二输入值并且输出(a)涉及所述第一输入值和所述第二输入值的第一和数，以及(b)涉及所述第一输入值和所述第二输入值的第二和数，所述电路装置包括：
第一加法器电路；
第二加法器电路；
压缩器电路；以及
预处理级；其中：
所述第一输入值和所述第二输入值被输入到所述第一加法器电路以提供所述第一和数；
所述第一输入值和所述第二输入值被输入到所述预处理级以提供至所述压缩器电路的输入，所述压缩器电路提供第一经压缩的输出信号和第二经压缩的输出信号；
所述第一经压缩的输出信号和所述第二经压缩的输出信号被输入至所述第二加法器电路以提供所述第二和数。
2.根据权利要求1所述的电路装置，其中所述第一加法器电路以及所述第二加法器电路是进位传播加法器。
3.根据权利要求1所述的电路装置，其中：
所述预处理级包括将所述第一输入值可编程地置零的电路装置；从而：
所述第一和数能够被可编程地设定到所述第二输入值。
4.根据权利要求1所述的电路装置，其中：
所述预处理级包括使所述第一输入值和所述第二输入值中的每一个输入值加倍以与所述第一输入值和所述第二输入值一起输入到所述压缩器电路的电路装置；从而：
所述第二和数是所述第一和数的三倍。
5.根据权利要求1所述的电路装置，其中：
所述压缩器电路包括用于处理相应的位位置的相应的分开的电路装置；
对于相应的位位置，所述相应的分开的电路装置具有所述第一输入值和所述第二输入值中的每一个输入值的相应的位、以及所述第一输入值和所述第二输入值中的每一个输入值的相应的下一更低有效位作为输入，以及进一步包括组合所述第一输入值和所述第二输入值中的每一个输入值的所述相应的位的异或门；以及
在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的输出与用于下一更高有效位位置的相应的分开的电路装置共享。
6.根据权利要求5所述的电路装置，其中在用于所述相应的位位置的所述相应的分开的电路装置中，所述第一输入值和所述第二输入值中的每一个输入值的所述相应的下一更低有效位从用于下一更低有效位位置的相应的分开的电路装置借位。
7.根据权利要求5所述的电路装置，其中所述第一加法器电路包括：
前缀树，所述前缀树具有所述第一输入值和所述第二输入值的相应的位作为输入，并且提供用于每个位位置的相应的进位值作为输出；以及
用于每个位位置的相应的异或门，每个相应的异或门具有用于所述相应的位位置的所述相应的进位值、以及在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的所述输出作为输入。
8.根据权利要求7所述的电路装置，其中所述前缀树是Kogge-Stone前缀树。
9.一种电路装置，所述电路装置接受第一输入值和第二输入值并且输出(a)涉及所述第一输入值和所述第二输入值的第一和数，以及(b)涉及所述第一输入值和所述第二输入值的第二和数，所述电路装置包括：
第一加法器电路；
第二加法器电路；
压缩器电路；以及
预处理级，包括将所述第一输入值可编程地置零的电路装置；从而：
所述第一和数能够被可编程地设定到所述第二输入值，以及所述第二和数可编程为独立于所述第一输入值。
10.根据权利要求9所述的电路装置，其中将所述第一输入值置零的所述电路装置包括具有所述第一输入值和接地作为输入的与门。
11.根据权利要求9所述的电路装置，其中：
所述第一输入值和所述第二输入值被输入到所述第一加法器电路以提供所述第一和数；
所述第一输入值和所述第二输入值被输入到所述预处理级以提供至所述压缩器电路的输入，所述压缩器电路提供第一经压缩的输出信号和第二经压缩的输出信号；
所述第一经压缩的输出信号和所述第二经压缩的输出信号被输入至所述第二加法器电路以提供所述第二和数。
12.根据权利要求9所述的电路装置，其中：
所述预处理级包括使所述第一输入值和所述第二输入值中的每一个输入值加倍以与所述第一输入值和所述第二输入值一起输入到所述压缩器电路的电路装置；从而：
所述第二和数是所述第一和数的三倍。
13.根据权利要求9所述的电路装置，其中：
所述压缩器电路包括用于处理相应的位位置的相应的分开的电路装置；
对于相应的位位置，所述相应的分开的电路装置具有所述第一输入值和所述第二输入值中的每一个输入值的相应的位、以及所述第一输入值和所述第二输入值中的每一个输入值的相应的下一更低有效位作为输入，以及进一步包括组合所述第一输入值和所述第二输入值中的每一个输入值的所述相应的位的异或门；以及
在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的输出与用于下一更高有效位位置的相应的分开的电路装置共享。
14.根据权利要求13所述的电路装置，其中在用于所述相应的位位置的所述相应的分开的电路装置中，所述第一输入值和所述第二输入值中的每一个输入值的所述相应的下一更低有效位从用于下一更低有效位位置的相应的分开的电路装置借位。
15.根据权利要求13所述的电路装置，其中所述第一加法器电路包括：
前缀树，所述前缀树具有所述第一输入值和所述第二输入值的相应的位作为输入，并且提供用于每个位位置的相应的进位值作为输出；以及
用于每个位位置的相应的异或门，每个相应的异或门具有用于所述相应的位位置的所述相应的进位值、以及在用于所述相应的位位置的所述相应的分开的电路装置中的所述异或门的所述输出作为输入。
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