US6539413B1 - Prefix tree adder with efficient sum generation - Google Patents
Prefix tree adder with efficient sum generation Download PDFInfo
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- US6539413B1 US6539413B1 US09/525,644 US52564400A US6539413B1 US 6539413 B1 US6539413 B1 US 6539413B1 US 52564400 A US52564400 A US 52564400A US 6539413 B1 US6539413 B1 US 6539413B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
- G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder
Definitions
- the present invention relates generally to electronic circuits and more particularly to adder circuits for use in semiconductor integrated circuits and other electronic devices.
- the recursive carry computation can also be reduced to a prefix computation, as described in, e.g., P. M. Kogge and H. S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. on Computers, Vol. C-22, No.8, pp. 786-793, August 1973.
- a prefix tree can be used to compute the carry at the most-significant bit position, and an additional tree superimposed on the prefix tree can be used to compute the intermediate carries.
- a problem associated with the above-noted full prefix tree adders which are also known as Kogge-Stone adders, is the additional delay introduced as a result of exponentially growing interconnection complexity.
- Existing architecture tradeoffs have emphasized reduction of interconnection complexity at the expense of higher gate fanouts.
- Interconnection complexity can also be reduced by using hybrid carry lookahead/carry select architectures which eliminate the need to implement a full prefix tree for each bit position.
- the use of low resistance and low capacitance materials can reduce the negative effects of architectures that depend on large amounts of interconnect, as described in J. Silberman et al., “A 1.0 GHz Single-Issue 64b PowerPC Integer Processor,” IEEE Intl. Solid-State Circuits Conf., pp. 230-231, February 1998.
- the area overhead required to implement such adders is alleviated through the use of extensive “over-the-cell” routing, which removes the routing channels and further minimizes the interconnect capacitance.
- g j a j ⁇ b j
- p j a j ⁇ b j
- c j g j + p j ⁇ c j - 1
- s j p j ⁇ c j - 1 ⁇ ⁇ ⁇ ⁇ j ⁇ 0 ⁇ j ⁇ n
- c ⁇ 1 is the primary carry-input.
- the signals designated g j , p j and c j are referred to herein as generate, propagate and carry signals, respectively.
- the fundamental carry operator o is both associative and idempotent. At each bit position, the carry is given by
- c ⁇ 1 is the primary carry input. If there is no primary carry input, then c j is simply G 0 j .
- An additional speedup in the above-described conventional prefix tree adder can be achieved by using transmit signals t j instead of propagate signals p j to compute the carries for each bit position.
- the final sum computation still requires the propagate signals p j to be generated from the primary inputs.
- c ⁇ 1 is the primary carry input. If there is no primary carry input, then c j is simply G 0 j .
- the t j signals can be computed faster than the p j signals since an OR gate is typically faster than an XOR gate. Hence, the carry computation through the prefix trees can start slightly earlier if the transmit signals are used. Since the sum generation step still uses the propagate signals, the load on the transmit signals in this architecture is smaller than the load on the propagate signals in the architecture which uses the p j signals to compute the carries. However, the load on the input signals is now higher since both transmit and propagate signals need to be generated.
- the invention provides an improved prefix tree adder in which a significant delay reduction is achieved by implementing sum computation logic circuitry in a final stage of the adder so as to exploit the differing delays with which group-generate (G), group-transmit (T) and intermediate carries (c) are generated. Previous adder designs have not exploited these final-stage delay differences to reduce the overall computation delay of the adder.
- an n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages.
- the computation stages for each of the bit positions include a sum computation stage implemented in logic circuitry.
- the corresponding sum computation logic circuitry computes a sum based at least in part on group-generate, group-transmit and intermediate carry signals.
- the sum computation logic circuitry is configured to exploit differences in delay associated with generation of the group-generate, group-transmit and intermediate carry signals, so as to reduce the total computational delay of the adder.
- additional delay reduction may be achieved by configuring the sum computation stages of the adder in accordance with a left-to-right routing of most-significant group-generate and group-transmit signals, such that the most-significant half of the sum bits are generated in the same prefix trees in which the least-significant half of the sum bits are generated.
- the adder architecture of the present invention provides a reduced computational delay relative to conventional architectures.
- the techniques of the invention are applicable to a wide variety of prefix tree adders, including both radix-2 adders and non-radix-2 adders.
- FIG. 1 shows a set of prefix trees for an n-bit prefix tree adder with carry incorporated into the tree as described in the above-cited U.S. patent application Ser. No. 09/291,677.
- FIG. 2 is a diagram illustrating maximum accumulated stage delays for a 32-bit prefix tree adder of the type illustrated in FIG. 1 .
- FIG. 3 ( a ) shows logic circuitry used in the last stage of a prefix tree adder of the type illustrated in FIG. 1 for calculating a final sum result.
- FIGS. 3 ( b ) and 3 ( c ) show logic circuitry used in the last stage of a prefix tree adder for calculating a final sum result, in accordance with an illustrative embodiment of the present invention.
- FIG. 4 shows a set of prefix trees for an improved n-bit prefix tree adder in accordance with an illustrative embodiment of the present invention.
- FIG. 5 is a diagram illustrating maximum accumulated stage delays for a 32-bit prefix tree adder of the type illustrated in FIG. 4 .
- FIG. 1 shows a set of superimposed prefix trees 10 for an n-bit prefix tree adder of the type described in the above-cited U.S. patent application Ser. No. 09/291,677.
- the general algorithm for an n-bit radix-2 prefix tree adder of this type is described below.
- Step 2 ( ⁇ log 2 n ⁇ stages):
- c j G j ⁇ 2 k ⁇ 1 +1 j +T j ⁇ 2 k ⁇ 1 +1 j c j ⁇ 2 k ⁇ 1 ⁇ j 2 k ⁇ 1 ⁇ 1 ⁇ j ⁇ 2 k ⁇ 1 ,
- c n ⁇ 1 G 0 n ⁇ 1 +T 0 n ⁇ 1 c ⁇ 1 .
- the squares at the top of the figure compute g j , t j and p j for each bit position in accordance with Step 1.
- the empty circles apply the fundamental carry operator in accordance with Step 2.
- the filled circles represent buffers.
- the crossed circles compute carries in accordance with Step 2 and Step 3 above.
- the diamonds at the bottom of the figure generate the sum at each bit position from the p j signal in accordance with the equation of Step 3. It should be noted that the sum computation of in Step 3 occurs in parallel with the computation of the final carry output c n ⁇ 1 in Step 3.
- the logic depth of an n-bit prefix tree adder configured as shown in FIG. 1 is 2+ ⁇ log 2 n ⁇ , and the fanout of the carry input c ⁇ 1 is 1+ ⁇ log 2 n ⁇ .
- the above-described algorithm can also be extended in a straightforward manner to higher radix prefix trees.
- This gate level model specifies that a 2-input NAND or NOR gate has a delay of ⁇ , while XOR/XNOR, AOI (and-or-invert), OAI (or-and-invert) and 2-to-1 multiplexer gates each have a delay of 1.5* ⁇ .
- the interconnect delay is modeled as ⁇ v for a minimum width routing along the vertical pitch of the corresponding circuit design, and as ⁇ h for a minimum width routing along the horizontal pitch of the design.
- the critical path delay for an n-bit adder design (with a total of ( ⁇ log 2 n ⁇ +2) logic stages) of the type illustrated in FIG. 1 is as follows:
- ⁇ s j 1.5* ⁇ + ⁇ c j ⁇ 1 + ⁇ h , ⁇ j 0 ⁇ j ⁇ n,
- ⁇ c n ⁇ 1 1.5* ⁇ + ⁇ G 0 n ⁇ 1 + ⁇ h .
- ⁇ t j is selected to be the worst delay from stage 1 since an OR/NOR gate is typically slower than an AND/NAND gate.
- FIG. 2 shows a graph of the maximum accumulated stage delays for group-generate (G), group-transmit (T), and intermediate carries (c) for a 32-bit prefix tree adder design of the type shown in FIG. 1, i.e., an adder design with c routing over n/2 bits. It can be seen from the graph that the group-generate, the group-transmit, and the intermediate carries are all generated with differing delays, and that this difference is maximum at the final stage of the parallel prefix tree of the adder.
- the present invention provides an improved prefix tree adder design which significantly reduces delay relative to the FIG. 1 adder design. More particularly, the invention in an illustrative embodiment exploits the above-described difference in the delays for computing the group-generate, group-transmit, and the intermediate carries in the final stage of the prefix tree, by combining the last two stages of the most-significant half of the adder into a single stage. As will be described in greater detail below, this may be done by altering the carry and sum generation equations in the adder algorithm so as to take advantage of the latency of the signals.
- FIG. 3 ( a ) shows the Boolean logic used in the last stage, i.e., the sum generation stage, of the prefix tree adder of FIG. 1 .
- FIGS. 3 ( b ) and 3 ( c ) show the Boolean logic of two cells which may be used in the most-significant half of the final stage of the adder in order to decrease the adder delay in accordance with the present invention. More specifically, FIG. 3 ( b ) shows the Boolean logic used in the last stage of an improved prefix tree adder in accordance with the invention for all values of j such that n>j ⁇ 3 ⁇ 4n, while FIG. 3 ( c ) shows the Boolean logic used in the last stage of the prefix tree adder for all values of j such that 3 ⁇ 4n>j ⁇ n/2.
- Step 2 ( ⁇ log 2 n ⁇ 1 stages)
- Step 3 (1 stage) for the final stage, calculate
- c n ⁇ 1 G 0 n ⁇ 1 +T 0 n ⁇ 1 c ⁇ 1 .
- a further improvement in computation speed is possible in accordance with the invention by rearranging the physical layout of the last stage of the adder so that the upper or most-significant half of the sum bits are generated in the same column as the lower or least-significant half of the sum bits. This reduces the routing delay on the intermediate carry signals that are on the critical path and therefore speeds up the sum computation.
- Such an arrangement may be implemented as a left-to-right routing of the most-significant group-generate and group-transmit signals, and may be referred to as a “folded” arrangement.
- This further improvement is particularly useful for adders having a large word length, i.e., a word length greater than or equal to 32, and for adder applications in which a regular layout is not required.
- FIG. 4 shows a set of superimposed prefix trees 40 for an n-bit prefix tree adder incorporating the above-described improvements.
- the empty circles apply the fundamental carry operator in accordance with Step 2.
- the filled circles represent buffers.
- the crossed circles compute carries in accordance with Step 2 and Step 3 of the general algorithm.
- the empty diamonds represent the Boolean logic of FIG. 3 ( b )
- the filled diamonds represent the Boolean logic of FIG. 3 ( c )
- the crossed rectangles represent logic that implements the sum computation equation in Step 3 for values of j such that n/2>j ⁇ 0.
- FIGS. 3 ( a ) and 3 ( b ) are shown by way of example only. Those skilled in the art will recognize that numerous alternative arrangements of logic circuitry may be used to exploit the differences in delay in the group-generate, group-transmit and intermediate carry signals in accordance with the techniques of the present invention.
- the improved prefix tree adder of FIG. 4 has a logic depth of 2+ ⁇ log 2 n ⁇ , and the fanout of the carry input c ⁇ 1 is 1+ ⁇ log 2 n ⁇ .
- the above-described general algorithm for the improved prefix tree adder can be extended in a straightforward manner to higher radix prefix trees.
- FIG. 5 shows a graph of the maximum accumulated stage delays for group-generate (G), group-transmit (T), and intermediate carries (c) for a 32-bit prefix tree adder design of the type shown in FIG. 4, i.e., an adder design with G and T routing over n/2 bits. It is apparent from the graph that the delay of the improved prefix tree adder is smaller than that of the adder of FIG. 1 .
- the adder architecture of the present invention thus reduces the gate delay of an n-bit prefix tree adder, as compared to existing architectures such as that illustrated in FIG. 1, while providing the same logic depth, fanout and wiring complexity.
- a fully-static 32-bit radix-2 prefix tree adder configured in accordance with the invention has a delay on the order of 0.7 nsec in a 0.16 ⁇ m static CMOS implementation.
- the wiring complexity is manageable in 0.16 ⁇ m technology using five layers of interconnect.
- static circuits were used in the above-described illustrative 32-bit implementations, it should be noted that the invention may be implemented using either static circuits, dynamic circuits or combinations of both static and dynamic circuits. Static circuits are often preferred to dynamic circuits because of their ease of design.
- Adders in accordance with the invention may be used as elements of many different types of circuits, such as, e.g., arithmetic logic units (ALUs), multiply-add units, and comparators.
- ALUs arithmetic logic units
- the invention can be incorporated in a wide variety of integrated circuits or other processing devices, including, e.g., microprocessors, digital signal processors (DSPs), microcontrollers, application-specific integrated circuits (ASICs), memory circuits, telecommunications hardware and other types of processing devices.
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Cited By (9)
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US20020103842A1 (en) * | 2000-12-08 | 2002-08-01 | Alexander Goldovsky | Adder with improved overflow flag generation |
US20040225706A1 (en) * | 2003-05-05 | 2004-11-11 | Harris David L. | Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks |
US8683398B1 (en) * | 2012-11-27 | 2014-03-25 | International Business Machines Corporation | Automated synthesis of high-performance two operand binary parallel prefix adder |
US8928675B1 (en) | 2014-02-13 | 2015-01-06 | Raycast Systems, Inc. | Computer hardware architecture and data structures for encoders to support incoherent ray traversal |
GB2523805A (en) * | 2014-03-06 | 2015-09-09 | Advanced Risc Mach Ltd | Data processing apparatus and method for performing vector scan operation |
US20160283196A1 (en) * | 2015-03-26 | 2016-09-29 | Altera Corporation | Combined adder and pre-adder for high-radix multiplier circuit |
US10073677B2 (en) | 2015-06-16 | 2018-09-11 | Microsoft Technology Licensing, Llc | Mixed-radix carry-lookahead adder architecture |
US11301213B2 (en) * | 2019-06-24 | 2022-04-12 | Intel Corporation | Reduced latency multiplier circuitry for very large numbers |
US11334318B2 (en) * | 2018-07-12 | 2022-05-17 | Intel Corporation | Prefix network-directed addition |
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US20020103842A1 (en) * | 2000-12-08 | 2002-08-01 | Alexander Goldovsky | Adder with improved overflow flag generation |
US6912560B2 (en) * | 2000-12-08 | 2005-06-28 | Agere Systems, Inc. | Adder with improved overflow flag generation |
US20040225706A1 (en) * | 2003-05-05 | 2004-11-11 | Harris David L. | Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks |
US7152089B2 (en) * | 2003-05-05 | 2006-12-19 | Sun Microsystems, Inc. | Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks |
US8683398B1 (en) * | 2012-11-27 | 2014-03-25 | International Business Machines Corporation | Automated synthesis of high-performance two operand binary parallel prefix adder |
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