CN105814687A - 半导体封装及其安装结构 - Google Patents

半导体封装及其安装结构 Download PDF

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Publication number
CN105814687A
CN105814687A CN201580002992.4A CN201580002992A CN105814687A CN 105814687 A CN105814687 A CN 105814687A CN 201580002992 A CN201580002992 A CN 201580002992A CN 105814687 A CN105814687 A CN 105814687A
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China
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chip part
intermediary layer
semiconductor packages
pad
layer
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CN201580002992.4A
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CN105814687B (zh
Inventor
手岛祐郎
手岛祐一郎
中矶俊幸
竹岛裕
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

本发明涉及半导体封装及其安装结构。具备中介层(1)、搭载于中介层(1)的第一面的半导体元件(2)、形成于中介层(1)的第二面的凸块(3)、以及搭载于中介层(1)的第二面的芯片部件(10)。中介层(1)是硅中介层，半导体元件(2)被倒装芯片安装于中介层(1)的第一面，芯片部件(10)是在硅基板上通过薄膜工艺形成元件，并在单一面形成焊盘的薄膜无源元件，芯片部件(10)的焊盘经由导电性接合材料而与形成于中介层(1)的第二面的焊环连接。根据该结构，小型化的同时确保半导体封装的中介层(1)与芯片部件(10)之间的接合可靠性。

Description

半导体封装及其安装结构
技术领域
本发明是涉及在内部具备半导体元件并且在底面形成安装用的凸块的、半导体封装及其安装结构的发明。
背景技术
在如数字电路这样的基于时钟信号来进行动作的半导体器件、如高频电路这样的对高频信号进行处理的半导体器件中，在这些半导体器件被安装在印刷电路板的状态下，存在起因于电流变动的噪声与电源线叠加，对半导体器件带来不良影响的情况。为了除去该噪声，在半导体器件的电力供给端子的附近设置旁路电容器(去耦电容器)。
另一方面，在表面安装于印刷电路板的、被封装化的半导体器件(以下，“半导体封装”)之一中存在具备中介层的BGA(BallGridArray：球栅阵列)型的半导体封装。
图13是表示上述半导体封装以及上述旁路电容器的以往的安装结构的几个例子的剖视图。在图13中(1)(2)(3)所示的任何的例子中，都是在中介层1的上面安装半导体元件2，利用密封树脂4对半导体元件2进行树脂密封，在中介层的下面形成凸块3。在(1)所示的例子中，半导体元件2与中介层1的上面引线接合，在印刷电路板6安装有旁路电容器5，并在其上部安装有半导体封装。在(2)所示的例子中，半导体元件2在中介层1的上面被倒装芯片安装。在(3)所示的例子中，在中介层1的下面安装有旁路电容器5。即在半导体封装侧安装有旁路电容器5。
在BGA型半导体封装的下面安装有旁路电容器的例子被专利文献1示出。
专利文献1：日本特开2005－150283号公报
在图13所示的以往的半导体封装的安装结构中，在(1)(2)的半导体封装的安装结构中，由于从半导体元件2到旁路电容器5的距离较长，所以等效串联电感(ESL)较大。在(3)的半导体封装的安装结构中，由于从半导体元件2到旁路电容器5的电流路径长较短，所以ESL较小，噪声减少效果较高。
然而，在专利文献1所公开的BGA型半导体封装中存在如下那样的应解决的课题。
(a)专利文献1所公开的BGA型半导体封装具备的中介层通常是玻璃环氧树脂基板。另外，旁路电容器是具有在两端的5面上分别形成电极的所谓狗骨型的端子结构的层叠型陶瓷电容器(MLCC)。由于玻璃环氧树脂基板和MLCC的线膨胀系数较大地偏离，所以根据热历程，有可能在接合部产生裂缝。
(b)MLCC的坯体是陶瓷，MLCC硬且脆。因此，在弯曲BGA型半导体封装时，应力集中在接合部，在接合部容易产生裂缝。
(c)由于MLCC具有狗骨型的端子结构，所以难以使与邻接的焊球的间隙变小。在作为BGA型半导体封装的安装目标的印刷电路板的布线与MLCC之间有短路的风险。另外，在印刷电路板的布线与MLCC之间所产生的寄生电容容易变大。换句话说，不容易适应高密度地配置有焊球的封装。
如此，不容易确保芯片电容器与半导体封装的中介层之间的接合可靠性，并且不能成为小型、高密度、电特性优异的。
发明内容
本发明的目的在于提供一种确保半导体封装的中介层与芯片部件之间的接合可靠性，并且小型、高密度、电气特性出色的半导体封装以及其安装结构。
(1)本发明的半导体封装的特征在于具备中介层、搭载于上述中介层的第一面的半导体元件、形成于上述中介层的第二面的凸块、以及搭载于上述中介层的上述第二面的芯片部件，上述中介层是硅中介层，上述半导体元件被安装于上述中介层的第一面，上述芯片部件是在硅基板上通过薄膜工艺形成元件，并在单一面形成焊盘的薄膜元件，上述芯片部件的上述焊盘经由导电性接合材料与形成在上述中介层的第二面上的焊环连接。
根据上述构成，能够确保中介层与芯片部件之间的接合可靠性，并且构成小型、高密度、电特性出色的半导体封装。
(2)在上述(1)中，
优选，上述半导体元件是处理器单元，上述芯片部件是旁路电容器(去耦电容器)，上述中介层具备使上述半导体元件与上述芯片部件导通的通孔。根据该构成，由于从半导体元件到旁路电容器的电流路径长较短，所以ESL较小，噪声减少效果较高。另外，相应地，在电容器单体中的ESL可以并不那么小。
(3)在上述(1)或者(2)中，
优选，上述凸块排列成格子状，上述芯片部件被配置在上述凸块的排列范围内的一部分(除去上述凸块的一部分这样的区域)。根据该构成，不需打乱半导体封装的凸块的格子状排列、以及不需打乱作为安装目标的印刷电路板的焊盘的格子状排列，就能够配置芯片部件。尤其，由于芯片部件具有在单一面形成焊盘的端子结构，所以在芯片部件的侧面没有电极，另外，由于是通过薄膜工艺所形成的部件，所以芯片部件的外形尺寸不需低于中介层的凸块的排列尺寸精度，就能够减少凸块的取掉个数(除去格子状排列的凸块的一部分的配置图案的、该除去的凸块的数量)。
(4)在上述(1)～(3)中的任意一项中，
优选上述芯片部件在上述焊盘的形成面具有树脂层。由此，由于芯片部件的焊盘形成面的缓冲性、弹性较高，所以即使半导体封装弯曲，也能够抑制施加给芯片部件的接合部的应力。
(5)在上述(4)中，
优选上述半导体元件在上述中介层上被树脂密封。根据该构成，半导体元件的保护结构能够容易地实现。尤其，由于构成中介层的硅基板与密封树脂的线膨胀率一般差异较大，所以虽然半导体封装容易弯曲，但是由于芯片部件的焊盘形成面的缓冲性、弹性较高，所以芯片部件的接合部的稳定性被保持。
(6)在上述(1)～(5)中的任意一项中，，
优选上述芯片部件在俯视时具有四边形的外形，并被搭载在上述四边形的4边相对于上述凸块的排列方向形成倾斜的朝向上。由此，不需较大地减少形成于中介层的凸块的数量，就能够构成带芯片部件的半导体封装。
(7)在上述(1)～(6)中的任意一项中，
优选上述芯片部件的上述焊盘在俯视时是矩形，并被形成在上述矩形的各边沿着上述凸块的排列方向的朝向上。由此，容易确保中介层的多个焊环的中的、连接芯片部件的焊盘的焊环与设有置凸块的焊环的间隔，并且容易确保连接芯片部件的焊盘的焊环的面积。
(8)在上述(1)～(7)中的任意一项中，
优选上述芯片部件的上述焊盘在俯视时被配置在上述芯片部件的上述外形的角部。由此，即使芯片部件的外形尺寸较小，也能够确保焊盘间的距离，并且向中介层的搭载也容易。
(9)本发明的半导体封装的安装结构的特征在于，包括印刷电路板和安装于上述印刷电路板的半导体封装，
上述半导体封装具备中介层、搭载于上述中介层的第一面的半导体元件、形成于上述中介层的第二面的凸块、以及搭载于上述中介层的上述第二面的芯片部件，上述中介层是硅中介层，上述半导体元件被安装于上述中介层的第一面，上述芯片部件是在硅基板上通过薄膜工艺形成元件，并在单一面形成焊盘的薄膜有源元件，上述芯片部件的上述焊盘经由导电性接合材料与形成于上述中介层的第二面的焊环连接，在上述芯片部件与上述印刷电路板之间具备安装于上述印刷电路板的表面安装部件。
根据上述构成，能够确保中介层与芯片部件之间的接合可靠性，并且构成小型、高密度、电特性出色的电路。
根据本发明，确保半导体封装的中介层与芯片部件之间的接合可靠性，并获得小型、高密度、电气特性出色的半导体封装以及半导体封装的安装结构。
附图说明
图1是表示第一实施方式所涉及的半导体封装101以及其安装结构201的剖视图。
图2是表示针对中介层1的芯片部件10的搭载部的结构示剖视图。
图3是中介层1的第二面的俯视图。
图4是芯片部件10的焊盘形成面侧的外观立体图。
图5是芯片部件10的焊盘形成面侧的俯视图。
图6是图5所示的A－A部分的剖视图。
图7是表示第二实施方式所涉及的半导体封装的安装结构202的剖视图。
图8是第二实施方式所涉及的半导体封装的安装结构的主要部分的剖视图。
图9(A)、(B)是表示第三实施方式所涉及的半导体封装的安装结构的图。
图10(A)、(B)、(C)是表示第三实施方式所涉及的半导体封装具备的芯片部件的构成的图。
图11(A)、(B)是表示第四实施方式所涉及的半导体封装的安装结构的图。
图12(A)、(B)是表示比较例所涉及的半导体封装的安装结构的图。
图13是表示半导体封装以及旁路电容器的以往的安装结构的几个例子的剖视图。
具体实施方式
《第一实施方式》
图1是表示第一实施方式所涉及的半导体封装101以及其安装结构201的剖视图。
半导体封装101具备中介层1、搭载于中介层1的第一面(按照图1所示的朝向为上面)的半导体元件2、形成于中介层1的第二面的凸块3、和搭载于中介层1的第二面的芯片部件10。
中介层1是硅制的中介层。例如由Si单晶体或者Si玻璃构成。在该中介层1的第一面形成用于安装半导体元件2的焊环。
半导体元件2是从晶片切分出的裸片。该半导体元件2在中介层1的第一面例如被进行倒装芯片安装。另外，半导体元件2被覆盖中介层1的第一面的密封树脂4密封。密封树脂4例如是环氧树脂。
在中介层1的第二面形成用于设置焊球的多个焊环，通过焊球借助焊球植球机被安装于这些焊环，从而形成凸块3。另外，在中介层1的第二面形成用于搭载芯片部件10的焊环，在这些焊环搭载有芯片部件10。
半导体封装101通过该凸块3与印刷电路板6上的焊环7接合而被安装。
图2是表示针对中介层1的芯片部件10的搭载部的结构的剖视图。芯片部件10是可表面安装地构成的薄膜无源元件。在本实施方式中是薄膜电容器，作为旁路电容器(去耦电容器)被使用。对芯片部件10而言，利用薄膜工艺在硅基板上形成电容器，并在单一面(安装面)的外径尺寸内形成焊盘43、44。芯片部件10的焊盘43、44经由焊料等导电性接合材料9与形成于中介层1的第二面的焊环53、54连接。
图1所表示的半导体元件2例如是CPU(CentralProcessingUnit：中央处理单元)、APU(ApplicationProcessingUnit：应用处理单元)等处理单元。中介层1具备使半导体元件2与芯片部件10直接导通的通孔8。换句话说，在本实施方式中，半导体元件两侧的端子和芯片部件10侧的端子不经由引绕用的面内图案地连接。该通孔8通过例如利用反应离子蚀刻(RIE)(尤其是深层RIE)来形成通孔并在其内面进行Cu溅射以及镀Cu从而形成。
在由焊料构成上述导电性接合材料9的情况下，形成于中介层1的第二面的焊环53、54等是在Ti/Cu/Ti的布线层的表面依次设置镀Ni膜、镀Au膜的构成，在中介层1的焊环53、54或者芯片部件10的焊盘43、44搭载焊球，并通过回流焊工序进行焊接。另外，在由Au凸块构成导电性接合材料9的情况下，形成于中介层1的第二面的焊环53、54等也是在Ti/Cu/Ti的布线层的表面依次设置镀Ni膜、镀Au膜的构成(其中，镀Au膜比上述的镀膜厚)，通过超声波接合法将芯片部件10与中介层1进行Au-Au接合。芯片部件10也可以不经由焊环53等直接与通孔8的端面连接。
根据上述构成，由于从半导体元件2到芯片部件(旁路电容器)10的电流路径长较短，所以ESL较小、噪声减少效果较高。另外，可以是比较低电容的电容器，电容器单体中的ESL可以并不那么小。
通过具备上述芯片部件10，与使用具有狗骨型的端子结构的MLCC的情况相比，能够减小与邻接的凸块(焊球)3的间隙，所以适合高密度地配置凸块(焊球)的封装。另外，由于芯片部件10的焊盘43、44仅形成在与中介层1对置的面，所以在作为半导体封装101的安装目标的印刷电路板6的布线与芯片部件10之间没有短路的风险。另外，与MLCC相比，由于芯片部件10的坯体为硅基板，所以坯体的介电常数较低(相对介电常数10～11左右)，印刷电路板6的布线与芯片部件10之间所产生的寄生电容较小。
图3是中介层1的第二面的俯视图。在中介层1的第二面呈格子状地排列形成凸块3。另外，在中介层1的第二面，在凸块3的排列范围内的一部分(除去凸块3的一部分这样的区域)配置芯片部件搭载用的焊环53、54。芯片部件10的焊盘43、44经由导电性接合材料9与该焊环53、54连接。根据该构成，不会打乱半导体封装101的(中介层1的)凸块的格子状排列、以及不会打乱作为安装目标的印刷电路板的焊盘的格子状排列，就能够配置芯片部件10。而且半导体封装101能够作为通常的BGA型的半导体封装进行处理。
接下来，参照图4～6对上述芯片部件10的构成进行说明。
图4是芯片部件10的焊盘形成面侧的外观立体图。芯片部件10在单一面(按照图4所示的朝向是上面)形成输入输出用的焊盘43、44。换句话说，该芯片部件是具有LGA型的端子电极的表面安装部件。
图5是芯片部件10的焊盘形成面侧的俯视图。图6是图5所示的A－A部分的剖视图。
芯片部件10是薄膜电容器元件，并具备基板11、紧贴层13、电容部20、和保护层30。
作为基板11的材质，例如列举Si单晶体基板。优选在基板11的表面形成氧化物层12。氧化物层12以防止基板11与紧贴层13的相互扩散为目的而设置。氧化物层12例如通过对基板11进行热处理来形成。
紧贴层13形成在基板11的一个主面之上。紧贴层13确保基板11的氧化物层12与下部电极层21的紧贴性。
电容部20具有下部电极层21、电介质层22、和上部电极层23。下部电极层21形成在紧贴层13上。电介质层22形成在下部电极层21上。另外，上部电极层23形成在电介质层22上。
下部电极层21以及上部电极层23使用具有导电性的金属材料。具体而言，优选导电性良好、耐氧化性出色的高熔点的贵金属(例如Au、Pt)。
电介质层22采用电介质材料。作为电介质材料的例子，列举(Ba，Sr)TiO3、SrTiO3、BaTiO3、Pb(Zr，Ti)O3、SrBi4Ti4O15等铋层状化合物。
另外，在上部电极层23上设置有无机绝缘层24。无机绝缘层24是为了提高上部电极层23与保护层30的紧贴性而设置的。
保护层30以包覆电容部20和无机绝缘层24的方式形成。保护层30是为了防止水分浸入电容部20而形成的。保护层30具有无机保护层31和有机保护层33。作为无机保护层31的材质的例子，列举SiNx、SiO2、Al2O3、TiO2。另外，作为有机保护层33的材质的例子，列举聚酰亚胺树脂、环氧树脂。
在本实施方式中，紧贴层13的端部从无机保护层31露出。即，由于在无机保护层31与基板11之间夹设紧贴层13，所以紧贴层13防止无机保护层31与基板11的剥离。
焊盘43经由引出电极41与下部电极层21电连接。引出电极41贯通电介质层22、无机保护层31以及有机保护层33而形成。引出电极41向有机保护层33的上部延伸。另外，焊盘44经由引出电极42与上部电极层23电连接。引出电极42贯通无机绝缘层24、无机保护层31以及有机保护层33而形成。另外，引出电极42向有机保护层33的上部延伸。
焊盘43、44例如以下层Ni和上层Au的二层结构构成。另外，引出电极41、42例如以下层Ti和上层Cu的二层结构构成。
在本实施方式中，金属膜45形成于保护层30的端部的至少一部分。优选金属膜45与紧贴层13接触。即，紧贴层13延伸到与金属膜45接触的位置。利用该金属膜45的存在，防止水分浸入保护层30与基板11之间的缺陷。
另外，优选金属膜45以包覆无机保护层31与有机保护层33的界面的外周部的方式形成。由此，防止水分从外周部浸入无机保护层31与有机保护层33界面。
金属膜45例如以下层Ti和上层Cu的二层结构构成。
有机绝缘层34以包覆无机保护层31以及有机保护层33、引出电极41、42、和金属膜45的方式形成。而且，焊盘43、44以露出芯片部件10的表面的方式形成。有机绝缘层34的材质例如是聚酰亚胺树脂、环氧树脂。
如此，在芯片部件10的焊盘43、44的形成面具有作为树脂层的有机绝缘层34。由此，由于芯片部件10的焊盘43、44的形成面的缓冲性、弹性较高，所以即使半导体封装弯曲，也能够抑制施加给芯片部件的接合部的应力。尤其，在半导体元件2利用将中介层1的第一面覆盖的密封树脂4被密封的情况下，构成中介层1的硅基板和作为密封树脂的环氧树脂的线膨胀率一般差异较大，所以半导体封装101容易弯曲。然而，由于芯片部件10的焊盘形成面的缓冲性、弹性较高，所以确保芯片部件10的接合部的稳定性。
在本实施方式中，由于利用薄膜工艺形成芯片部件10，所以能够使芯片部件10矮化，适合将芯片部件配置于中介层1与印刷电路板6之间的微小的空间中。换句话说，能够使芯片部件10的安装后的高度(例如30～90μm)在凸块3的高度尺寸(例如100μm)以下。
另外，由于芯片部件10与中介层1同样地使用硅基板，所以两者的线膨胀系数实际一致，因此，对于热循环，芯片部件10和中介层1的膨胀、收缩举动一致，所以安装可靠性较高。
而且，由于芯片部件10具有在单一面形成焊盘的端子结构，所以在芯片部件10的侧面没有电极，另外，由于是通过薄膜工艺所形成的部件，所以芯片部件10的外形尺寸不必低于中介层1的凸块的排列尺寸精度，就能够减少凸块的取掉个数(除去格子状排列的凸块的一部分后的配置图案的、其除去的凸块的数)。
《第二实施方式》
图7是表示第二实施方式所涉及的半导体封装的安装结构202的剖视图。图8是第二实施方式所涉及的半导体封装的安装结构的主要部分的剖视图。图8所示的部分是与第一实施方式所示的图2对应的部分。
与第一实施方式所示的半导体封装的安装结构不同，第二实施方式的半导体封装的安装结构在芯片部件10与印刷电路板6之间，且在印刷电路板6安装有表面安装部件60。
该表面安装部件60如图8所示那样，是具有狗骨型的端子结构的层叠型陶瓷电容器(MLCC)。该表面安装部件60也作为旁路电容器被使用。虽然该表面安装部件60与芯片部件10相比，ESL较大，但却是高电容的电容器。另外，由于半导体元件2与表面安装部件60之间的路径长比较长，所包括该路径的ESL较大。然而，由于表面安装部件60是比较高电容的电容器，所以表面安装部件60作为有效地抑制低频率的噪声的旁路电容器进行作用。另一方面，即使芯片部件10是比较低电容的电容器，由于ESL较小，所以也作为有效地抑制高频率的噪声的旁路电容器进行作用。作为该表面安装部件，与芯片部件10同样地也可以利用薄膜电容器元件。
对芯片部件10而言，由于其印刷电路板6侧的表面为绝缘体，所以即使该芯片部件10与表面安装部件60的间隙非常窄，在电气方面也不存在问题。另外，即使以不损坏芯片部件10以及表面安装部件60的程度抵接也不会短路。
《第三实施方式》
在第三实施方式中，特别对芯片部件的构成以及该芯片部件向中介层的搭载结构进行表示。
图9(A)是本实施方式所涉及的半导体封装103的中介层1的第二面的俯视图。图9(B)是图9(A)中的A－A部分的剖视图。
在中介层1的第二面呈格子状地排列形成凸块3。另外，在中介层1的第二面，在凸块3的排列范围内的一部分(除去凸块3的一部分这样的区域)配置芯片部件10搭载用的焊环53、54。芯片部件10的焊盘43、44经由导电性接合材料9与该焊环53、54连接。
芯片部件10在俯视时具有四边形的外形，并被在该四边形的4边相对于凸块3的排列方向形成倾斜的朝向上。其它的构成如第一实施方式所示。
图10(A)是芯片部件10的立体图，图10(B)是芯片部件10的俯视图。另外，图10(C)是切开芯片部件10前的晶片的俯视图。
芯片部件10是从硅基板(晶片)切出的部件。即，在硅基板10W，通过薄膜工艺形成薄膜电容器等多个芯片部件用的电路，最终通过切割而分离成多个芯片部件10。
芯片部件10在俯视时具有四边形的外形，芯片部件10的焊盘43、44在俯视时被配置在外形的角部。
在图9中沿纵横引出的多个虚线表示中介层的凸块3的排列方向。如图9所示，芯片部件10在俯视时具有四边形的外形，并且被搭载在该四边形的4边相对于凸块3的排列方向形成倾斜的朝向上。另外，芯片部件10的焊盘43、44在俯视时被配置在外形的角部。并且，芯片部件10的焊盘43、44在俯视时为矩形，并被形成在该矩形的各边沿着凸块3的排列方向的朝向上。
此外，芯片部件10并不限于薄膜电容器等无源元件，即使晶体管等有源元件、包括它们的集成电路也同样地能够应用。
根据本实施方式，不打乱半导体封装103的(中介层1的)凸块的格子状排列、以及不打乱作为安装目标的印刷电路板的焊盘的格子状排列，就能够配置芯片部件10。而且半导体封装103能够作为通常的BGA型的半导体封装进行处理。尤其，因为芯片部件10在俯视时具有四边形的外形，并被搭载在该四边形的4边相对于凸块3的排列方向形成倾斜的朝向上，所以不需较大地减少排列在中介层1的凸块的数量，就能够构成带芯片部件的半导体封装。
此处，在图12(A)、(B)中表示比较例所涉及的半导体封装的安装结构。图12(A)是中介层1的第二面的俯视图。图12(B)是图12(A)中的A－A部分的剖视图。
在该比较例中，搭载有芯片部件90，该芯片部件90具有在两端的5个面分别形成电极的、所谓狗骨型的端子结构。芯片部件的平面积与图9所示的芯片部件10的平面积相同。在图12(A)、(B)所示的比较例中，需要除去6个凸块，并在该区域形成芯片部件的搭载用的焊环等。
与此相对，在图9(A)、(B)所示的本实施方式的半导体封装103中，可以只设置除去中介层10的5个凸块这样的区域。由此，不需较大地减少形成于中介层的凸块的数量，就能够构成带芯片部件的半导体封装。
另外，在本实施方式中，芯片部件10的焊盘43、44在俯视时是矩形，并在该矩形的各边沿着凸块3的排列方向的朝向上形成。由此，容易确保中介层1的多个焊环中的、连接芯片部件10的焊盘43、44的焊环53、54与设置有凸块的焊环的间隔，并且容易确保与芯片部件10的焊盘43、44连接的焊环53、54的面积。
另外，在本实施方式中，芯片部件10的焊盘43、44在俯视时被配置在外形的角部。由此，即使芯片部件10的外形尺寸较小，也能够确保焊盘43－44间的距离，并且向中介层1的搭载也容易。
此外，优选，在芯片部件10的焊盘是2个的情况下，如图9(A)、(B)所示那样，分别配置于对置的角部。然而，芯片部件10的焊盘也可以是3个以上。
《第四实施方式》
图11(A)、(B)是表示第四实施方式所涉及的半导体封装104的安装结构的图。芯片部件10的形状与第三实施方式不同。在本实施方式中，芯片部件10的平面形状是菱形。对芯片部件而言，若考虑从半导体基板切出时的面积效率，则基本上优选是四边形，但并不限于是矩形。如本实施方式那样，芯片部件的平面形状也可以是菱形、平行四边形。在本发明中，芯片部件是薄膜元件，尤其在通过从晶片切出薄膜元件的方法形成薄膜元件的情况下，能够形成为各种形状而并不限于矩形。因此，能够考虑到搭载的中介层的焊盘配置等来选择适当的形状。
此外，在图1、图7中，虽然示出了在中介层1搭载一个半导体元件2的例子，但也可以在中介层1上搭载多个半导体元件。
另外，在以上所示的实施方式中，虽然芯片部件10是薄膜电容器，但如果是在硅基板上通过薄膜工艺形成元件并在单一面形成焊盘的薄膜无源元件则能够同样应用。例如即使是薄膜电感器、薄膜阻抗元件也能够同样地应用。
最后，上述的实施方式的说明是在全部的点上进行例示的说明，并不是限制的说明。对本领域普通技术人员来说能够适当地进行变形以及变更是清楚的。本发明的范围并不是上述的实施方式，而通过权利要求示出。并且，在本发明的范围中意在包括与权利要求均等的意思以及范围内的全部的变更。
附图标记说明
1…中介层；2…半导体元件；3…凸块；4…密封树脂；5…旁路电容器；6…印刷电路板；7…焊环；8…通孔；9…导电性接合材料；10…芯片部件；11…基板；12…氧化物层；13…紧贴层；20…电容部；21…下部电极层；22…电介质层；23…上部电极层；24…无机绝缘层30…保护层；31…无机保护层；33…有机保护层；34…有机绝缘层；41、42…引出电极；43、44…焊盘；45…金属膜；53、54…焊环；60…表面安装部件；101、103、104…半导体封装；201、202…半导体封装的安装结构。

Claims (9)

1.一种半导体封装，其特征在于，
具备中介层、搭载于所述中介层的第一面的半导体元件、形成于所述中介层的第二面的凸块、以及搭载于所述中介层的所述第二面的芯片部件，
所述中介层是硅中介层，
所述半导体元件被安装于所述中介层的第一面，
所述芯片部件是在硅基板上通过薄膜工艺形成元件，并在单一面形成焊盘的薄膜元件，
所述芯片部件的所述焊盘经由导电性接合材料而与形成于所述中介层的第二面的焊环连接。
2.根据权利要求1所述的半导体封装，其中，
所述半导体元件是处理器单元，
所述芯片部件是旁路电容器，
所述中介层具备使所述半导体元件与所述芯片部件导通的通孔。
3.根据权利要求1或者2所述的半导体封装，其中，
所述凸块被排列成格子状，
所述芯片部件被配置在所述凸块的排列范围内的一部分。
4.根据权利要求1～3中的任意一项所述的半导体封装，其中，
所述芯片部件在所述焊盘的形成面具有树脂层。
5.根据权利要求4所述的半导体封装，其中，
所述半导体元件在所述中介层上被树脂密封。
6.根据权利要求1～5中的任意一项所述的半导体封装，其中，
所述芯片部件在俯视时具有四边形的外形，并被搭载在所述四边形的4边相对于所述凸块的排列方向形成倾斜的朝向上。
7.根据权利要求1～6中的任意一项所述的半导体封装，其中，
所述芯片部件的所述焊盘在俯视时是矩形，并被形成在所述矩形的各边沿着所述凸块的排列方向的朝向上。
8.根据权利要求1～7中的任意一项所述的半导体封装，其中，
所述芯片部件的所述焊盘在俯视时被配置在所述芯片部件的所述外形的角部。
9.一种半导体封装的安装结构，是包括印刷电路板和安装于所述印刷电路板的半导体封装的半导体封装的安装结构，其特征在于，
所述半导体封装具备中介层、搭载于所述中介层的第一面的半导体元件、形成于所述中介层的第二面的凸块、以及搭载于所述中介层的所述第二面的芯片部件，
所述中介层是硅中介层，
所述半导体元件被安装于所述中介层的第一面，
所述芯片部件是在硅基板上通过薄膜工艺形成元件，并在单一面上形成焊盘的薄膜元件，
所述芯片部件的所述焊盘经由导电性接合材料而与形成于所述中介层的第二面的焊环连接，
在所述芯片部件与所述印刷电路板之间具备安装于所述印刷电路板的表面安装部件。
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