CN105723518A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN105723518A
CN105723518A CN201480061640.1A CN201480061640A CN105723518A CN 105723518 A CN105723518 A CN 105723518A CN 201480061640 A CN201480061640 A CN 201480061640A CN 105723518 A CN105723518 A CN 105723518A
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drain
region
conductivity type
semiconductor device
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CN105723518B (zh
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和田真一郎
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Abstract

提供在栅极宽度方向上器件的端部和中央部上的通态电阻或漏极电流密度均匀的高耐压横向半导体器件。在形成于SOI衬底上的横向N型MOS晶体管(11)的端部形成有由绝缘膜填充的沟槽隔离(10b)。隔着沟槽隔离(10b)与晶体管的P型体区(1)相邻地设置有二极管12的阳极区(6)，并且，隔着沟槽隔离(10b)与晶体管的N型漏极漂移区(4)相邻地设置有二极管(12)的阴极区(15)，使得在对晶体管施加电压时施加到沟槽隔离(10b)的电场为0。

Description

半导体器件
技术领域
本发明涉及半导体器件，涉及形成在半导体衬底上的横向半导体器件。
背景技术
在高耐压的横向晶体管中，为了提高晶体管的通态击穿电压，相比以前在俯视形状的器件端部做了布局上的调整。在此举两个例子，下面基于图7和图8的俯视布局图进行说明。
如图7所示，第一以往例中，在横向NMOS晶体管中，N+漏极区5、N型漏极漂移区4被P型体区1包围。并且，与P型体区1的端部重叠地形成有栅极电极3。进一步，在俯视形状为半圆状的P型体区1的端部，具有栅极电极3与N+源极区2不邻接的部位。在该结构中，由于器件端部没有源极区2，因此能够减小漏极区5的端部上的电流密度，能够解决端部上漏极电流密度增大、通态击穿电压因柯克效应(Kirkeffect)而降低的问题。
此外，如图8所示，第二以往例中，在横向NMOS晶体管中，N+源极区2、P型体区1被N+漏极区5和N型漏极漂移区4包围。此外，与P型体区1的端部重叠地形成有栅极电极3。进一步地，在俯视形状为半圆状的P型体区1的端部，具有栅极电极3与N+源极区2不邻接的部位。与以往例1相比，该结构由于将N+漏极区设置得比N+源极区更靠外周，因此漏极漂移区的曲率半径变大，能够进一步地减小端部上的漏极电流密度。因此，与第一以往例相比，可进一步地期待通态击穿电压的提高。
现有技术文献
专利文献
专利文献1：日本专利特许3473460号公报
专利文献2：日本特开2007-96143号公报
发明内容
发明要解决的技术问题
然而，以往例的晶体管中，虽然能够提高通态击穿电压，但存在以下问题。
第一，晶体管端部的通态电阻或漏极电流特性与中央部的通态电阻或漏极电流特性不同。以往例的结构中，虽然每种情况下在端部都没有N+源极区2，但在端部还形成有N+漏极区5、N型漏极区4。因此，在端部由N型漏极漂移区和N+漏极区的扩散电阻决定的漏极电阻与中央部的漏极电阻相比较小。其结果是，通态电阻Ron的倒数或漏极电流Ids相对于栅极宽度Wg不成线性，而是具有偏移量ΔWg，由以下式子表示。
1 R o n ∝ I d s ∝ W g + ΔW g
因此，栅极宽度Wg小的晶体管中，偏移量ΔWg所占比例变大。因此，例如在将晶体管用于电流检测(传感)电路中的情况下，由于具有该偏移量，传感比(senseratio)偏离晶体管的栅极宽度Wg之比。此外，由于偏移量的影响，无法实现通态电阻大、漏极电流小的晶体管，难以构成传感比大的电流检测电路。
第二，端部的通态电阻因温度变化导致的变化量与中央部的变化量不同。高耐压横向MOS晶体管的通态电阻主要由沟道电阻RCH、漏极漂移电阻RDRIFT之和给出，由以下的式子给出。
Ron(Tj)＝RCH(Tj)+RDRIFT(Tj)
在此，沟道电阻RCH、漏极漂移电阻RDRIFT虽然都具有温度Tj依赖性，但其温度系数相互不同。如上所述，器件端部的漏极漂移电阻RDRIFT比中央部小，因此，通态电阻中漏极漂移电阻RDRIFT所占的比例随栅极宽度Wg而变化。其结果是，产生通态电阻的温度依赖性因晶体管的栅极宽度Wg而不同的问题。
另一方面，在将该晶体管用于电流检测(传感)电路的情况下，传感比由传感电路与主电路的电流量比即通态电阻的反比给出，由以下的式子给出。
S e n s e R a t i o ( T j ) = Ids M a i n ( T j ) Ids S e n c e ( T j ) = Ron S e n c e ( T j ) Ron M a i n ( T j )
因此，将栅极宽度不同的晶体管用于传感电路和主电路的情况下，由于晶体管各自的通态电阻或者漏极电流的温度系数不同，因此产生传感比因温度而变化的问题。
本发明提供可改善上述两个问题的高耐压的横向MOS晶体管结构的横向半导体器件。
解决技术问题的技术方案
本发明的目的在于在高耐压的横向器件中使器件端部的通态电阻特性或漏极电流特性与器件中央部相等。由此，能够使器件的电流特性相对于器件的宽度成线性，能够改善上述的问题。
本发明的横向MOS晶体管包括：形成在半导体衬底层上的第一导电型的体区；与上述体区邻接或者隔开间隔地将上述体区完全包围的第二导电型的漏极漂移区；与上述漏极漂移区接触的第二导电型的漏极区；形成在上述体区内的第二导电型的源极区；从上述源极区的端部覆盖至上述漏极漂移区上的绝缘膜；隔着上述绝缘膜从上述源极区的端部上覆盖至上述漏极漂移区上的栅极电极；和与体区和漏极漂移区的端部邻接的由绝缘膜构成的上述沟槽隔离，并且，上述横向半导体器件具有二极管，该二极管包括：与上述沟槽隔离邻接的第一导电型的阳极区；与上述沟槽隔离邻接的第二导电型的阴极区；从上述阳极区的端部覆盖至上述阴极区上的绝缘膜；和隔着所述绝缘膜从上述阳极区上覆盖至上述阴极区上的二极管场板电极。此外，上述二极管的阳极区和阴极区分别与上述体区和漏极区具有相同的杂质分布，并且，至少在与上述沟槽隔离接触的部分，连接上述阳极区的扩散区与连接上述阴极区的扩散区的距离和上述源极区与上述漏极区的距离相等。此外，上述阳极区通过布线层与上述体区电连接为同电位，上述阴极区通过布线层与上述漏极区电连接，上述栅极电极与上述二极管场板电极电连接。
此外，本发明的另一种横向MOS晶体管为一种形成在半导体衬底上的横向半导体器件，包括：形成在上述半导体衬底层上的第一导电型的体区；与上述体区邻接或者隔开间隔地将上述体区完全包围的第二导电型的漏极漂移区；与上述漏极漂移区接触的第二导电型的漏极区；形成在上述体区内的第二导电型的源极区；从上述源极区的端部覆盖至上述漏极漂移区上的绝缘膜；隔着上述绝缘膜从上述源极区的端部上覆盖至上述漏极漂移区上的栅极电极；和与体区和漏极漂移区的端部邻接的由绝缘膜构成的上述沟槽隔离，并且，上述横向半导体器件具有虚设MOS晶体管，该虚设MOS晶体管包括：与上述沟槽隔离邻接的第一导电型的第二体区；与上述沟槽隔离邻接的第二导电型的第二漏极漂移区；与上述漏极漂移区接触的第二导电型的第二漏极区；形成在上述体区内的第二导电型的第二源极区；从上述第二源极区的端部覆盖至上述第二漏极漂移区上的第二绝缘膜；和隔着上述第二绝缘膜从上述第二源极区上覆盖至上述第二漏极漂移区上的第二栅极电极。此外，上述虚设MOS晶体管的第二体区、第二漏极漂移区分别与MOS晶体管的体区、漏极漂移区具有相同的杂质分布，并且，至少在与上述沟槽隔离接触的部分，上述虚设MOS晶体管的第二源极区与第二漏极区的距离和MOS晶体管的源极区与漏极区的距离相等。此外，所述虚设MOS晶体管的源极电极、漏极电极通过布线层与MOS晶体管的源极电极、漏极电极电连接，并且，所述虚设MOS晶体管的栅极电极与源极电极电连接。
发明效果
通过本发明，在高耐压横向半导体器件中，在器件端部的体区、漏极漂移区的端部设置沟槽隔离，并且与沟槽隔离邻接地形成二极管。进一步地，使与沟槽隔离邻接的二极管和MOS晶体管的杂质分布和尺寸等结构相同，并且将端子间电连接。因此，能够使对器件的各端子施加电压时的半导体区域的电场电位隔着沟槽隔离彼此相等。换而言之，能够使施加于沟槽隔离的电压为0。由此，器件端部的电场电位不会受到来自沟槽隔离的影响，通态击穿电压不会降低。并且，由于能够消除在以往结构中无法分离的端部的漏极漂移区，因此能够使端部的漏极电流特性与中央部相等。作为其结果，能够改善晶体管的通态电阻或漏极电流相对于栅极宽度的线性度。
此外，由于能够使端部的漏极电流特性与中央部相同，因此能够使通态电阻的温度特性固定而不依赖于栅极宽度。其结果是，在具有与主电路不同的晶体管栅极宽度的电流检测(传感)电路中，能够消除传感比的温度变化。
此外，由于能够使器件端部的漏极电流密度与中心部相同，所以对于端部的漏极电流密度比中心部大、通态击穿电压降低这一以往问题也是有效的。
附图说明
图1是表示本发明的实施方式1的高耐压NMOS晶体管的主要部分的俯视图。
图2中，(a)是图1的A-A’所示的区域的纵截面图。(b)是图1的B-B’所示的区域的纵截面图。(c)是图1的C-C’所示的区域的纵截面图。
图3是表示本发明的实施方式2的高耐压NMOS晶体管的主要部分的俯视图。
图4是表示本发明的实施方式3的高耐压NMOS晶体管的主要部分的俯视图。
图5是表示本发明的实施方式4的高耐压NMOS晶体管的主要部分的俯视图。
图6中，(a)是图5的A-A’所示的区域的纵截面图。(b)是图5的B-B’所示的区域的纵截面图。(c)是图5的C-C’所示的区域的纵截面图。
图7是第一以往高耐压NMOS晶体管的主要部分的俯视图。
图8是第二以往高耐压NMOS晶体管的主要部分的俯视图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。此外，本实施例中，在SOI(SiliconOnInsulator，绝缘体上硅)衬底上形成半导体器件，但也可在Si衬底上形成半导体器件。此外，在本实施例中以NMOS晶体管的情况进行说明，但也可为PMOS晶体管。
(实施方式1)
基于图1～图2说明本发明的第一实施方式。
图1是用于说明第一实施方式的俯视图，图2中，(a)、(b)、(c)表示图1的A-A’线、B-B’线、C-C’线的各截面图。
如图1、2所示，在由埋入氧化膜16和半导体层17构成的SOI衬底上具有MOS晶体管区域11和二极管区域12，其中，MOS晶体管区域11包括：P型体区1；与P型体区1邻接的N型漏极漂移区4；与N型漏极漂移区4接触的N+漏极区5；形成在P型体区内的源极区2；从源极区2的端部覆盖至漏极漂移区4上的绝缘膜13；隔着绝缘膜13从源极区2端部上覆盖至漏极漂移区4上的栅极电极3；和与P型体区1和漏极漂移区4的端部邻接的由绝缘膜构成的沟槽隔离10b，二极管区域12包括：与沟槽隔离10b邻接的P型阳极区6；与沟槽隔离10b邻接的N型阴极区8；从P型阳极区6的端部覆盖至N型阴极区8上的绝缘膜13；和隔着绝缘膜13从P型阳极区6上覆盖至N型阴极区8上的二极管场板电极7。至少在与沟槽隔离10b接触的部分，图2(b)所示的MOS晶体管区域的截面结构与图2(c)所示的二极管区域的截面结构除了N型源极区2、P+体接触扩散区15、P+阳极接触扩散区15之外是相同的。此外，虽然图中未记载，N+漏极区5与N+阴极接触扩散区9通过布线层电连接，P+体接触扩散区15与P+阳极接触扩散区14通过布线层电连接，栅极电极3与二极管场板电极7通过布线层电连接。由此，能够使得至少在靠近沟槽隔离10b的部分，对MOS晶体管11施加电压时，P型体区1、N型漏极漂移区4的电场电位与二极管12的P型阳极区6、N型阴极区8的电场电位相同，使施加到沟槽隔离10b的电场强度为0。由此，靠近沟槽隔离10b的MOS晶体管11的端部的电场电位不受沟槽隔离的影响，与MOS晶体管11端部以外的电场电位相同。其结果是，晶体管端部的漏极电流特性与端部以外的漏极电流特性相同。并且，在MOS晶体管11端部不会发生通态击穿电压、断态击穿电压的降低。
(实施方式2)
基于图3说明本发明的第二实施方式。与图1的结构不同之处是：图1中MOS晶体管11的栅极电极3通过布线层与二极管12的二极管场板电极7连接，而图3中栅极电极3与二极管场板电极直接连接。由此，能够得到与第一实施方式所述的效果相同的效果。
(实施方式3)
基于图4说明本发明的第三实施方式。与图3的结构不同之处是：在MOS晶体管11的N+漏极区5和N型漏极漂移区4周围设置有栅极电极3、N型源极区2，与之对应地，在二极管12的N型阴极区8周围设置有P+阳极接触扩散区。由此，如第一实施方式所述，对晶体管施加电压时施加到沟槽隔离10b的电场强度为0，能够得到相同的效果。
(实施方式4)
基于图5～图6说明本发明的第四实施方式。与图1的结构不同之处是：与沟槽隔离10b邻接地设置有虚设(dummy)MOS晶体管18来代替晶体管12。MOS晶体管11的截面结构(图6(b))与虚设MOS晶体管18的截面结构(图6(c))至少在靠近沟槽隔离10b的部分是相同的。此外，虽然图中未记载，N+漏极区5与虚设MOS晶体管18的N+漏极区22通过布线层电连接，P+体接触扩散区15与虚设MOS晶体管18的P+体接触扩散区24、虚设MOS晶体管18的栅极电极20通过布线层电连接。由此，能够使得至少在靠近沟槽隔离10b的部分，对MOS晶体管11施加电压时，P型体区1、N型漏极漂移区4的电场电位与虚设MOS晶体管的电场电位相同，使施加到沟槽隔离10b的电场强度为0。由此，能够得到第一实施方式中所述的效果。
附图标记说明
1……P型体区
2……N型源极区
3……栅极电极
4……N型漏极漂移区
5……N型漏极区
6……P型阳极区
7……二极管场板区
8……N型阴极区
9……N+阴极接触扩散区
10a……与外周衬底绝缘的沟槽隔离
10b……将MOS晶体管与二极管隔开的沟槽隔离
11……MOS晶体管区域
12……二极管区域
13……绝缘膜
14……P+阳极接触扩散区
15……P+体接触扩散区
16……埋入氧化膜
17……半导体层
18……虚设MOS晶体管区域
19……虚设MOS晶体管的P型体区
20……虚设MOS晶体管的栅极电极
21……虚设MOS晶体管的N型漏极区
22……虚设MOS晶体管的N+漏极区
23……虚设MOS晶体管的栅极氧化膜
24……虚设MOS晶体管的P+体接触扩散区
25……虚设MOS晶体管的N+源极区
26……P+扩散区

Claims (10)

1.一种形成在半导体衬底上的横向半导体器件，其特征在于，包括：
形成在所述半导体衬底层上的第一导电型的第一区域；
与所述第一导电型的区域邻接或者隔开间隔地将所述第一导电型的区域完全包围的第二导电型的第一区域；和
与所述第一导电型的第一区域和第二导电型的第一区域的端部邻接的由绝缘膜构成的沟槽隔离，并且，
所述横向半导体器件包括：
与所述沟槽隔离邻接的第一导电型的第二区域；和
与所述沟槽隔离邻接的第二导电型的第二区域，
所述第一导电型的第一区域和第二区域至少在与所述沟槽隔离邻接的区域中具有相同的杂质分布和相同的区域宽度，
所述第二导电型的第一区域和第二区域至少在与所述沟槽隔离邻接的区域中具有相同的杂质分布和相同的区域宽度，
第一导电型的第一区域和第二导电型的第一区域为构成晶体管的区域。
2.如权利要求1所述的形成在半导体衬底上的横向半导体器件，其特征在于，包括：
形成在所述半导体衬底层上的第一导电型的体区；
与所述体区邻接或者隔开间隔地将所述体区完全包围的第二导电型的漏极漂移区；
与所述漏极漂移区接触的第二导电型的漏极区；
形成在所述体区内的第二导电型的源极区；
从所述源极区的端部覆盖至所述漏极漂移区上的绝缘膜；
隔着所述绝缘膜从所述源极区的端部上覆盖至所述漏极漂移区上的栅极电极；和
与体区和漏极漂移区的端部邻接的由绝缘膜构成的所述沟槽隔离，并且，
所述横向半导体器件具有二极管，该二极管包括：
与所述沟槽隔离邻接的第一导电型的阳极区；
与所述沟槽隔离邻接的第二导电型的阴极区；和
从所述阳极区的端部覆盖至所述阴极区上的绝缘膜。
3.如权利要求2所述的横向半导体器件，其特征在于：
所述阳极区具有与所述体区相同的杂质分布，
所述阴极区具有与所述漏极区相同的杂质分布，
至少在靠近所述沟槽隔离的部分，所述源极区与所述漏极区的距离和连接所述阳极区的扩散区与连接所述阴极区的扩散区的距离相等，
至少在靠近所述沟槽隔离的部分，从所述源极区的端部延伸至所述漏极漂移区上的所述栅极电极的距离与从所述阳极区上延伸至所述阴极区上的二极管的场板电极的距离相等。
4.如权利要求2所述的横向半导体器件，其特征在于：
所述阳极区通过布线层与所述体区电连接，
所述阴极区通过布线层与所述漏极区电连接，
所述栅极电极与所述二极管场板电极电连接。
5.如权利要求2所述的横向半导体器件，其特征在于：
所述二极管以使得在对所述横向半导体器件的端子施加电压时施加到所述沟槽隔离的电场强度为0的方式形成。
6.如权利要求1所述的形成在半导体衬底上的横向半导体器件，其特征在于，包括：
形成在所述半导体衬底层上的第一导电型的体区；
与所述体区邻接或者隔开间隔地将所述体区完全包围的第二导电型的漏极漂移区；
与所述漏极漂移区接触的第二导电型的漏极区；
形成在所述体区内的第二导电型的源极区；
从所述源极区的端部覆盖至所述漏极漂移区上的绝缘膜；
隔着所述绝缘膜从所述源极区的端部上覆盖至所述漏极漂移区上的栅极电极；和
与体区和漏极漂移区的端部邻接的由绝缘膜构成的所述沟槽隔离，并且，
所述横向半导体器件具有虚设MOS晶体管，该虚设MOS晶体管包括：
与所述沟槽隔离邻接的第一导电型的第二体区；
与所述沟槽隔离邻接的第二导电型的第二漏极漂移区；
与所述漏极漂移区接触的第二导电型的第二漏极区；
形成在所述体区内的第二导电型的第二源极区；
从所述第二源极区的端部覆盖至所述第二漏极漂移区上的第二绝缘膜；和
隔着所述第二绝缘膜从所述第二源极区上覆盖至所述第二漏极漂移区上的第二栅极电极。
7.如权利要求6所述的横向半导体器件，其特征在于：
所述体区具有与所述第二体区相同的杂质分布，
所述漏极漂移区具有与所述第二漏极漂移区相同的杂质分布，
至少在靠近所述沟槽隔离的部分，所述源极区与所述漏极区的距离和所述第二源极区与所述第二漏极区的距离相等。
8.如权利要求6所述的横向半导体器件，其特征在于：
所述第二体区通过布线层与所述体区电连接，
所述第二漏极区通过布线层与所述漏极区电连接，
所述第二栅极电极与所述第二源极电极电连接。
9.如权利要求6所述的横向半导体器件，其特征在于：
所述虚设MOS晶体管以使得在对所述横向半导体器件的端子施加电压时所述沟槽隔离的电场强度为0的方式形成。
10.如权利要求1所述的横向半导体器件，其特征在于：
所述横向半导体器件装载在电流检测(传感)电路中。
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