CN110120414A - 晶体管结构 - Google Patents

晶体管结构 Download PDF

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CN110120414A
CN110120414A CN201810123483.2A CN201810123483A CN110120414A CN 110120414 A CN110120414 A CN 110120414A CN 201810123483 A CN201810123483 A CN 201810123483A CN 110120414 A CN110120414 A CN 110120414A
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embedding layer
transistor
substrate
arrangement according
transistor arrangement
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CN110120414B (zh
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陈彦铭
李久龄
蔡明轩
李秋德
王智充
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United Microelectronics Corp
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Abstract

本发明公开一种晶体管结构，包括基底、晶体管元件、分离式埋入层与第二埋入层。基底具有元件区。晶体管元件位于元件区中。分离式埋入层位于晶体管元件下方的基底中，且包括彼此分离的多个第一埋入层。第二埋入层位于分离式埋入层下方的基底中，且连接多个第一埋入层。第二埋入层与分离式埋入层具有第一导电型。上述晶体管结构可具有较高的击穿电压。

Description

晶体管结构
技术领域
本发明涉及一种半导体结构，且特别是涉及一种晶体管结构。
背景技术
在集成电路元件中，不同的电路需要具有不同基础操作特性的不同电路元件密切配合。其中，高压晶体管元件，顾名思义就是一种可以耐较高偏压的晶体管元件，意即高压晶体管元件的击穿电压(breakdown voltage)会较一般晶体管元件高。
然而，如何提高高压晶体管的击穿电压为目前面临的课题。
发明内容
本发明提出一种晶体管结构，其可具有较高的击穿电压。
本发明提供一种晶体管结构，包括基底、晶体管元件、分离式埋入层与第二埋入层。基底具有元件区。晶体管元件位于元件区中。分离式埋入层位于晶体管元件下方的基底中，且包括彼此分离的多个第一埋入层。第二埋入层位于分离式埋入层下方的基底中，且连接多个第一埋入层。第二埋入层与分离式埋入层具有第一导电型。
依照本发明的一实施例所述，在上述晶体管结构中，分离式埋入层与第二埋入层可在第二埋入层与分离式埋入层连接的位置形成阶梯结构。
依照本发明的一实施例所述，在上述晶体管结构中，第二埋入层与分离式埋入层重叠的部分例如是不超过分离式埋入层的两端。
依照本发明的一实施例所述，在上述晶体管结构中，基底可包括半导体基底与半导体层。半导体层设置于半导体基底上。
依照本发明的一实施例所述，在上述晶体管结构中，半导体基底与半导体层例如是具有第二导电型。
依照本发明的一实施例所述，在上述晶体管结构中，半导体层例如是外延硅层。
依照本发明的一实施例所述，在上述晶体管结构中，分离式埋入层可位于半导体基底与半导体层之间。
依照本发明的一实施例所述，在上述晶体管结构中，还可包括第一阱区。第一阱区位于晶体管元件的一侧的基底中，且连接于分离式埋入层。第一阱区具有第一导电型。
依照本发明的一实施例所述，在上述晶体管结构中，分离式埋入层、第二埋入层与第一阱区可包围晶体管元件。
依照本发明的一实施例所述，在上述晶体管结构中，还可包括第二阱区。第二阱区位于第一阱区中，且具有第一导电型。
依照本发明的一实施例所述，在上述晶体管结构中，还包括第一掺杂区。第一掺杂区位于所述第二阱区中，且具有第一导电型。
依照本发明的一实施例所述，在上述晶体管结构中，还包括第一隔离结构。第一隔离结构设置于基底中，且位于第一阱区与晶体管元件之间。
依照本发明的一实施例所述，在上述晶体管结构中，晶体管元件可包括栅极结构、第二掺杂区、第三掺杂区与第四掺杂区。栅极结构设置于基底上。第二掺杂区与第三掺杂区分别位于栅极结构的一侧与另一侧的基底中，且具有第二导电型。第四掺杂区位于第二掺杂区远离栅极结构的一侧的基底中，且具有第一导电型。
依照本发明的一实施例所述，在上述晶体管结构中，晶体管元件还可包括基体区(body region)与飘移区(drift region)。基体区位于栅极结构的一侧的基底中，且具有所述第一导电型。第二掺杂区与第四掺杂区可位于基体区中。飘移区位于栅极结构的另一侧的基底中，且具有第二导电型。第三掺杂区可位于飘移区中。
依照本发明的一实施例所述，在上述晶体管结构中，相对于穿过基体区且沿着基底的法线方向的轴，晶体管元件例如是镜像对称。
依照本发明的一实施例所述，在上述晶体管结构中，晶体管元件还可包括第三阱区。第三阱区位于基底中，且具有第二导电型。基体区与飘移区可位于第三阱区中。
依照本发明的一实施例所述，在上述晶体管结构中，晶体管元件还可包括第二隔离结构。第二隔离结构设置于基底中，且位于第二掺杂区与第三掺杂区之间。
依照本发明的一实施例所述，在上述晶体管结构中，部分栅极结构例如是位于第二隔离结构上。
依照本发明的一实施例所述，在上述晶体管结构中，晶体管元件例如是横向扩散金属氧化物半导体晶体管(lateral diffused metal-oxide-semiconductor transistor，LDMOS transistor)或漏极延伸金属氧化物半导体晶体管(drain extended metal-oxide-semiconductor transistor，DEMOS transistor)。
本发明提供一种晶体管结构，包括基底、晶体管元件、分离式埋入层与第二埋入层。基底具有元件区。晶体管元件位于元件区中。分离式埋入层位于晶体管元件下方的基底中，且包括彼此分离的多个第一埋入层。分离式埋入层在相邻两个第一埋入层之间具有开口。第二埋入层位于分离式埋入层下方的基底中，且封住开口的底部。第二埋入层与分离式埋入层具有第一导电型。
基于上述，在本发明的一实施例的晶体管结构中，由于分离式埋入层包括彼此分离的多个第一埋入层，第二埋入层连接多个第一埋入层，且第二埋入层与分离式埋入层具有相同的第一导电型，因此可有效地避免电场集中，进而可提高晶体管结构的击穿电压。
此外，在本发明的一实施例的晶体管结构中，由于分离式埋入层在相邻两个第一埋入层之间具有开口，第二埋入层封住开口的底部，且第二埋入层与分离式埋入层具有相同的第一导电型，因此可有效地避免电场集中，进而可提高晶体管结构的击穿电压。
另外，由于本发明的一实施例的晶体管结构的制作工艺不需对现有制作工艺进行大幅度地变更，因此可轻易地与现有制作工艺进行整合。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1为本发明的一实施例的晶体管结构的剖视图。
符号说明
100：晶体管结构
102：基底
102a：半导体基底
102b：半导体层
104：晶体管元件
106：分离式埋入层
106a、108：埋入层
110：栅极结构
112、114、116、138：掺杂区
118：栅极
120：栅介电层
122：间隙壁
124：基体区
126：飘移区
128、134、136：阱区
130、140、142：隔离结构
132：开口
A：轴
R：元件区
具体实施方式
图1为本发明的一实施例的晶体管结构的剖视图。
请参照图1，晶体管结构100包括基底102、晶体管元件104、分离式埋入层106与埋入层108。基底102具有元件区R。基底102可包括半导体基底102a与半导体层102b。半导体基底102a例如是硅基底。半导体层102b设置于半导体基底102a上。半导体层102b例如是外延硅层。
此外，第一导电型与第二导电型为不同导电型，且第一导电型与第二导电型可分别为N型导电型与P型导电型中的一者与另一者。在此实施例中，第一导电型是以N型导电型为例来进行说明，且第二导电型是以P型导电型为例来进行说明，但本发明并不以此为限。在另一实施例中，第一导电型可为P型导电型，且第二导电型可为N型导电型。
在此实施例中，半导体基底102a与半导体层102b是以具有第二导电型(如，P型导电型)为例来进行说明。
晶体管元件104位于元件区R中。晶体管元件104例如是横向扩散金属氧化物半导体晶体管(LDMOS transistor)或漏极延伸金属氧化物半导体晶体管(DEMOS transistor)。在此实施例中，晶体管元件104是以横向扩散金属氧化物半导体晶体管(LDMOStransistor)为例来进行说明，且晶体管元件104是以P型金属氧化物半导体晶体管(PMOStransistor)为例来进行说明，但本发明并不以此为限。
晶体管元件104可包括栅极结构110、掺杂区112、掺杂区114与掺杂区116。栅极结构110设置于基底102上。栅极结构110可包括栅极118与栅介电层120，且还可具有间隙壁122。栅极118设置于基底102上。栅极118的材料例如是掺杂多晶硅等导体材料。栅介电层120设置于栅极118与基底102之间。栅介电层120的材料例如是氧化硅等介电材料。间隙壁122设置于栅极118两侧的基底102上。间隙壁122可为单层结构或多层结构。在此实施例中，间隙壁122是以单层结构为例来进行说明。间隙壁122的材料例如是氮化硅、氧化硅或其组合。
掺杂区112与掺杂区114分别位于栅极结构110的一侧与另一侧的基底102中，且具有第二导电型(如，P型导电型)。掺杂区112与掺杂区114分别可作为源极与漏极。掺杂区116位于掺杂区112远离栅极结构110的一侧的基底102中，且具有第一导电型(如，N型导电型)。
此外，晶体管元件104还可包括基体区124、飘移区126、阱区128与隔离结构130中的至少一者。基体区124位于栅极结构110的一侧的基底102中，且具有所述第一导电型(如，N型导电型)。掺杂区112与掺杂区116可位于基体区124中。飘移区126位于栅极结构110的另一侧的基底102中，且具有第二导电型(如，P型导电型)。掺杂区114可位于飘移区126中。阱区128位于基底102中，且具有第二导电型(如，P型导电型)。基体区124与飘移区126可位于阱区128中。
隔离结构130设置于基底102中，且位于掺杂区112与掺杂区114之间。部分栅极结构110例如是位于隔离结构130上。隔离结构130例如是浅沟槽隔离结构。
此外，相对于穿过基体区124且沿着基底102的法线方向的轴A，晶体管元件104例如是镜像对称。
分离式埋入层106位于晶体管元件104下方的基底102中，且包括彼此分离的多个埋入层106a。然而，只要埋入层106a的数量为多个即属于本发明所主张的范围，并不限于图1中所绘示的数量。分离式埋入层106可位于半导体基底102a与半导体层102b之间。埋入层108位于分离式埋入层106下方的基底102中，且连接多个埋入层106a。在一实施例中，分离式埋入层106在相邻两个埋入层106a之间具有开口132，且埋入层108封住开口132的底部。埋入层108与分离式埋入层106具有第一导电型(如，N型导电型)。
此外，分离式埋入层106与埋入层108可在埋入层108与分离式埋入层106连接的位置形成阶梯结构。埋入层108与分离式埋入层106重叠的部分例如是不超过分离式埋入层106的两端。
另外，晶体管结构100中还可包括阱区134、阱区136、掺杂区138、隔离结构140与隔离结构142中的至少一者。阱区134位于晶体管元件104的一侧的基底102中，且连接于分离式埋入层106。阱区134具有第一导电型(如，N型导电型)。分离式埋入层106、埋入层108与阱区134可包围晶体管元件104。阱区136位于阱区134中，且具有第一导电型(如，N型导电型)。掺杂区138位于所述阱区136中，且具有第一导电型(如，N型导电型)。
隔离结构140设置于基底102中，且位于阱区134与晶体管元件104之间。隔离结构142设置于基底102中，且位于掺杂区138远离晶体管元件104的一侧的基底102中。隔离结构140与隔离结构142例如是浅沟槽隔离结构。
基于上述可知，在一实施例中，由于分离式埋入层106包括彼此分离的多个埋入层106a，埋入层108连接多个埋入层106a，且埋入层108与分离式埋入层106具有相同的第一导电型，因此可有效地避免电场集中，进而可提高晶体管结构100的击穿电压。
此外，在一实施例中，由于分离式埋入层106在相邻两个埋入层106a之间具有开口132，埋入层108封住开口132的底部，且埋入层108与分离式埋入层106具有相同的第一导电型，因此可有效地避免电场集中，进而可提高晶体管结构100的击穿电压。
此外，由于晶体管结构100的制作工艺不需对现有制作工艺进行大幅度地变更，因此可轻易地与现有制作工艺进行整合。
综上所述，上述实施例的晶体管结构可通过分离式埋入层与位于其下方的另一埋入层来提高晶体管结构的击穿电压，且可轻易地与现有制作工艺进行整合。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种晶体管结构，其特征在于，包括：
基底，具有元件区；
晶体管元件，位于所述元件区中；
分离式埋入层，位于所述晶体管元件下方的所述基底中，且包括彼此分离的多个第一埋入层；以及
第二埋入层，位于所述分离式埋入层下方的所述基底中，且连接所述多个第一埋入层，其中所述第二埋入层与所述分离式埋入层具有第一导电型。
2.根据权利要求1所述的晶体管结构，其特征在于，所述分离式埋入层与所述第二埋入层在所述第二埋入层与所述分离式埋入层连接的位置形成阶梯结构。
3.根据权利要求1所述的晶体管结构，其特征在于，所述第二埋入层与所述分离式埋入层重叠的部分不超过所述分离式埋入层的两端。
4.根据权利要求1所述的晶体管结构，其特征在于，所述基底包括：
半导体基底；以及
半导体层，设置于所述半导体基底上。
5.根据权利要求4所述的晶体管结构，其特征在于，所述半导体基底与所述半导体层具有第二导电型。
6.根据权利要求4所述的晶体管结构，其特征在于，所述半导体层包括外延硅层。
7.根据权利要求4所述的晶体管结构，其特征在于，所述分离式埋入层位于所述半导体基底与所述半导体层之间。
8.根据权利要求1所述的晶体管结构，其特征在于，还包括：
第一阱区，位于所述晶体管元件的一侧的所述基底中，且连接于所述分离式埋入层，其中所述第一阱区具有所述第一导电型。
9.根据权利要求8所述的晶体管结构，其特征在于，所述分离式埋入层、所述第二埋入层与所述第一阱区包围所述晶体管元件。
10.根据权利要求8所述的晶体管结构，其特征在于，还包括：
第二阱区，位于所述第一阱区中，且具有所述第一导电型。
11.根据权利要求10所述的晶体管结构，其特征在于，还包括：
第一掺杂区，位于所述第二阱区中，且具有所述第一导电型。
12.根据权利要求8所述的晶体管结构，其特征在于，还包括：
第一隔离结构，设置于所述基底中，且位于所述第一阱区与所述晶体管元件之间。
13.根据权利要求1所述的晶体管结构，其特征在于，所述晶体管元件包括：
栅极结构，设置于所述基底上；
第二掺杂区与第三掺杂区，分别位于所述栅极结构的一侧与另一侧的所述基底中，且具有第二导电型；以及
第四掺杂区，位于所述第二掺杂区远离所述栅极结构的一侧的所述基底中，且具有所述第一导电型。
14.根据权利要求13所述的晶体管结构，其特征在于，所述晶体管元件还包括：
基体区，位于所述栅极结构的一侧的所述基底中，且具有所述第一导电型，其中所述第二掺杂区与所述第四掺杂区位于所述基体区中；以及
飘移区，位于所述栅极结构的另一侧的所述基底中，且具有所述第二导电型，其中所述第三掺杂区位于所述飘移区中。
15.根据权利要求14所述的晶体管结构，其特征在于，相对于穿过所述基体区且沿着所述基底的法线方向的轴，所述晶体管元件为镜像对称。
16.根据权利要求14所述的晶体管结构，其特征在于，所述晶体管元件还包括：
第三阱区，位于所述基底中，且具有所述第二导电型，其中所述基体区与所述飘移区位于所述第三阱区中。
17.根据权利要求13所述的晶体管结构，其特征在于，所述晶体管元件还包括：
第二隔离结构，设置于所述基底中，且位于所述第二掺杂区与所述第三掺杂区之间。
18.根据权利要求17所述的晶体管结构，其特征在于，部分所述栅极结构位于所述第二隔离结构上。
19.根据权利要求1所述的晶体管结构，其特征在于，所述晶体管元件包括横向扩散金属氧化物半导体晶体管或漏极延伸金属氧化物半导体晶体管。
20.一种晶体管结构，其特征在于，包括：
基底，具有元件区；
晶体管元件，位于所述元件区中；
分离式埋入层，位于所述晶体管元件下方的所述基底中，且包括彼此分离的多个第一埋入层，其中所述分离式埋入层在相邻两个第一埋入层之间具有开口；以及
第二埋入层，位于所述分离式埋入层下方的所述基底中，且封住所述开口的底部，其中所述第二埋入层与所述分离式埋入层具有第一导电型。
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