CN105321888A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN105321888A
CN105321888A CN201410441735.8A CN201410441735A CN105321888A CN 105321888 A CN105321888 A CN 105321888A CN 201410441735 A CN201410441735 A CN 201410441735A CN 105321888 A CN105321888 A CN 105321888A
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Prior art keywords
line layer
insulating barrier
electric conductor
opening
making
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Granted
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CN201410441735.8A
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CN105321888B (zh
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许诗滨
曾昭崇
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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Abstract

一种封装结构及其制法，该制法，先于一承载板上形成一第一线路层，且于该第一线路层上形成多个第一导电体，再以一第一绝缘层包覆该第一线路层与该多个第一导电体，接着于该第一绝缘层上形成一第二线路层，且于该第二线路层上形成多个第二导电体，再以一第二绝缘层包覆该第二线路层与该多个第二导电体，之后于该第二绝缘层形成至少一开口，以于该开口中设置至少一电子元件，所以通过先形成两绝缘层，再形成该开口，因而不需堆叠或压合已开口的基材，使该电子元件不会受压迫而位移，以减少良率损失。

Description

封装结构及其制法
技术领域
本发明有关一种封装结构，尤指一种嵌埋电子元件的封装结构及其制法。
背景技术
随着半导体封装技术的演进，于智慧型手机、平板、网络、笔记型电脑等产品中，半导体装置(Semiconductordevice)已开发出不同的封装型态，而该半导体装置主要通过在一封装基板(packagesubstrate)装置晶片，且将晶片电性连接在该封装基板上，接着再以胶体进行封装；而为降低封装高度，遂有将晶片嵌埋在一封装基板中，而此种封装件能缩减整体半导体装置的体积并提升电性功能，遂成为一种封装的趋势。
图1A至图1D为现有封装结构1的制法的剖视示意图。
如图1A所示，提供一具有贯穿的开口130的核心板13，于该核心板13的上、下两侧具有多个内层线路11与一铜窗110，且于该核心板13中形成多个导电柱12，以电性连接上、下两侧的内层线路11。
如图1B所示，于该核心板13底侧设置一承载板10，如聚酰亚胺(Polyimide，简称PI)胶带，以将一具有多个电极垫180的半导体晶片18容置于该开口130中，且该半导体晶片18设于该承载板10上。通过该铜窗110的设计，可避免该半导体晶片18接触该内层线路11。
如图1C所示，于该核心板13上侧及半导体晶片18上压合一介电材料，使该介电材料填入该开口130的孔壁与半导体晶片18之间的间隙中，再移除该承载板10，之后压合另一介电材料于该核心板13下侧，使两介电材料形成一介电材料层16。
如图1D所示，于该介电材料层16的上、下侧分别形成一线路层14，且该线路层14具有位于该介电材料层16中并电性连接该电极垫180与内层线路11的导电体15。
然而，现有封装结构1的制法中，因使用该铜窗110作阻隔层，会减少该内层线路11的布线区域，且以CO2激光形成该开口130，会增加激光制程与成本，并使该核心板13的有机玻纤露出，因而导致影响该半导体晶片18置放良率与品质。
此外，需使用激光制程制作盲孔(即该导电体15的位置)或通孔(即该导电柱12的位置)，所以仅能制作圆形孔型，且孔型不佳。
另外，使用PI胶带(该承载板10)固定该半导体晶片18，不仅需增加贴胶带与撕胶带制程，且增加胶带耗材与设备成本。
另外，需经过两次介电材料的制作，再进行压合以形成该介电材料层16，所以需进行预压制程与固化(Cure)压合制程，不仅增加制程时间与成本，且导致该半导体晶片18产生偏移(甚至旋转)，因而不易准确定位于该开口130中，以致于该半导体晶片18的电极垫180不易与该导电体15精准对应，而容易产生电性连接的品质不良或失效的情况，导致降低产品的良率。
图1A’至图1D’为另一现有封装结构1’的制法的剖视示意图。
如图1A’所示，于一如铜箔基板的承载板10上形成一第一线路层11’，且将一无源元件18’，如积层陶瓷电容器(Multi-layerCeramicCapacitor，简称MLCC)通过绝缘胶材180’固定于该第一线路层11’上。
如图1B’所示，将一具有贯穿的开口130的第一介电材料层13’设于该承载板10上，且该无源元件18’容置于该开口130中。
如图1C’所示，于该第一介电材料层13’上侧及该无源元件18’上压合第二介电材料层，且该第二介电材料层填入于该开口130的孔壁与无源元件18’之间的间隙中，使该第一介电材料层13’与该第二介电层热压形成一介电材料包覆层16’，以将该无源元件18’与该第一线路层11’固定于该介电材料包覆层16’中。
如图1D’所示，于该介电材料包覆层16’的上侧上形成第二线路层14’，且该第二线路层14’具有位于该介电材料包覆层16’中并电性连接该无源元件18’的导电体15。接着，移除该承载板10以外露该第一线路层11’。
现有封装结构1’的制法中，因使用铜箔基板作该承载板10，所以容易产生分层，而造成结构损坏，且需使用激光制程制作盲孔(即该导电体15的位置)，所以仅能制作圆形孔型，且孔型不佳。
此外，使用非导电材与点胶方式粘着该无源元件18’，由于点胶的胶粒直径大于200um，所以每次点胶的粒径误差极大，因而不易控制，导致该绝缘胶材180’容易扩流至其它区域，以致于该第一线路层11’的各线路间易受胶材粘着，而有信赖度的风险。
又，需经过两次介电材料层的制作，再进行压合以形成该介电材料包覆层16’，所以该第一介电材料层13’与该第二介电材料层两者的置放容易错位，不仅增加制程时间与成本，且该无源元件18’置放后而于烘烤该介电材料包覆层16’之前，该无源元件18’并未固定，所以该无源元件18’容易偏移，而造成良率损失。
另外，使用该导电体15对该无源元件18’作单侧的电性导通，会增加电性路径及信号损失的风险，且使用铜电极MLCC做为该无源元件18’，其非一般封装界使用的元件，所以成本极高。
因此，如何避免现有技术中的种种缺失，实已成为目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种封装结构及其制法，不需堆叠或压合已开口的基材，使该电子元件不会受压迫而位移，以减少良率损失。
本发明的封装结构，其特征为包括：一第一绝缘层，其具有相对的第一表面及第二表面；一第一线路层，其结合于该第一绝缘层的第一表面；多个第一导电体，其设于该第一绝缘层中并电性连接该第一线路层；一第二线路层，其设于该第一绝缘层的第二表面上并通过该多个第一导电体电性连接该第一线路层；多个第二导电体，其设于该第二线路层上；一第二绝缘层，其设于该第一绝缘层的第二表面上并包覆该第二线路层与该多个第二导电体，且该第二绝缘层上具有至少一开口，以令该第二线路层的部分表面外露于该开口；以及至少一电子元件，其设于该开口中并电性连接该第二线路层。
本发明还提供一种封装结构的制法，其特征为包括：于一承载板上形成第一线路层；于该第一线路层上形成多个第一导电体；于该承载板上形成一具有相对的第一表面及第二表面的第一绝缘层，以令该第一绝缘层包覆该第一线路层与该多个第一导电体，且该第一绝缘层通过其第一表面结合至该承载板上；于该第一绝缘层的第二表面上形成第二线路层，以令该第二线路层通过该多个第一导电体电性连接该第一线路层；于该第二线路层上形成多个第二导电体；于该第一绝缘层的第二表面上形成第二绝缘层，以令该第二绝缘层包覆该第二线路层与该多个第二导电体；于该第二绝缘层形成至少一开口，以令该第二线路层的部分表面外露于该开口；以及于该开口中设置至少一电子元件，且该电子元件电性连接该第二线路层。
由上可知，本发明封装结构及其制法，先形成两层线路布设，再于第二绝缘层上形成开口，以有效利用该多个第二导电体以外的无效区域制作该开口，而有效使用立体空间，不仅能缩小封装后整体体积与增加该第二线路层的布线应用，且可增加电性与信号稳定。
此外，本发明未使用核心板，因而更能缩小整体基板尺寸，以提升布线使用率。
另外，本发明不需堆叠或压合已开口的基材，所以该电子元件不会受压迫而位移，因而能有效定位该电子元件，以减少良率损失。
附图说明
图1A至图1D为现有封装结构的制法的剖视示意图；
图1A’至图1D’为现有封装结构的另一制法的剖视示意图；
图2A至图2G为本发明的封装结构的制法的剖视示意图；其中，图2F’及图2F”为图2F的其它不同实施例，图2G’及图2G”为图2G的其它不同实施例；以及
图3为本发明的封装结构的另一实施例的剖视示意图。
其中，附图标记说明如下：
1，1’，2，3封装结构
10，20承载板
11内层线路
11’，21第一线路层
110铜窗
12导电柱
13核心板
13’第一介电材料层
130，260，260’开口
14线路层
14’，24，24’，24”，34第二线路层
15导电体
16介电材料层
16’介电材料包覆层
18半导体晶片
18’无源元件
180电极垫
180’绝缘胶材
20承载件
21a，24a，24a’，24a”表面
210电性连接垫
211，241，341导电迹线
22第一导电体
22a端面
23第一绝缘层
23a第一表面
23b第二表面
240，340电性接触垫
25第二导电体
26第二绝缘层
260a底面
27阻层
270开口区
28，28’，28a，28b电子元件
280导电材料
29导电元件。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的封装结构2的制法的剖视示意图。
如图2A所示，通过图案化制程于一承载板20上形成一第一线路层21，再于该第一线路层21上形成多个第一导电体22。
于本实施例中，该承载板20为基材，例如铜箔基板或其它板体，并无特别限制。
此外，该第一线路层21包含多个电性连接垫210与多个导电迹线211，且该第一导电体22为导电柱，如铜柱。
如图2B所示，于该承载板20上形成一具有相对的第一表面23a及第二表面23b的第一绝缘层23，以令该第一绝缘层23包覆该第一线路层21与该多个第一导电体22，且该第一绝缘层23通过其第一表面23a结合至该承载板20上。
于本实施例中，该多个第一导电体22的一端面22a外露于该第一绝缘层23的第二表面23b。
此外，该第一线路层21的表面21a齐平该第一绝缘层23的第一表面23a。
另外，该第一绝缘层23以压合或铸模(molding)方式制作。
如图2C所示，于该第一绝缘层23的第二表面23b上形成一第二线路层24，以令该第二线路层24通过该多个第一导电体22电性连接该第一线路层21。接着，于该第二线路层24上形成多个第二导电体25，再于该第一绝缘层23的第二表面23b上形成一第二绝缘层26，以令该第二绝缘层26包覆该第二线路层24与该多个第二导电体25。
于本实施例中，该第二线路层24包含多个电性接触垫240与多个导电迹线241，且该多个电性接触垫240与该导电迹线241直接连接该多个第一导电体22。
此外，该第二导电体25为导电柱，如铜柱，且该第二导电体25的一端面外露于该第二绝缘层26。
又，该第二绝缘层26以压合或铸模(molding)方式制作。
如图2D所示，形成一如光阻的阻层27于该第二绝缘层26上，且该阻层27具有至少一开口区270，以令该第二绝缘层26的部分表面外露于该开口区270。接着，于该开口区270中的第二绝缘层26上形成至少一开口260，令该第二线路层24的部分表面(即该多个电性接触垫240)外露于该开口260。
于本实施例中，该开口260以如研磨法(pumice)的研磨方式制作或以激光烧灼方式制作，并非采用传统铣刀成型方式制作，所以可缩小该开口260于转弯处的导角(如底面处、开口处)。
此外，该第二线路层24的表面24a齐平该开口260的底面260a。
又，该多个电性接触垫240未受激光或铣刀、钻针破坏而凹陷，所以该多个电性接触垫240能保持表面完整。
如图2E所示，移除该阻层27。于本实施例中，该第二导电体25的一端面外露于该第二绝缘层26，因而无需于该第二导电体25上制作接触垫，以有效利用各该第二导电体25之间的空间而形成该开口260。
如图2F所示，移除该承载板20，且于该开口260中设置至少一电子元件28，因而该电子元件28不会包覆于该第一绝缘层23或第二绝缘层26中，并使该电子元件28电性连接该第二线路层24的电性接触垫240。本发明的制法未使用传统铣刀成型方式，所以可缩小该电子元件28与该开口260的孔壁间的距离。
于本实施例中，该电子元件28可为有源元件、无源元件或其二者组合，且该有源元件例如半导体元件(如晶片)，而该无源元件例如电阻、电容及电感。其中，第2F图所示的电子元件28为无源元件，如多层陶瓷电容器(Multi-layerCeramicCapacitor，简称MLCC)，且该电子元件28使用现行封装界的焊锡制程制作，而无需使用较高成本的铜电极，以降低成本。
此外，该电子元件28通过印刷或点胶等的导电材料280(如焊料或导电胶)固接并电性连接于该多个电性接触垫240上，且通过限制各该电性接触垫240的尺寸或形状，以防止胶材扩散至相邻的电性接触垫240。
又，于另一实施例中，如图2F’所示，该电子元件28’为有源元件，且各该电性接触垫240间可依需求增设线路，以对应该电子元件28’的接点。
另外，如图2F”所示，可于该开口260’内形成高低不等的平面，即该开口260’内为阶梯状，以于不同高度的阶面上设置多个电子元件28a,28b而增加立体空间使用率，例如，其中一电子元件28a为无源元件，而另一电子元件28b为有源元件。
如图2G所示，形成多个如焊球的导电元件29于该第二绝缘层26上，且该多个导电元件29电性连接该多个第二导电体25，以通过该多个导电元件29堆叠结合其它电子装置(图略)。
于本实施例中，通过该多个导电元件29的设计以增加利用空间，所以于后续堆叠制程时，该电子元件28不会碰撞其它电子装置。
于其它实施例中，依孔深设计，该第二线路层24’的表面24a’高于该开口260的底面260a，如图2G’所示；或者，该第二线路层24”的表面24a”低于该开口260的底面260a，如图2G”所示的嵌埋式线路。
另外，如图3所示，该第二线路层34的电性接触垫340通过该导电迹线341间接连接该第一导电体22，也就是该电性接触垫340并未直接连接该第一导电体22。
本发明封装结构2的制法中，利用各该第二导电体25之间的无效区域制作开口260，以有效使用立体空间，不仅缩小封装后整体体积(如厚度)与增加该第二线路层24的布线应用，且可增加电性与信号稳定。
此外，相较于现有使用玻璃纤维作为介电材料内埋元件结构，本发明未使用核心板，因而更能缩小整体基板尺寸，以改善于有限空间内的布线使用率。
又，本发明不需堆叠或压合已开口的基材，所以该电子元件28不会受压迫而位移，因而能有效定位该电子元件28，以减少良率损失。
另外，传统电路板与球栅阵列封装(BallGridArray，简称BGA)等电路板制程需使用多张介电材料层压合才能完成内埋式元件制程，因而该内埋式元件的高度与该介电层的厚度会产生配合不易等问题。若使用凹槽(cavity)方式内埋电子元件，常见开口制程利用机械式成型机与铣刀等工具，所以每一凹槽需将每一介电材料层进行开口，因而耗时长，且物料成本增加。若使用本发明进行内埋元件，只需使用一般表面粘着技术(SurfaceMountTechnology，简称SMT)的封装流程，再以铸模(molding)方式一次完成，所以无需使用多张介电材料层与进行多次开口制程。若外层开口制程(如该开口260)因使用本发明制程材料特性，因而可用一次性生产或整面性生产，如研磨法(pumice)，借以缩短生产时程与成本，此方式为传统电路板或BGA等电路板所无法制作出的。
本发明还提供一种封装结构2，3，包括：一第一绝缘层23、一第一线路层21、多个第一导电体22、一第二线路层24，34、多个第二导电体25、一第二绝缘层26、以及至少一电子元件28。
所述的第一绝缘层23具有相对的第一表面23a及第二表面23b。
所述的第一线路层21结合于该第一绝缘层23的第一表面23a。例如，该第一线路层21嵌埋于该第一绝缘层23的第一表面23a且齐平该第一表面23a。
所述的第一导电体22为导电柱，其设于该第一绝缘层23中并连通该第二表面23b且电性连接该第一线路层21。
所述的第二线路层24，34设于该第一绝缘层23的第二表面23b上并通过该多个第一导电体22电性连接该第一线路层21。
所述的第二导电体25为导电柱，其设于该第二线路层24上。
所述的第二绝缘层26设于该第一绝缘层23的第二表面23b上并包覆该第二线路层24与该多个第二导电体25，且该第二绝缘层26上具有至少一开口260，以令该第二线路层24的部分表面外露于该开口260。
所述的电子元件28设于该开口260中并电性连接该第二线路层24。例如，该电子元件28，28’，28a，28b为有源元件、无源元件或其二者组合。
于一实施例中，该第二线路层24，24’的表面24a，24a’高于或齐平该开口260的底面260a。
于一实施例中，该第二线路层24”的表面24a”低于该开口260的底面260a。
于一实施例中，该第二线路层24，34包含多个电性接触垫240，340与电性连接该电性接触垫240，340的多个导电迹线241，341，且该多个电性接触垫240，340结合并电性连接该电子元件28。其中，该电性接触垫240连接该第一导电体22；或者，该电性接触垫340未连接该第一导电体22，且该导电迹线341连接该第一导电体22。
于一实施例中，该开口260’内为阶梯状。
于一实施例中，所述的封装结构2还包括设于该第二绝缘层26上的多个导电元件29，其电性连接各该第二导电体25。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (26)

1.一种封装结构，其特征为包括：
一第一绝缘层，其具有相对的第一表面及第二表面；
一第一线路层，其结合于该第一绝缘层的第一表面；
多个第一导电体，其设于该第一绝缘层中并电性连接该第一线路层；
一第二线路层，其形成于该第一绝缘层的第二表面上并通过该多个第一导电体电性连接该第一线路层；
多个第二导电体，其设于该第二线路层上；
一第二绝缘层，其形成于该第一绝缘层的第二表面上并包覆该第二线路层与该多个第二导电体，且该第二绝缘层上具有至少一开口，以令该第二线路层的部分表面外露于该开口；以及
至少一电子元件，其设于该开口中并电性连接该第二线路层。
2.如权利要求1所述的封装结构，其特征为，该第一线路层嵌埋于该第一绝缘层的第一表面。
3.如权利要求1所述的封装结构，其特征为，该第一导电体为导电柱。
4.如权利要求1所述的封装结构，其特征为，该第二导电体为导电柱。
5.如权利要求1所述的封装结构，其特征为，该第二线路层的表面高于或齐平该开口的底面。
6.如权利要求1所述的封装结构，其特征为，该第二线路层的表面低于该开口的底面。
7.如权利要求1所述的封装结构，其特征为，该第二线路层包含多个电性接触垫与多个导电迹线，且该多个电性接触垫结合并电性连接该电子元件。
8.如权利要求7所述的封装结构，其特征为，该电性接触垫连接该第一导电体。
9.如权利要求7所述的封装结构，其特征为，该电性接触垫未连接该第一导电体，且该导电迹线连接该第一导电体。
10.如权利要求1所述的封装结构，其特征为，该开口内为阶梯状。
11.如权利要求1所述的封装结构，其特征为，该电子元件为有源元件、无源元件或其二者的组合。
12.如权利要求1所述的封装结构，其特征为，该封装结构还包括设于该第二绝缘层上的多个导电元件，其电性连接各该第二导电体。
13.一种封装结构的制法，其特征为包括：
于一承载板上形成第一线路层；
于该第一线路层上形成多个第一导电体；
于该承载板上形成一具有相对的第一表面及第二表面的第一绝缘层，以令该第一绝缘层包覆该第一线路层与该多个第一导电体，且该第一绝缘层通过其第一表面结合至该承载板上；
于该第一绝缘层的第二表面上形成第二线路层，以令该第二线路层通过该多个第一导电体电性连接该第一线路层；
于该第二线路层上形成多个第二导电体；
于该第一绝缘层的第二表面上形成一第二绝缘层，以令该第二绝缘层包覆该第二线路层与该多个第二导电体；
于该第二绝缘层形成至少一开口，以令该第二线路层的部分表面外露于该开口；以及
于该开口中设置至少一电子元件，且令该电子元件电性连接该第二线路层。
14.如权利要求13所述的封装结构的制法，其特征为，该第一线路层的表面齐平该第一绝缘层的第一表面。
15.如权利要求13所述的封装结构的制法，其特征为，该第一导电体为导电柱。
16.如权利要求13所述的封装结构的制法，其特征为，该第二导电体为导电柱。
17.如权利要求13所述的封装结构的制法，其特征为，该第二线路层的表面高于或齐平该开口的底面。
18.如权利要求13所述的封装结构的制法，其特征为，该第二线路层的表面低于该开口的底面。
19.如权利要求13所述的封装结构的制法，其特征为，该第二线路层包含多个电性接触垫与多个导电迹线，且该多个电性接触垫结合并电性连接该电子元件。
20.如权利要求19所述的封装结构的制法，其特征为，该电性接触垫连接该第一导电体。
21.如权利要求19所述的封装结构的制法，其特征为，该电性接触垫未连接该第一导电体，且该导电迹线连接该第一导电体。
22.如权利要求13所述的封装结构的制法，其特征为，该开口以研磨方式或激光方式制作。
23.如权利要求13所述的封装结构的制法，其特征为，该开口内为阶梯状。
24.如权利要求13所述的封装结构的制法，其特征为，该电子元件为有源元件、无源元件或其二者组合。
25.如权利要求13所述的封装结构的制法，其特征为，该制法还包括形成多个导电元件于该第二绝缘层上，且该多个导电元件电性连接该多个第二导电体。
26.如权利要求13所述的封装结构的制法，其特征为，该制法还包括于形成该开口之后，移除该承载板。
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