CN105280616A - 互连结构和方法 - Google Patents
互连结构和方法 Download PDFInfo
- Publication number
- CN105280616A CN105280616A CN201410803165.2A CN201410803165A CN105280616A CN 105280616 A CN105280616 A CN 105280616A CN 201410803165 A CN201410803165 A CN 201410803165A CN 105280616 A CN105280616 A CN 105280616A
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- Prior art keywords
- layer
- metal wire
- metal
- polymeric layer
- polymeric
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 66
- 229920000642 polymer Polymers 0.000 claims abstract description 41
- 238000001465 metallisation Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 200
- 229910052751 metal Inorganic materials 0.000 claims description 170
- 239000002184 metal Substances 0.000 claims description 170
- 239000013047 polymeric layer Substances 0.000 claims description 81
- 239000004020 conductor Substances 0.000 claims description 61
- 230000008569 process Effects 0.000 claims description 40
- 239000003822 epoxy resin Substances 0.000 claims description 18
- 229920000647 polyepoxide Polymers 0.000 claims description 18
- 239000004642 Polyimide Substances 0.000 claims description 17
- 229920001721 polyimide Polymers 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 11
- 229920005575 poly(amic acid) Polymers 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 8
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- 230000008021 deposition Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 63
- 238000005516 engineering process Methods 0.000 description 25
- 230000004888 barrier function Effects 0.000 description 21
- 239000000758 substrate Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 17
- 238000005530 etching Methods 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000010949 copper Substances 0.000 description 16
- 238000001723 curing Methods 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
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- 238000010168 coupling process Methods 0.000 description 5
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- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- FXHOOIRPVKKKFG-UHFFFAOYSA-N N,N-Dimethylacetamide Chemical compound CN(C)C(C)=O FXHOOIRPVKKKFG-UHFFFAOYSA-N 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- WYURNTSHIVDZCO-UHFFFAOYSA-N Tetrahydrofuran Chemical compound C1CCOC1 WYURNTSHIVDZCO-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
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- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000011415 microwave curing Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
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- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- 229910021341 titanium silicide Inorganic materials 0.000 description 1
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
本发明提供了一种互连结构和方法。一种器件,包括:第一导电线,位于介电层上方的第一金属层中,其中,第一导电线在三个侧面被第一聚合物层包裹,并且第一导电线和介电层通过第一聚合物层的底部隔离;第二导电线,位于介电层上方,其中,第二导电线在三个侧面被第二聚合物层包裹,并且第二导电线和介电层被第二聚合物层的底部隔离;以及气隙,位于第一导电线和第二导电线之间。
Description
技术领域
本发明涉及互连结构和方法。
背景技术
半导体行业由于各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的持续改进而经历了快速的发展。很大程度上,这种集成密度的改进源于最小部件尺寸的不断缩小,这使得更多的部件集成到给定区域中。随着近来对更小电子器件的需求的增加,需要更小且更具有创造性的半导体管芯的封装技术。
随着半导体技术的进步,出现晶圆级芯片规模封装结构作为进一步减小半导体器件的物理尺寸的有效可选方式。在晶圆级芯片规模封装结构中,诸如晶体管等的有源器件形成在晶圆级芯片规模封装结构的顶面处。包括互连结构的各种金属化层形成在衬底上方。半导体器件的互连结构可包括多个横向互连件(诸如金属线)和多个垂直互连件(诸如通孔、插塞等)。金属化层的金属线通过介电层隔离。沟槽和通孔形成在介电层中以提供金属线之间的电连接。半导体器件的各个有源电路可通过由垂直和横向互连件形成的各种导电通道连接至外部电路。
金属线和通孔可由铜形成。为了防止诸如两条相邻金属线之间的电容耦合的干扰对半导体器件的整体性能产生影响,低K介电材料可填充在相邻的金属线之间。低K介电材料的介电常数可近似等于或小于4.0。此外,可以使用气隙来进一步减少电容耦合,从而提高半导体器件的整体性能特性。
发明内容
针对现有技术中存在的问题,根据本发明的一个方面,提供了一种装置,包括:
第一导电线,位于介电层上方的第一金属层中,其中:
第一导电线在三个侧面被第一聚合物层包裹;并且
第一导电线和介电层通过第一聚合物层的底部隔离;
第二导电线,位于介电层上方,其中:
第二导电线在三个侧面被第二聚合物层包裹;并且
第二导电线和介电层被第二聚合物层的底部隔离;以及
气隙,位于第一导电线和第二导电线之间。
根据本发明的一个实施例,第一聚合物层和第二聚合物层包括聚酰亚胺。
根据本发明的一个实施例,第一聚合物层和第二聚合物层包括交联环氧树脂。
根据本发明的一个实施例,第一聚合物层包括第一侧壁、第二侧壁和第一底部,第一导电线在三个侧面被第一侧壁、第二侧壁和第一底部包裹;并且
第二聚合物层包括第三侧壁、第四侧壁和第二底部,第二导电线在三个侧面被第三侧壁、第四侧壁和第二底部包裹。
根据本发明的一个实施例,气隙位于第一聚合物层的第二侧壁和第二聚合物层的第三侧壁之间。
根据本发明的一个实施例,还包括:第二金属化层,位于第一金属化层上方,气隙位于第二金属化层和介电层之间。
根据本发明的一个实施例,第二金属化层包括形成在聚合物层中的多条金属线。
根据本发明的另一方面,提供了一种器件,包括:
第一金属化层,位于介电层上方,第一金属化层包括:
第一金属线,在三个侧面被第一聚合物层包裹;和
气隙,与第一金属线相邻,气隙和第一金属线被第一聚合物层的侧壁隔离;以及
第二金属化层,位于第一金属化层上方,其中:
第一金属线的顶面与第二金属化层的底面直接接触;并且
第一金属线的底面和介电层通过第一聚合物层的底部隔开。
根据本发明的一个实施例,第一聚合物层的底部的厚度在大约1nm至大约5nm的范围内。
根据本发明的一个实施例,还包括:第二金属线,在三个侧面被第二聚合物层包裹,其中,气隙位于第一金属线和第二金属线之间。
根据本发明的一个实施例,第一聚合物层包括聚酰亚胺。
根据本发明的一个实施例,第一聚合物层包括交联环氧树脂。
根据本发明的一个实施例,第二金属化层包括被聚合物材料环绕的通孔,其中,通孔的底面与第一金属化层的金属线的顶面直接接触。
根据本发明的一个实施例,通孔和金属线包括铜。
根据本发明的又一方面,提供了一种方法,包括:
在介电层上方沉积第一聚合物层;
使用蚀刻工艺形成第一开口和第二开口,第一开口和第二开口部分地穿过第一聚合物层;
用导电材料填充第一开口和第二开口,以形成第一金属线和第二金属线;
对第一聚合物层施加选择性热固化工艺,直到第一聚合物层环绕第一金属线和第二金属线的部分被固化;
通过清洁工艺去除第一聚合物层的未固化部分;以及
沉积介电层以在第一金属线和第二金属线之间形成气隙。
根据本发明的一个实施例,还包括:将热源引导至第一金属线和第二金属线上;
固化第一聚合物层直到环绕第一金属线和第二金属线的区域中的聚酰胺酸转化为聚酰亚胺。
根据本发明的一个实施例,还包括:将热源引导至第一金属线和第二金属线上;
固化第一聚合物层直到环绕第一金属线和第二金属线的区域中的环氧树脂转化为交联环氧树脂。
根据本发明的一个实施例,还包括:在第一金属线和第二金属线上方设置第二聚合物层,以在第一金属线和第二金属线之间形成气隙;
对第二聚合物层施加固化工艺;以及
在第二聚合物层中形成通孔,通孔的底面与金属线的顶面直接接触。
根据本发明的一个实施例,还包括:固化工艺的温度在大约250度至大约400度的范围内。
根据本发明的一个实施例,在去除第一聚合物层的未固化部分之后,第一聚合物层的固化部分在三个侧面包裹第一金属线和第二金属线。
附图说明
当结合附图阅读时,根据以下详细的描述能够最好地理解本发明的各个方面。注意,根据行业的标准实践,各个部件没有按比例绘制。事实上,为了讨论的清楚,各个部件的尺寸可以任意增加或减小。
图1示出了根据本发明各个实施例的半导体器件的截面图;
图2示出了根据本发明各个实施例的另一半导体器件的截面图;
图3至图17示出了根据本发明各个实施例的制造图1所示半导体器件的中间步骤;
图18示出了根据本发明各个实施例的用于形成图1所示半导体器件的方法的流程图;
图19至图22示出了根据本发明各个实施例的制造图2所示半导体器件的中间步骤;以及
图23示出了根据本发明各个实施例的用于形成图2所示半导体器件200的方法的流程图。
具体实施方式
以下公开提供了许多不同的用于实施本发明主题的不同特征的实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然,这些仅仅是实例而不用于限制。例如,在以下的描述中,在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例,并且也可以包括可以在第一部件和第二部件之间形成附加部件使得第一部件和第二部分没有直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚,其本身并不表示所讨论的各个实施例和/或结构之间的关系。
图1示出了根据本发明各个实施例的半导体器件的截面图。半导体器件100包括形成在衬底102中的晶体管器件150以及形成在衬底102上方的多个互连结构。
衬底102可由硅形成,尽管其还可以由其他III族、IV族和/或V族元素形成,诸如硅、锗、镓、砷和它们的组合。衬底102还可以为绝缘体上硅(SOI)的形式。SOI衬底可包括形成在硅衬底中所形成的绝缘体层(例如,隐埋氧化物等)上方的半导体材料层(例如,硅、锗等)。此外,可使用的其他衬底,包括多层衬底、梯度衬底、混合取向衬底等。
衬底102可进一步包括各种电路,诸如金属氧化物半导体(MOS)晶体管(例如晶体管器件150)和相关的接触插塞(例如接触插塞118)。形成在衬底102上的电路可以为任何类型的适合于特定应用的电路。根据实施例,电路可包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件,诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。电路可以互连以执行一种或多种功能。功能可包括存储结构、处理结构、传感器、放大器、配电、输入/输出电路等。本领域技术人员应该理解,上述实例只是为了示意性的目的,并不将本发明限于任何特定的应用。
如图1所示,晶体管器件150包括第一源极/漏极区域106和第二源极/漏极区域108。第一源极/漏极区域106和第二源极/漏极区域108形成在晶体管器件150的栅极结构的相对侧上。栅极结构形成在介电层112中和衬底102上方。栅极结构可包括栅极介电层113、栅极介电层113上方的栅电极114、以及间隔件116。
栅极介电层113可以为诸如氧化硅、氮氧化硅、氮化硅、氧化物、含氮氧化物、它们的组合等的介电材料。栅极介电层113可具有大于约4的相对介电常数值。这种材料的其他实例包括氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪、任何它们的组合等。在栅极介电层113包括氧化物层的实施例中,栅极介电层113可通过任何适当的沉积工艺来形成,诸如将四乙氧基硅烷(TEOS)和氧用作前体的等离子体增强化学气相沉积(PECVD)处理。根据实施例,栅极介电层113的厚度可以在大约8埃至大约200埃的范围内。
栅电极114可包括导电材料,诸如金属(例如钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如,硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如,氮化钛、氮化钽)、掺杂多晶硅、其他导电材料、它们的组合等。在栅电极114由多晶硅形成的实施例中,栅电极114可通过低压化学气相沉积(LPCVD)将掺杂或非掺杂多晶硅沉积至大约400埃至大约2400埃范围内的厚度来形成。
间隔件116可通过在栅电极114和衬底102上方毯式沉积一个或多个间隔件层(未示出)来形成。间隔件116可包括适当的介电材料,诸如SiN、氮氧化物、SiC、SiON、氧化物等。间隔件116可通过常用的技术来形成,诸如化学气相沉积(CVD)、PECVD、溅射等。
第一和第二源极/漏极区域106和108可在栅极介电层113的相对侧形成在衬底102中。在衬底102是n型衬底的实施例中,第一和第二源极/漏极区域106和108可通过注入适当的p型杂质(诸如硼、镓、铟等)来形成。可选地,在衬底102是p型衬底的实施例中,第一和第二源极/漏极区域106和108可通过注入适当的n型杂质(诸如磷、砷等)来形成。
如图1所示,可以在晶体管器件150的相对侧形成两个隔离区域。隔离区域104可以是浅沟槽隔离(STI)区域。如本领域已知的,STI区域可通过蚀刻衬底102以形成沟槽并且用介电材料填充沟槽来形成。例如,隔离区域104可填充有介电材料,诸如氧化物材料、高密度等离子体(HDP)氧化物等。诸如化学机械抛光(CMP)工艺的平面化工艺可应用于顶面,使得可以去除过量的介电材料。
介电层112形成在衬底102的顶部。介电层112例如可以由低K介电材料形成,诸如氧化硅。介电层112可通过本领域已知的任何适当的方法来形成,诸如旋涂、CVD和PECVD。注意,本领域技术人员应该意识到,虽然图1示出了单个介电层,但介电层112可包括多个介电层。
第一介电层201形成在介电层112上方。在一些实施例中,第一介电层201是第一金属化层207的一部分。如图1所示,在第一金属化层207中可以形成三条金属线202、204和206。每条金属线(例如,金属线202)被基于聚合物的结构(例如,结构222)所环绕。在一些实施例中,基于聚合物的结构222、224和226由聚酰亚胺形成。在可选实施例中,基于聚合物的结构222、224和226由交联环氧树脂形成。
如图1所示,可具有三个基于聚合物的结构222、224和226,每个基于聚合物的结构(例如,结构222)都包括两个侧壁部分和底部。例如,如图1所示,基于聚合物的结构222的底部形成在介电层112和对应的金属线202之间。更具体地,基于聚合物的结构222的底部的底面与介电层112的顶面直接接触。基于聚合物的结构222的底部的顶面与金属线202的底面直接接触。基于聚合物的结构224和226与基于聚合物的结构222类似,因此在这里不再进行详细描述。
在一些实施例中,金属线202、204和206可由适当的金属材料形成,诸如铜、铜合金、铝、银、钨、金、任何它们的组合等。
图1还示出了第一金属化层207包括两个气隙203和205。如图1所示,第一气隙203位于金属线202和204之间。第二气隙205位于金属线204和206之间。下面将参照图14详细描述气隙203和205的形成工艺。
应该注意,虽然图1示出了两个气隙形成在第一金属化层207中,但半导体器件100可以包括任何数量的气隙。为了简化而示出了两个气隙(例如,气隙203和205)。
第二介电层211形成在第一介电层201上方。第二介电层211是第二金属化层210的一部分。如图1所示,在第二金属化层210中可以具有两条金属线212和214。此外,在第二金属化层210中可以形成通孔217。如图1所示,通孔217连接在金属线214和金属线206之间。在一些实施例中,通孔217和金属线214可通过适当的半导体制造工艺来形成,诸如双镶嵌工艺。
虽然图1示出了一个金属化层(例如,第二金属化层210)形成在第一金属化层207的上方,但本领域技术人员应该意识到,更多的金属间介电层(未示出)以及相关的金属线和通孔(未示出)可形成在金属化层210上方。具体地,可以通过介电材料(例如,极低k介电材料)和导电材料(例如,铜)的交替层来形成附加层。
图1还示出了半导体器件100包括蚀刻停止层208、第一阻挡层216和第二阻挡层218。蚀刻停止层208形成在金属线202、204和206上方。在一些实施例中,蚀刻停止层208可用于提供蚀刻选择性。在可选实施例中,蚀刻停止层208可用作阻挡层来防止金属线202、204和206的金属(例如,铜)扩散到周围的介电层(例如,介电层201)。第一阻挡层216形成在金属线212的下方。第一阻挡层216从三个侧面环绕金属线212。阻挡层216防止金属线212的金属扩散到介电层211中。类似地,第二阻挡层218用于防止金属线214和通孔217的金属扩散到介电层211中。
图2示出了根据本发明各个实施例的另一半导体器件的截面图。图2所示的半导体器件200类似于图1所示的半导体器件100,除了介电层213由诸如聚酰亚胺的聚合物形成。由于介电层213是聚合物层,所以图1所示的阻挡层216和218可以省略。图2所示的无阻挡层的结构可以帮助减小通孔217和金属线206之间的界面电阻。下面将参照图19至图22描述半导体器件200的详细形成工艺。
图3至图17示出了根据本发明各个实施例的制造图1所示半导体器件的中间步骤。图3示出了根据本发明各个实施例的介电层的截面图。介电层112可由低K介电材料形成,诸如氟硅酸盐玻璃(FSG)等。介电层112可用作金属间介电层。介电层112可由适当的沉积技术形成,诸如PECVD技术、高密度等离子体化学气相沉积(HDPCVD)等。应该注意,为了清楚从图3中省略了图1所示的半导体器件100的其他部件。
图4示出了根据各个实施例的图3所示半导体器件在介电层上方形成聚合物层之后的截面图。聚合物层302通过适当的半导体制造工艺(诸如旋涂工艺等)沉积在介电层112上方。根据不同的应用和设计需求,聚合物层302的厚度可以相应的进行变化。在一些实施例中,聚合物层302的厚度大于图1所示金属线202、204和206的厚度。
在一些实施例中,聚合物层302由第一聚合物材料形成,诸如具有以下示意性化学式的聚酰胺酸:
在可选实施例中,聚合物层302可由第二聚合物材料形成,诸如具有以下示意性化学式的环氧树脂:
图5示出了根据各个实施例的图4所示半导体器件在聚合物层上方形成抗反射层之后的截面图。抗反射层304用于减少后续光刻图案化工艺期间的反射。抗反射层304是通过适当的沉积工艺(诸如CVD、旋涂等)形成在聚合物层302上方的无氮抗反射层(NFARC)。
图6示出了根据各个实施例的图5所示半导体器件在抗反射层上方形成掩模层之后的截面图。掩模层306可用作后续光刻工艺期间的硬掩模。在整个描述中,掩模层306可以可选地被称为硬掩模层306。
在一些实施例中,硬掩模层306可以为金属硬掩模(MHM)层。硬掩模层306可以由氮化钛(TiN)形成。可选地,硬掩模层306可由其他适当的材料(诸如氮化钽(TaN)等)形成。
硬掩模层306可以通过适当的半导体制造技术(诸如CVD等)形成。硬掩模层306的厚度可以在大约200埃至大约1400埃的范围内。
应该注意,虽然图6示出了单个硬掩模层306,但本领域技术人员应该意识到,还可以进行许多改变、替代和修改。例如,还可以使用多层硬掩模。
图7示出了根据各个实施例的图6所示半导体器件在聚合物层中形成多个开口之后的截面图。根据图1所示金属线202、204和206的位置,在聚合物层302中形成开口702、704和706。开口702、704和706部分地穿过聚合物层302。
开口702、704和706可通过任何适当的半导体图案化技术(诸如蚀刻工艺、激光切除工艺等)来形成。例如,开口702、704和706可通过使用光刻技术来形成,以在半导体器件100上方沉积和图案化光刻胶材料(未示出)。根据图1所示金属线202、204和206的位置和形状露出光刻胶的一部分。诸如各向异性干蚀刻工艺的蚀刻工艺可用于形成部分地穿过聚合物层302延伸的开口702、704和706。开口(例如,开口702)下方的聚合物层的剩余部分的厚度在大约1nm至大约5nm的范围内。
图8示出了根据本发明的各个实施例的图7所示半导体器件在将硬掩模去除工艺施加于半导体器件之后的截面图。可使用例如湿蚀刻工艺、干蚀刻工艺或其他适当的工艺去除图7所示剩余的硬掩模层306。
图9示出了根据各个实施例的图8所示半导体器件在开口中填充导电材料之后的截面图。在一些实施例中,可以在蚀刻开口中形成晶种层(未示出)。晶种层可由铜、镍、金、任何它们的组合等形成。晶种层可通过适当的沉积技术(诸如PVD、CVD等)形成。晶种层的厚度可在大约50埃至大约1000埃的范围内。
此外,晶种层可以与改善晶种层的粘合特性的材料形成合金,使其可用作粘合层。例如,晶种层可与诸如镁或铝的材料形成合金,其将迁移到晶种层和阻挡层之间的界面并增强这两层之间的粘合性。可以在形成晶种层的过程中引入合金材料。合金材料可不多于晶种层的约10%。应该注意,还可以根据不同的应用和设计要求使用诸如阻挡层、粘合层等的其他层。
一旦形成晶种层,就在开口702、704和706中填充导电材料902。导电材料可以为铜,但是还可以是任何适当的导电材料,诸如铜合金、铝、钨、钛、银、任何它们的组合等。导电材料可通过适当的制造技术(诸如无电镀工艺、CVD、电镀等)形成。
应该注意,诸如铜的导电材料被聚合物材料(例如,聚酰胺酸)形成的聚合物层302所环绕。不需要在导电层的下方具有阻挡层,因为铜不能扩散到聚合物材料中。
图10示出了根据本发明各个实施例的图9所示半导体器件在执行平面化工艺以去除过量的导电材料之后的截面图。平面化工艺可通过使用适当的技术(诸如研磨、抛光和/或化学蚀刻、蚀刻和研磨技术的组合)来实施。
根据各个实施例,可通过使用CMP工艺实施平面化工艺。在CMP工艺中,蚀刻材料和研磨材料的组合与半导体器件的顶面接触,并且研磨垫(未示出)用于研磨掉过量的导电材料,直到聚合物层302的顶面与金属线202、204和206的顶面平齐。
图11A示出了根据本发明各个实施例的图10所示半导体器件在选择性热固化工艺施加于聚合物层之后的截面图。在一些实施例中,选择性热固化工艺可用于固化金属线202、204和206周围的聚合物材料。选择性热固化工艺可实施为红外线(IR)固化工艺、紫外线(UV)固化工艺、微波固化工艺、任何它们的组合等。
在一些实施例中,红外线(IR)系统可用于固化金属线202、204和206周围的聚合物材料。IR光的波长在大约0.7um至大约15um的范围内。IR光被导向金属线202、204和206的顶面。在一些实施例中,金属线202、204和206可由铜形成。由于铜的导热率较高(例如,401W/(m.K)),所以金属线202、204和206的温度可迅速增加。另一方面,聚合物层302具有大约0.1W/(m.K)至大约1W/(m.K)范围内的低导热率,所以聚合物层302的温度增加得较慢。这种温度差使得热量如箭头所示从金属线202、204和206传送至它们周围的区域。
从金属线202、204和206传送的热量可以导致热酰亚胺化工艺。在热酰亚胺化工艺期间,金属线202、204和206周围的聚合物材料被转化为聚酰亚胺,其为热稳定聚合物。IR光被施加至金属线202、204和206,直到金属线和介电层112的顶面之间的聚酰胺酸部分被完全转化成聚酰亚胺。
在一些实施例中,IR系统的加热功率在大约10W至大约1000W的范围内。加热时间在大约30秒至大约1小时的范围内。应该注意,加热功率和加热时间的选择依赖于应用需要。两条相邻金属线(例如,金属线202和204)之间的未固化部分将在后续制造步骤中变成气隙。较长的加热时间和/或较高的加热功率将增加固化部分的厚度。结果,会相应地减小未固化部分的厚度。如此,图1所示气隙的宽度可以通过控制固化工艺的加热时间和/或加热功率来调整。以下将参照图12至图14描述气隙的详细形成工艺。
图11B示出了根据本发明各个实施例的图11A所示半导体器件在形成热稳定聚合物层之后的截面图。在热工艺完成之后,聚合物层302被划分为未固化部分和固化部分222、224和226。每个固化部分都包括第一侧壁部分、底部和第二侧壁部分。底部位于对应的金属线的底面和介电层112的顶面之间。侧壁部分和底部从三个侧面包裹金属线(例如金属线202)。在一些实施例中,固化部分(例如固化部分222)的底部的厚度在大约1nm至大约5nm的范围内。侧壁部分(例如,固化部分222)的厚度近似等于底部(例如,固化部分222)的厚度。
在一些实施例中,聚合物层302由聚酰胺酸形成。固化部分222、224和226由具有以下示意性化学式的聚酰亚胺形成:
在一些实施例中,聚合物层302由环氧树脂形成。固化部分222、224和226由具有以下示例性化学式的交联环氧树脂形成:
使环绕对应金属线的固化部分(聚酰亚胺或交联环氧树脂部分)为图11B所示的固化部分的一个优点是高机械强度和良好的热稳定性。此外,图11B所示固化部分的材料(例如,聚酰亚胺或交联环氧树脂)还为金属线202、204和206提供了高粘合强度。
此外,固化部分222、224和226具有低介电常数。由聚酰亚胺形成的固化部分的介电常数在大约2.7至大约3.5的范围内。由交联环氧树脂形成的固化部分的介电常数在大约3.2至大约4.6的范围内。这种低介电常数帮助减小相邻金属线之间的电容耦合。这种减小的电容耦合可帮助改进半导体器件100的可靠性。
使环绕对应金属线的固化部分为图11所示的固化部分的另一个优点是聚酰亚胺部分或交联环氧树脂部分可用作阻挡层。更具体地,在一些实施例中,金属线202、204和206由铜形成。金属线202、204和206的铜不能扩散到固化部分222、224和226中。结果,本文所描述的制造工艺不要求阻挡层形成在金属线202、204和206下方。
图12示出了根据本发明各个实施例的图11B所示半导体器件在清洁工艺施加于聚合物层之后的截面图。图11B所示的未固化聚合物层302可通过使用适当的溶剂来去除。
在一些实施例中,由聚酰胺酸形成的未固化聚合物层302可通过适当的溶剂去除,包括乙酰二甲胺(DMAc)、N-甲基-2-吡咯烷酮(NMP)等。DMAc的分子式为C4H9NO。DMAc的摩尔质量为87.12gmol-1。NMP的分子式为C5H9NO。NMP的摩尔质量为99.13gmol-1.
在一些实施例中,由环氧树脂形成的未固化聚合物层302可通过适当的溶剂去除,包括丙酮、四氢呋喃等。丙酮的分子式为C3H6O。丙酮的摩尔质量为53.08gmol-1。四氢呋喃的分子式为C4H8O。四氢呋喃的摩尔质量为72.11gmol-1。
在清洁工艺完成之后,图11B所示的未固化部分如图12所示被去除。形成两个沟槽1202和1204。第一沟槽1202位于金属线202和204之间。第二沟槽1204位于金属线204和206之间。应该注意,气隙的宽度可调。通过控制未固化部分的宽度,可以相应地调整气隙的宽度。
在传统的基于蚀刻的沟槽形成工艺中,为了形成沟槽,可采用干蚀刻工艺。然而,干蚀刻工艺会引起金属损伤(例如,阻挡损伤),这会影响半导体器件的物理和电特性。使用上述清洁工艺的一个优点在于基于溶剂的清洁工艺不会在沟槽1202和1204的形成过程中引起金属损伤。
图13示出了根据本发明各个实施例的图12所示半导体器件在半导体器件上方形成蚀刻停止层之后的截面图。如图13所示,蚀刻停止层208可形成在半导体器件的露出部分上方。蚀刻停止层208可以为诸如氮化硅、氮氧化硅、碳氧化物、碳化硅、它们的组合、它们的多层的介电材料。在一些实施例中,蚀刻停止层208可使用适当的沉积工艺形成,诸如CVD、PECVD、原子层沉积(ALD)等。蚀刻停止层208的厚度可在大约300埃至大约1500埃的范围内。
图14示出了根据本发明各个实施例的图13所示半导体器件在形成气隙之后的截面图。介电材料1402可通过适当的沉积技术(诸如共形沉积技术)沉积在半导体器件100上方。如图14所示,在介电层1402沉积在半导体器件100上方之后,由于两条相邻金属线之间的开口的高纵横比(即,气隙高度和气隙宽度的比)而形成两个气隙203和205。如图14所示,较窄的气隙宽度会导致气隙上部中形成的突出(overhang)。这种突出会防止介电材料填充开口使得如图14所示形成气隙203和205。
如图14所示,气隙203和205为矩形。应该注意,纯粹为了说明的目的选择图14所示的形状,这不用于限制本发明的各个实施例。例如,在本发明的范围内,气隙203和205可包括其他形状,诸如但不限于椭圆形、正方形、三角形等。
具有图12所示气隙203和205的一个优点在于,气隙203和205中的空气表现出近似等于1的介电常数。这种低介电常数帮助减小相邻金属线(例如,金属线202和204)之间的电容耦合。这种减小的电容耦合可帮助提高可靠性。
图15示出了根据本发明各个实施例的图14所示半导体器件在形成多个开口之后的截面图。根据金属线212和214以及通孔217的位置和形状,在介电层1402中形成开口1502和1504。开口1502和1504可通过双镶嵌工艺形成,尽管也可以可选地使用诸如单镶嵌工艺的其他适当的技术。双镶嵌工艺在本领域是公知的,因此这里不再进行讨论。
应该注意,在形成通孔217的工艺中不存在制造缺陷(诸如穿通问题)。更具体地,环绕金属线206的聚酰亚胺层可防止通孔穿通至气隙205。
图16示出了根据本发明各个实施例的图15所示半导体器件在形成两个阻挡层之后的截面图。阻挡层216和218可沉积在它们对应的开口的侧壁和底部上。阻挡层216和218可由钛、氮化钛、钽、氮化钽和它们的组合等形成。阻挡层216和218可使用适当的制造技术(诸如ALD、PECVD等)形成。
图17示出了根据本发明各个实施例的图16所示半导体器件在开口中填充导电材料之后的截面图。然后在开口1306和1604中填充导电材料。导电材料可以为铜,但是也可以为任何适当的导电材料,诸如铜合金、铝、钨、钛、银、任何它们的组合等。导电材料可通过适当的制造技术形成,诸如无电镀工艺、CVD、电镀等。
执行平面化工艺以去除过量的导电材料,从而形成金属线212和214。可通过使用适当的技术来实施平面化工艺,诸如研磨、抛光和/或化学蚀刻、蚀刻和研磨技术的组合。
图18示出了根据本发明各个实施例的用于形成图1所示半导体器件的方法的流程图。该流程图仅仅是实例,而不应限制权利要求的范围。本领域技术人员应该意识到许多变化、替代和修改。例如,可以添加、去除、替换、再配置和重复图18所示的各个步骤。
在步骤1802中,在介电层上沉积聚合物层。聚合物层可由适当的材料形成,诸如聚酰胺酸、环氧树脂等。在步骤1804中,在聚合物层上方形成硬掩模层。在步骤1806中,对聚合物层施加图案化工艺。在步骤1808中,使用适当的蚀刻工艺以形成部分穿过聚合物层的多个开口。在步骤1812中,在开口中填充导电材料以形成多条金属线。在步骤1814中,向金属线施加固化工艺。结果,环绕金属线的聚合物部分被固化以形成聚酰亚胺或交联环氧树脂区域。
在步骤1816中,使用清洁工艺以去除聚合物层的未固化部分。在步骤1818中,在金属线上方形成蚀刻停止层。在步骤1822中,在金属线上方沉积第二介电层。在相邻的金属线之间形成气隙。在步骤1824中,在第二介电层中形成多个开口。在步骤1826中,在开口中填充导电材料以在第二介电层中形成多条金属线。
图19至图22示出了根据本发明各个实施例的制造图2所示半导体器件的中间步骤。图19所示用于制造半导体器件200的步骤类似于图3至图12所示的步骤,因此为了避免不必要的重复不再进行详细的讨论。
图20示出了根据本发明各个实施例的图19所示半导体器件在半导体器件上方形成聚合物层之后的截面图。聚合物层213由聚酰胺酸、环氧树脂等形成。聚酰胺酸和环氧树脂的形成和结构已经参照图4进行过描述,因此为了避免重复不再进行讨论。图20所示气隙203和205的形成工艺类似于图14所示,因此不再进行讨论。
在沉积聚合物层之后,使用固化工艺来固化聚合物层213。在固化工艺期间,在热室中烘烤半导体器件200。固化时间在大约2分钟至大约4分钟的范围内。固化温度在大约250度至大约400度的范围内。在固化工艺完成之后,由聚酰胺酸形成的聚合物层213被转化成完全固化的聚酰亚胺层。
图21示出了根据本发明各个实施例的图20所示半导体器件在形成多个开口之后的截面图。根据金属线212和214以及通孔217的位置和形状,在聚合物层213中形成开口2102和2104。开口2102和2104可通过双镶嵌工艺形成,尽管还可以可选地使用诸如单镶嵌的其他适当的技术。
图22示出了根据本发明各个实施例的图21所示半导体器件在开口中填充导电材料之后的截面图。在开口2102和2104中填充导电材料。导电材料可以为铜,但是还可以为任何适当的导电材料,诸如铜合金、铝、钨、钛、银、任何它们的组合等。可通过适当的制造技术形成导电材料,诸如无电镀工艺、CVD、电镀等。
根据本发明的各个实施例,执行平面化工艺以去除过量的导电材料。平面化工艺可通过使用适当的技术来实施,诸如研磨、抛光和/或化学蚀刻、蚀刻和研磨技术的组合。
应该注意,诸如铜的导电材料可直接填充在开口中而不具有阻挡层。诸如铜的导电材料不能够扩散到聚合物层213中。结果,阻挡层不形成在开口中。图22所示这种无阻挡层的结构帮助减小通孔217和金属线206之间的电阻。
图23示出了根据本发明各个实施例的用于形成图2所示半导体器件200的方法的流程图。该流程图仅仅是实例,而不应限制权利要求的范围。本领域技术人员应该意识到许多变化、替代和修改。例如,可以添加、去除、替换、再配置和重复图23所示的各个步骤。
图23所示的步骤2302至2316与图18所示的步骤1802至1816类似,因此为了避免重复不再进行讨论。在步骤2318中,在半导体器件上方沉积聚合物层。在相邻的金属线之间形成气隙。在步骤2322中,将固化工艺施加于聚合物层。聚合物材料被转化成热稳定聚合物。在步骤2324中,在热稳定聚合物层中形成多个开口。在步骤2326中,在开口中填充导电材料以形成金属线和通孔。
根据一个实施例,一种装置包括:第一导电线,位于介电层上方的第一金属层中,其中,第一导电线在三个侧面被第一聚合物层包裹,并且所述第一导电线和介电层通过第一聚合物层的底部隔离;第二导电线,位于介电层上方,其中,第二导电线在三个侧面被第二聚合物层包裹,并且第二导电线和介电层被第二聚合物层的底部隔离;以及气隙,位于第一导电线和第二导电线之间。
根据本发明的一个实施例,一种器件包括:第一金属化层,位于介电层上方,第一金属化层包括在三个侧面被第一聚合物层包裹的第一金属线和与第一金属线相邻的气隙,气隙和第一金属线被第一聚合物层的侧壁隔离。
该器件还包括第二金属化层,位于第一金属化层上方,其中,第一金属线的顶面与第二金属化层的底面直接接触,并且第一金属线的底面和介电层通过第一聚合物层的底部隔开。
根据一个实施例,一种方法,包括:在介电层上方沉积第一聚合物层;使用蚀刻工艺形成第一开口和第二开口,第一开口和第二开口部分地穿过第一聚合物层;用导电材料填充第一开口和第二开口,以形成第一金属线和第二金属线;对第一聚合物层施加选择性热固化工艺,直到第一聚合物层环绕第一金属线和第二金属线的部分被固化;通过清洁工艺去除第一聚合物层的未固化部分;以及沉积介电层以在第一金属线和第二金属线之间形成气隙。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以容易地以本公开为基础设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到,这些等效结构不背离本发明的精神和范围,并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。
Claims (10)
1.一种装置,包括:
第一导电线,位于介电层上方的第一金属层中,其中:
所述第一导电线在三个侧面被第一聚合物层包裹;并且
所述第一导电线和所述介电层通过所述第一聚合物层的底部隔离;
第二导电线,位于所述介电层上方,其中:
所述第二导电线在三个侧面被第二聚合物层包裹;并且
所述第二导电线和所述介电层被所述第二聚合物层的底部隔离;以及
气隙,位于所述第一导电线和所述第二导电线之间。
2.根据权利要求1所述的装置,其中,
所述第一聚合物层和所述第二聚合物层包括聚酰亚胺。
3.根据权利要求1所述的装置,其中,
所述第一聚合物层和所述第二聚合物层包括交联环氧树脂。
4.根据权利要求1所述的装置,其中,
所述第一聚合物层包括第一侧壁、第二侧壁和第一底部,所述第一导电线在三个侧面被所述第一侧壁、所述第二侧壁和所述第一底部包裹;并且
所述第二聚合物层包括第三侧壁、第四侧壁和第二底部,所述第二导电线在三个侧面被所述第三侧壁、所述第四侧壁和所述第二底部包裹。
5.根据权利要求4所述的装置,其中,
所述气隙位于所述第一聚合物层的所述第二侧壁和所述第二聚合物层的所述第三侧壁之间。
6.根据权利要求1所述的装置,还包括:
第二金属化层,位于所述第一金属化层上方,所述气隙位于所述第二金属化层和所述介电层之间。
7.一种器件,包括:
第一金属化层,位于介电层上方,所述第一金属化层包括:
第一金属线,在三个侧面被第一聚合物层包裹;和
气隙,与所述第一金属线相邻,所述气隙和所述第一金属线被所述第一聚合物层的侧壁隔离;以及
第二金属化层,位于所述第一金属化层上方,其中:
所述第一金属线的顶面与所述第二金属化层的底面直接接触;并且
所述第一金属线的底面和所述介电层通过所述第一聚合物层的底部隔开。
8.根据权利要求7所述的器件,其中,
所述第一聚合物层的底部的厚度在大约1nm至大约5nm的范围内。
9.一种方法,包括:
在介电层上方沉积第一聚合物层;
使用蚀刻工艺形成第一开口和第二开口,所述第一开口和所述第二开口部分地穿过所述第一聚合物层;
用导电材料填充所述第一开口和所述第二开口,以形成第一金属线和第二金属线;
对所述第一聚合物层施加选择性热固化工艺,直到所述第一聚合物层环绕所述第一金属线和所述第二金属线的部分被固化;
通过清洁工艺去除所述第一聚合物层的未固化部分;以及
沉积介电层以在所述第一金属线和所述第二金属线之间形成气隙。
10.根据权利要求9所述的方法,还包括:
将热源引导至所述第一金属线和所述第二金属线上;
固化所述第一聚合物层直到环绕所述第一金属线和所述第二金属线的区域中的聚酰胺酸转化为聚酰亚胺。
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Also Published As
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US20160172232A1 (en) | 2016-06-16 |
US9269668B2 (en) | 2016-02-23 |
CN105280616B (zh) | 2019-02-05 |
US9496170B2 (en) | 2016-11-15 |
US20160020176A1 (en) | 2016-01-21 |
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