TWI509765B - 互連結構及方法 - Google Patents

互連結構及方法 Download PDF

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TWI509765B
TWI509765B TW102135536A TW102135536A TWI509765B TW I509765 B TWI509765 B TW I509765B TW 102135536 A TW102135536 A TW 102135536A TW 102135536 A TW102135536 A TW 102135536A TW I509765 B TWI509765 B TW I509765B
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Taiwan
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substrate
hard mask
wafer
layer
mask layer
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TW102135536A
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TW201436153A (zh
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Shuting Tsai
Dunnian Yaung
Chenjong Wang
Jencheng Liu
Fengchi Hung
Tzuhsuan Hsu
Uting Chen
Jengshyan Lin
Shuangji Tsai
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Taiwan Semiconductor Mfg Co Ltd
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Description

互連結構及方法
本申請案係關於一種互連結構及方法。
由於在各種電子元件(例如，電晶體、二極體、電阻器、電容器等)在積集密度上的不斷改良，半導體工業正在經歷快速的成長。積集密度的改良大部分係來自最小特徵尺寸上的重複縮減(例如，將半導體製程世代節點朝低於20nm節點微縮)，此舉允許將更多元件積集至一給定區域內。因為對於微縮化、更高速度及更大帶寬以及更低功率消耗及等待時間之需求增長，對於半導體晶片(die)之更小及更有創造力之封裝技術的需要也隨之增長。
隨著半導體技術進一步推進，堆疊半導體裝置應運而生成為一有交的替代方案以進一步縮小半導體裝置之實體尺寸。在堆疊半導體裝置中，諸如邏輯電路、記憶體電路、處理器電路等有源電路係製造於不同的半導體晶圓上。可將兩個或兩個以上半導體晶圓安裝為一個晶圓在另一個晶圓頂部以進一步降低半導體裝置之形式因子(form factor)。
兩個半導體晶圓可經由適當的接合技術彼此接合在一起。常用接合技術包括直接接合、化學活化接合、電漿活化接合、陽極接合、共晶接合、玻璃粉接合、黏著劑接合、 熱壓縮接合、反應性接合及/或類似接合。一旦將兩個半導體晶圓接合在一起，介於兩個半導體晶圓之間的介面就可在堆疊半導體晶圓之間提供導電路徑。
堆疊半導體裝置的一個優點在於藉由使用堆疊半導體裝置可達成更高的密度。此外，堆疊半導體裝置可達到更小的形式因子、更高的成本效益、增強的效能及較低的功率消耗。
本發明的一個態樣係關於一種設備，包含：一第一半導體晶片，包括一第一基板及形成於該第一基板上之複數個第一金屬接線；一第二半導體晶片，接合於該第一半導體晶片上，其中該第二半導體晶片包含一第二基板及形成於該第二基板上之複數個第二金屬接線；以及一導電插塞，耦接在該等第一金屬接線與該等第二金屬接線之間，其中該導電插塞包含：一第一部分，形成於一硬遮罩層之一第一側上，其中該第一部分具有一第一寬度；以及一第二部分，形成於該硬遮罩層之一第二側上，其中該第二部分具有一第二寬度，該第二寬度大於或等於該第一寬度。
本發明的另一態樣係關於一種裝置，包含：一第一晶片，包含：一第一基板；以及複數個第一互連元件，形成於第一金屬間介電層內且在該第一基板上；一第二晶片，接合於該第一晶片上，其中該第二晶片包含：一第二基板；以及複數個第二互連元件，形成於第二金屬間介電層內且在該第二基板上；以及一導電插塞，經由該第一基板及該等第一金屬間介電層而形成且經由該等第二金屬間介電層而局部 形成，其中該導電插塞係耦接在該等第一互連元件與該等第二互連元件之間。
本發明的又一態樣係關於一種方法，包含：將一第一半導體晶圓接合於一第二半導體晶圓上，其中：該第一半導體晶圓包含一第一基板、第一金屬間介電層及第一互連結構，該等第一互連結構形成於該等第一金屬間介電層內且在該第一基板上；以及該第二半導體晶圓包含一第二基板、第二金屬間介電層及第二互連結構，該等第二互連結構形成於該等第二金屬間介電層內且在該第二基板上；圖案化該第一基板以在該第一基板內形成一第一開口；使用一蝕刻製程及使用作為一硬遮罩層之該等第一互連結構形成一第二開口，其中該第二開口係經由該等第一金屬間介電層且局部經由該等第二金屬間介電層而形成；以及在該第一開口及該第二開口內電鍍一導電材料。
100‧‧‧堆疊半導體裝置
102‧‧‧第一基板
104‧‧‧金屬間介電層
106‧‧‧金屬接線
108‧‧‧金屬接線
110‧‧‧第一半導體晶圓
112‧‧‧BARC層
114‧‧‧開口
116‧‧‧開口
202‧‧‧第二基板
1004‧‧‧導電插塞
1006‧‧‧接觸面
1008‧‧‧接觸面
1100‧‧‧堆疊半導體裝置
1102‧‧‧導電插塞
1103‧‧‧三維結構
1104‧‧‧導電插塞
1106‧‧‧再分配金屬接線
1108‧‧‧再分配金屬接線
1110‧‧‧成像感測器
204‧‧‧金屬間介電層
206‧‧‧金屬接線
208‧‧‧金屬接線
210‧‧‧第二半導體晶圓
302‧‧‧介電層
402‧‧‧圖案化遮罩
404‧‧‧開口
406‧‧‧開口
502‧‧‧凹陷
504‧‧‧開口
506‧‧‧開口
702‧‧‧導電插塞
704‧‧‧導電插塞
710‧‧‧阻障層
802‧‧‧導電插塞
804‧‧‧導電插塞
902‧‧‧介電層
904‧‧‧三維結構
1000‧‧‧堆疊半導體裝置
1002‧‧‧導電插塞
1003‧‧‧三維結構
1112‧‧‧鋁銅墊
1114‧‧‧鋁銅墊
1120‧‧‧金屬接線
1122‧‧‧金屬接線
1124‧‧‧金屬接線
1126‧‧‧金屬接線
1200‧‧‧背光圖像感測器
1201‧‧‧感測器晶圓
1203‧‧‧ASIC晶圓
1206‧‧‧邏輯電路
1208‧‧‧邏輯電路
1210‧‧‧三維結構
1220‧‧‧金屬接線
1222‧‧‧金屬接線
1224‧‧‧金屬接線
1226‧‧‧金屬接線
1302‧‧‧頂視圖
1304‧‧‧頂視圖
1402‧‧‧頂視圖
1404‧‧‧頂視圖
W1/W2/W3‧‧‧寬度
為了更加全面瞭解本發明及本發明之優勢，現在對結合隨附圖式考慮之下列描述進行參考，在不同圖式中之對應數字及符號通常係指對應元件，除非另有陳述。繪製圖式以清楚圖示各種實施例之相關態樣且圖式不必按比例繪製。在該等隨附圖式中：第1圖圖示根據本發明之各種實施例在接合製程之前的堆疊半導體裝置的剖面視圖；第2圖圖示根據本發明之各種實施例，第1圖中圖示之半導體裝置在將底部抗反射塗層(BARC)形成於第一半導體晶圓上且將圖案化製程應用於第一半導體晶圓之基板之後的剖 面視圖；第3圖圖示根據本發明之各種實施例，第2圖中圖示之半導體裝置在將介電層沉積於半導體裝置上之後的剖面視圖；第4圖圖示根據本發明之各種實施例，第3圖中圖示之半導體裝置在將遮罩層形成於半導體裝置上之後的剖面視圖；第5圖圖示根據本發明之各種實施例，第4圖中圖示之半導體裝置在將蝕刻製程應用於半導體裝置之後的剖面視圖；第6圖圖示根據本發明之各種實施例，第5圖中圖示之半導體裝置在已將剩餘光阻層移除之後的剖面視圖；第7圖圖示根據本發明之各種實施例，第6圖中圖示之半導體裝置在已將導電材料填充於開口中之後的剖面視圖；第8圖圖示根據本發明之各種實施例，第7圖中圖示之半導體裝置在將化學機械研磨(CMP)製程應用於半導體裝置之頂部表面之後的剖面視圖；第9圖圖示根據本發明之各種實施例，第8圖中圖示之半導體裝置在將介電層形成於半導體裝置上之後的剖面視圖；第10圖圖示根據本發明之各種實施例之另一堆疊半導體裝置的剖面視圖；第11圖圖示根據本發明之各種實施例之又一堆疊半導體裝置的剖面視圖；第12圖圖示根據本發明之各種實施例之包括堆疊晶圓結 構之背光成像感測器的剖面視圖；第13圖圖示根據本發明之各種實施例之硬遮罩的頂視圖；及第14圖圖示根據本發明之各種實施例之硬遮罩的另一頂視圖。
下文詳細論述目前較佳實施例之製造及使用。然而，應瞭解，本發明提供可在各式各樣的特定上下文中實施之許多可適用的發明概念。所論述之特定實施例僅說明製造及使用本發明之特定方式，且不限制本發明之範疇。
本發明將相對於特定上下文中之較佳實施例描述用於為堆疊半導體裝置形成互連結構之方法。然而，亦可將本發明應用於各種半導體裝置。在下文中，將參閱隨附圖式詳細說明各種實施例。
根據本發明之各種實施例，第1圖圖示在接合製程之前的堆疊半導體裝置之剖面視圖。第一半導體晶圓110及第二半導體晶圓210兩者皆包括半導體基板(例如，第一基板102及第二基板202)及形成於半導體基板上之複數個互連結構(例如，金屬接線106、金屬接線108、金屬接線206及金屬接線208)。第一半導體晶圓110係用作圖示在接合製程之前的半導體晶圓的詳細結構之實例。
如第1圖所示，第一半導體晶圓110可包含第一基板102及形成於第一基板102上之複數個金屬間介電層104。另外，諸如金屬接線106及金屬接線108之複數個金屬接線係形成在金屬間介電層104中。
第一基板102可由矽形成，儘管此第一基板102亦可由其他III族、IV族及/或V族元素形成，諸如矽、鍺、鎵、砷及前述各者之組合。第一基板102亦可以絕緣層上矽(silicon-on-insulator；SOI)的形式。SOI基板可包含形成於絕緣體層(例如，埋藏氧化層及/或類似層)上之一層半導體材料(例如，矽、鍺及/或類似物)，此絕緣體層係形成在矽基板中。另外，可使用之其他基板包括多層狀基板、梯度基板、混合定向基板、前述各者之任何組合及/或類似物。
第一基板102可進一步包含各種電路(未圖示)。形成於第一基板102上之電路可為適合於特定應用之任何類型的電路系統。根據一些實施例，電路可包括各種n型金屬氧化物半導體(n-type metal-oxide semiconductor；NMOS)裝置及/或p型金屬氧化物半導體(p-type metal-oxide semiconductor；PMOS)裝置，諸如電晶體、電容器、電阻器、二極體、光二極體、保險絲及/或類似物。
可將電路互連以執行一或多個功能。功能可包括記憶體結構、處理結構、感測器、放大器、功率分配、輸入/輸出電路系統及/或類似功能。一般技術者將瞭解，提供上述實例僅用於說明性目的且上述實例不意欲將各種實施例限於任何特定應用。
金屬間介電層104係形成於第一基板102上。如第1圖所示，金屬間介電層104可包含複數個金屬接線，諸如金屬接線106及金屬接線108。
金屬接線106及金屬接線108可經由任何適當的形成製程(例如，利用蝕刻之微影術、鑲嵌法、雙重金屬鑲 嵌法或類似製程)製得且金屬接線106及金屬接線108可使用適當的導電材料形成，該等導電材料諸如銅、鋁、鋁合金、銅合金或類似物。
如第1圖所示，第一半導體晶圓110將堆疊於第二半導體晶圓210之頂部上。在一些實施例中，複數個接合墊係分別形成在第一半導體晶圓110及第二半導體晶圓210中。此外，位於第二半導體晶圓210之接合墊與位於第一半導體晶圓110之此等接合墊之對應接合墊面對面對準。第一半導體晶圓110與第二半導體晶圓210係經由適當的接合技術接合在一起，該接合技術諸如直接接合。
根據一些實施例，在直接接合製程中，介於第一半導體晶圓110與第二半導體晶圓210之間的連接可經由以下各者實施：金屬與金屬接合(例如，銅與銅接合)、介電質與介電質接合(例如，氧化物與氧化物接合)、金屬與介電質接合(例如，氧化物與銅接合)、前述各接合之任何組合及/或類似接合。
根據本發明之各種實施例，第2圖圖示第1圖中圖示之半導體裝置在將底部抗反射塗層(bottom anti-reflection coating；BARC)形成於第一半導體晶圓上且將圖案化製程應用於第一半導體晶圓之基板之後的剖面視圖。BARC層112係形成於第一基板102之背側上。在整個描述中，第一基板102鄰近於BARC層112之側被稱為第一基板102之背側。
BARC層112可由氮化物材料、有機材料、氧化物材料及類似材料形成。BARC層112可使用適當的技術形成， 諸如化學氣相沉積(CVD)及/或類似技術。
可使用適當的沉積及光微影技術將諸如光阻遮罩及/或類似物之圖案化遮罩形成於BARC層112上。可將適當的蝕刻製程，諸如反應性離子蝕刻(reactive ion etch；RIE)或其他乾燥蝕刻、各向異性濕蝕刻或任何其他適當的各向異性蝕刻，或圖案化製程，應用於第一半導體晶圓110之第一基板102。因此，複數個開口114及116係形成在第一基板102中。
根據本發明之各種實施例，第3圖圖示第2圖圖示之半導體裝置在將介電層沉積於半導體裝置上之後的剖面視圖。如第3圖所示，介電層302係形成於開口114及開口116之底部及側壁上。另外，介電層302係形成於BARC層112上。
介電層302可由常用於積體電路製造中之各種介電材料形成。舉例而言，介電層302可由二氧化矽、氮化矽或諸如硼矽玻璃之摻雜玻璃層及類似物形成。或者，介電層可為一層氮化矽、氧氮化矽層、聚醯胺層、低介電常數絕緣層或類似物。另外，前述介電材料之組合亦可用來形成介電層302。根據一些實施例，介電層302可使用適當的技術來形成，該等技術諸如濺射、氧化、CVD及/或類似技術。
根據本發明之各種實施例，第4圖圖示第3圖中圖示之半導體裝置在將遮罩層形成於半導體裝置上之後的剖面視圖。圖案化遮罩402係形成於開口114及開口116之側壁上(第3圖中圖示)。如第4圖所示，兩個新開口404及406係在沿著開口114及開口116之側壁形成圖案化遮罩402之 後形成。
圖案化遮罩402可為光阻層。圖案化遮罩402係使用適當的沉積及光微影技術而形成於半導體裝置之頂部表面上。
根據本發明之各種實施例，第5圖圖示第4圖中圖示之半導體裝置在將蝕刻製程應用於半導體裝置之後的剖面視圖。可執行適當的蝕刻製程，諸如乾燥蝕刻、各向異性濕蝕刻或任何其他適當的各向異性蝕刻，或圖案化製程以形成開口504及開口506。開口504及開口506為開口404及開口406之各自延伸。詳言之，開口504及開口506延伸通過金屬間介電層104及204以及兩個堆疊晶圓之接合介面。如第5圖所示，金屬接線106、金屬接線108、金屬接線206及金屬接線208係暴露在已形成開口504及開口506之後。
應注意，金屬接線106及金屬接線108係由諸如銅之適當金屬材料形成，此材料具有與第一基板102及金屬間介電層不同的蝕刻速度(選擇性)。因而，金屬接線106及金屬接線108可充當硬遮罩層用於金屬間介電層104及204之蝕刻製程。可使用選擇性蝕刻製程以快速蝕刻金屬間介電層104及204，而僅蝕刻部分之金屬接線106及金屬接線108。如第5圖所示，將硬遮罩層(例如，金屬接線106及金屬接線108)之暴露部分局部地蝕刻掉，從而形成諸如凹陷502之凹陷。凹陷502之深度可取決於不同應用及設計需要而變化。
根據本發明之各種實施例，第6圖圖示第5圖中圖示之半導體裝置在已將剩餘光阻層移除之後的剖面視圖。 第5圖中圖示之剩餘光阻層可藉由使用適當的光阻剝離技術來移除，該等技術諸如化學溶劑清洗、電漿灰化、乾燥剝離及/或類似技術。光阻剝離技術是眾所熟知的且因此在本文不進一步詳細論述以避免重複。
根據本發明之各種實施例，第7圖圖示第6圖中圖示之半導體裝置在已將導電材料填充於開口中之後的剖面視圖。在一些實施例中，可將阻障層及晶種層在電鍍製程之前沉積，導電材料係經由此電鍍製程而填充至開口內。
可將阻障層710沉積於開口(例如，第6圖中圖示之開口404)之底部以及側壁上。阻障層710可由鈦、氮化鈦、鉭、氮化鉭及前述各者之組合及/或類似物形成。在一些實施例中，阻障層710可為厚度均勻的。在替代實施例中，阻障層710可為厚度不均勻的。阻障層710可使用適當的製造技術而形成，諸如原子層沉積(ALD)、電漿增強CVD(PECVD)、電漿增強物理氣相沉積(PEPVD)及/或類似製造技術。
另外，可將晶種層(未圖示)沉積於阻障層710上。晶種層可由銅、鎳、金、前述各者之任何組合及/或類似物形成。晶種層可藉由適當的沉積技術形成，該等技術諸如PVD、CVD及/或類似技術。
此外，晶種層可與改良晶種層之黏著劑性質之材料熔接，以便此晶種層可充當黏著層。舉例而言，晶種層可與諸如錳或鋁之材料熔接，該材料將遷移至介於晶種層與阻障層710之間的介面且該材料將增強介於此等兩個層之間的黏著。可在形成晶種層期間引入熔接材料。熔接材料可包含 晶種層之僅僅約10%。
一旦已將阻障層710及晶種層沉積在開口中，就將導電材料填充至開口內以形成導電插塞702及導電插塞704，此導電材料包括鎢、鈦、鋁、銅、前述各者之任何組合及/或類似物。在一些實施例中，可經由電鍍製程將導電材料填充在開口中。
根據本發明之各種實施例，第8圖圖示第7圖中圖示之半導體裝置在將化學機械研磨(CMP)製程應用於半導體裝置之頂部表面之後的剖面視圖。可執行諸如CMP、回蝕刻步驟及類似物之平坦化製程以平坦化半導體裝置之頂部表面。如第8圖所示，部分導電材料已作為結果而移除。如第8圖所示，在於半導體裝置上執行CMP製程之後可能存在形成於半導體裝置中之兩個導電插塞802及804。
如第8圖所示，每一導電插塞(例如，導電插塞802及導電插塞804)可包含三個部分。第一部分係自金屬接線206至藉由金屬接線106及金屬接線108形成之硬遮罩層。第一部分具有寬度W1，如第8圖所示。第二部分係自硬遮罩層至第一基板102之前側。第二部分具有寬度W2，如第8圖所示。第三部分係自第一基板102之背側至第一基板102之背側。第三部分具有寬度W3，如第8圖所示。在一些實施例中，W2係大於或等於W1。W3係大於W2。
根據本發明之各種實施例，第9圖圖示第8圖中圖示之半導體裝置在將介電層形成於半導體裝置上之後的剖面視圖。介電層902可包含常用的介電材料，諸如氮化矽、氧氮化矽、碳氧化矽、碳化矽、前述各者之組合及多層之前 述各者。可經由適當的沉積技術將介電層902沉積於半導體裝置上，該等技術諸如濺射、CVD及類似物。
導電插塞(例如，導電插塞802)包括三個部分，如上根據第8圖所述。在整個描述中可將自硬遮罩層(例如，金屬接線106)至金屬接線206之部分替代地稱為三維結構904。
具有第9圖所示之導電插塞802及導電插塞804之堆疊晶圓之一優點在於，兩個半導體晶圓之有源電路係經由單個導電插塞(例如，導電插塞802)而連接至彼此。此單個導電插塞幫助進一步縮減形式因子。此外，與藉由多個導電插塞連接之堆疊半導體裝置相比，耦接在第9圖中圖示之兩個半導體晶圓之間的單個導電插塞幫助削減功率消耗及防止寄生干擾。
應注意，儘管第9圖圖示堆疊在一起之兩個半導體晶圓，但熟習此項技術者將認識到，第9圖中圖示之堆疊半導體裝置僅為實例。可存在許多替代選擇、變化及修改。舉例而言，堆疊半導體裝置可容納多於兩個半導體晶圓。
根據本發明之各種實施例，第10圖圖示另一堆疊半導體裝置之剖面視圖。堆疊半導體裝置1000係類似於第9圖中圖示之堆疊半導體裝置100，不同之處在於硬遮罩層係藉由接觸面而形成，此硬遮罩層係鄰近於介於第一基板102與金屬間介電層104之間的介面而定位。
接觸面可形成於層間介電層中(未圖示)。層間介電層可包含諸如硼磷矽酸鹽玻璃(boron phosphorous silicate glass；BPSG)之材料，儘管任何適當的介電質可用於任一層。 層間介電層可使用諸如PECVD之製程而形成，儘管可替代地使用其他製程。
接觸面1006及接觸面1008可以適當的光微影及蝕刻技術經由層間介電層而形成。通常，此等光微影技術涉及沉積光阻材料，此光阻材料經遮罩、暴露及顯影而暴露待移除之層間介電層之部分。剩餘光阻材料保護下層材料免受諸如蝕刻之後續處理步驟之影響。
接觸面1006及接觸面1008可包含阻障/黏著層(未圖示)以防止擴散且為接觸面1006及接觸面1008提供較佳黏著。在一些實施例中，接觸面1006及接觸面1008可由任何適當的導電材料形成，諸如高導電、低電阻的金屬、基本金屬、過渡金屬或類似物。根據實施例，接觸面1006及接觸面1008係由鎢形成，儘管可替代地利用其他材料，諸如銅、鋁及/或類似材料。在其中接觸面1006及接觸面1008係由鎢形成之實施例中，接觸面1006及接觸面1008可藉由此項技術中所熟知的CVD技術而沉積，儘管可替代地使用任何形成方法。
如第11圖所示，導電插塞(例如，導電插塞1002及1004)包括三個部分。在整個描述中可將自硬遮罩層(例如，接觸面1006)至金屬接線206之部分替代地稱為三維結構1003。
圖示根據本發明之各種實施例第11圖之又一堆疊半導體裝置之剖面視圖。堆疊半導體裝置1100係類似於第9圖中圖示之堆疊半導體裝置100，不同之處在於蝕刻硬遮罩係藉由再分配層而形成，此等再分配層係鄰近於兩個半導體晶 圓之介面而定位。
再分配金屬接線1106及1108可為單一材料層或多層狀結構且可由諸如鈦、氮化鈦、鋁、鉭、銅及前述各者之組合的金屬製得。再分配金屬接線1106及1108可藉由此項技術中所熟知的任何適當方法來製得，該方法諸如物理氣相沉積(PVD)、濺射、CVD、電鍍及/或類似方法。
導電插塞(例如，導電插塞1102及1104)包括三個部分。在整個描述中可將自硬遮罩層(例如，再分配金屬接線1106及1108)至金屬接線206之部分替代地稱為三維結構1103。
應注意，可經由適當的金屬介電質接合技術將第一半導體晶圓110接合於第二半導體晶圓210上，該技術諸如銅氮氧化矽(Cu-SiON)接合製程。
應進一步注意，儘管第9圖、第10圖及第11圖圖示分別藉由金屬接線、接觸面及再分配接線形成之硬遮罩層，但熟習此項技術者將認識到，在第9圖至第11圖中圖示之硬遮罩層僅為實例。可存在許多替代選擇、變化及修改。舉例而言，硬遮罩層可藉由複數個隔離區、多晶矽區、前述各者之任何組合及/或類似物形成。
第12圖圖示根據本發明之各種實施例之包括堆疊晶圓結構的背光成像感測器的剖面視圖。背光圖像感測器1200包含兩個半導體晶圓，即感測器晶圓1201及特定應用積體電路(application-specific integrated circuit；ASIC)晶圓1203。如第12圖所示，感測器晶圓1201係堆疊於ASIC晶圓1203之頂部上。在一些實施例中，感測器晶圓1201及ASIC 晶圓1203係經由適當的三維結構而連接至彼此，該三維結構諸如第9圖中圖示之三維結構904、第10圖中圖示之三維結構1003、第11圖中圖示之三維結構1103及前述各者之任何組合。
ASIC晶圓1203可包含複數個邏輯電路，諸如邏輯電路1206及邏輯電路1208。在一些實施例中，邏輯電路可為類比至數位轉換器。然而，邏輯電路可為可在背光圖像感測器內利用之其他功能電路。舉例而言，邏輯電路1206及1208可為資料處理電路、記憶體電路、偏壓電路、參考電路、前述各者之任何組合及/或類似物。
ASIC晶圓1203可進一步包含複數個互連層及經嵌入此等互連層中之複數個金屬接線1220、1222、1224及1226。金屬接線1220、金屬接線1222、金屬接線1224及金屬接線1226可充當互連結構。如藉由第12圖中圖示之箭頭所指示，金屬接線1220、金屬接線1222、金屬接線1224及金屬接線1226提供介於邏輯電路1206及1208與感測器晶圓1201之間的訊號路徑。
金屬接線1220、金屬接線1222、金屬接線1224及金屬接線1226可經由任何適當的形成製程(例如，利用蝕刻之微影術、鑲嵌法、雙重金屬鑲嵌法或類似製程)製得且該等金屬接線可使用適當的導電材料形成，該等導電材料諸如銅、鋁、鋁合金、銅合金或類似物。
感測器晶圓1201係藉由在此項技術中熟知的CMOS製程技術而製造。詳言之，感測器晶圓1201包含在矽基板上之磊晶層。根據背光圖像感測器之製造製程，在背側 薄化製程中已移除矽基板直至暴露磊晶層。部分之磊晶層可保留。p型光有效區及n型光有效區(未分別圖示)係形成在剩餘磊晶層中。
諸如p型光有效區及n型光有效區之光有效區可形成PN接合，此PN接合充當光電二極體。如第12圖所示，成像感測器1110可包含複數個光電二極體。
感測器晶圓1201可包含電晶體(未圖示)。詳言之，電晶體可產生與照射於光有效區之光的強度或亮度有關之訊號。根據實施例，電晶體可為轉移電晶體。然而，電晶體可為可在背光圖像感測器內利用之許多類型之功能電晶體之實例。舉例而言，電晶體可包括定位在背光圖像感測器內之其他電晶體，諸如重置電晶體、源極隨耦器電晶體或選擇電晶體。可在圖像感測器內利用之所有適當電晶體及設置全部意欲包括於實施例之範疇內。
感測器晶圓1201可包含複數個互連層及經嵌入此等互連層之金屬接線。金屬接線1120、金屬接線1122、金屬接線1124及金屬接線1126可提供介於感測器晶圓1201與ASIC晶圓1203之間的訊號路徑。詳言之，如藉由第12圖中圖示之箭頭所指示，外部訊號可經由鋁銅墊1112進入背光圖像感測器1200，且隨後經由諸如通孔(未圖示)之互連結構到達金屬佈線(例如，金屬接線1120)。外部訊號可進一步通過三維結構1210。三維結構1210可為第9圖中圖示之三維結構904、第10圖中圖示之三維結構1003、第11圖中圖示之三維結構1103及/或前述各者之任何組合。
在外部訊號通過三維結構1210之後，外部訊號可 經由ASIC晶圓1203之金屬佈線(例如，金屬接線1220)到達邏輯電路1206。
當訊號離開邏輯電路1206時，此訊號經由導電路徑到達圖像感測器1110，此導電路徑係藉由ASIC晶圓1203之金屬佈線(例如，金屬接線1222)、三維結構1210、感測器晶圓1201之金屬佈線(例如，金屬接線1122)而形成。
在圖像感測器1110產生訊號之後，此訊號係經由路徑而傳送至邏輯電路1208，此路徑係藉由感測器晶圓1201之金屬佈線(例如，金屬接線1124)、三維結構1210、ASIC晶圓1203之金屬佈線(例如，金屬接線1224)而形成。此外，可經由路徑將訊號自邏輯電路1208傳送至背光圖像感測器1200外，此路徑係藉由ASIC晶圓1203之金屬佈線(例如，金屬接線1226)、三維結構1210、感測器晶圓1201之金屬佈線(例如，金屬接線1126)及鋁銅墊1114而形成。
可將邏輯電路1206及1208耦接至鋁銅墊1112及1114。如第12圖所示，鋁銅墊1112及1114可形成於感測器晶圓1201之背側上。
應注意，第12圖中圖示之鋁銅墊1112及1114之位置僅為實例。熟習此項技術者將認識到，可存在許多替代選擇、修改及變化。舉例而言，鋁銅墊1112及1114可形成於ASIC晶圓1203之非接合側上。背光圖像感測器之形式因子可藉由在ASIC晶圓1203之非接合側上形成鋁銅墊1112及1114而縮減。
具有形成於ASIC晶圓1203之非接合側上之輸入/輸出端的一優點為，背光圖像感測器1200之密度以及量子效 率可因此改進。
第13圖圖示根據本發明之各種實施例之硬遮罩之頂視圖。如上根據第9圖、第10圖及第11圖所述，硬遮罩層可分別藉由金屬接線、接觸面及再分配接線而形成。當剖面視圖1301圖示硬遮罩層包括兩個部分(例如，金屬接線106及金屬接線108)時，此兩個部分可來自於如藉由頂視圖1302圖示之連續環形區。硬遮罩層之頂視圖1302圖示硬遮罩層具有環形形狀。環形硬遮罩層之內徑表示為W1。
應注意，環形硬遮罩層之內圈可藉由其他適當形狀而取代，該適當形狀諸如如藉由頂視圖1304所示之正方形。在本發明之各種實施例之範疇及精神內，硬遮罩層之頂視圖可包含其他形狀，諸如但不局限於橢圓形、三角形、多邊形及/或類似形狀。
第14圖圖示根據本發明之各種實施例之硬遮罩的另一頂視圖。第14圖之頂視圖係類似於第13圖中圖示之彼等頂視圖，不同之處在於環形係藉由具有開口之正方形來取代。頂視圖1402圖示具有正方形開口之正方形。頂視圖1404圖示具有圓形開口之正方形。
根據實施例，設備包含：第一半導體晶片(chip)，包括第一基板及形成於第一基板上之複數個第一金屬接線；及第二半導體晶片，接合於第一半導體晶片上，其中第二半導體晶片包含第二基板及形成於第二基板上之複數個第二金屬接線。
半導體裝置進一步包含耦接在第一金屬接線與第二金屬接線之間的導電插塞，其中此導電插塞包含形成於硬 遮罩層之第一側上的第一部分及形成於硬遮罩層之第二側上的第二部分，其中此第一部分具有第一寬度，其中此第二部分具有第二寬度，第二寬度大於或等於第一寬度。
根據實施例，裝置包含第一晶片、第二晶片及導電插塞。第一晶片包含第一基板及複數個第一互連元件，該複數個第一互連元件形成於第一金屬間介電層內且在第一基板上。第二晶片係接合於第一晶片上。第二晶片包含第二基板及複數個第二互連元件，該複數個第二互連元件形成於第二金屬間介電層內且在第二基板上。導電插塞係經由第一基板及第一金屬間介電層而形成且經由第二金屬間介電層而局部地形成。導電插塞係耦接在第一互連元件與第二互連元件之間。
根據實施例，方法包含將第一半導體晶圓接合於第二半導體晶圓上，其中第一半導體晶圓包含第一基板、第一金屬間介電層及第一互連結構，該等第一互連結構形成於第一金屬間介電層內且在第一基板上，且第二半導體晶圓包含第二基板、第二金屬間介電層及第二互連結構，該等第二互連結構形成於第二金屬間介電層內且在第二基板上。
方法進一步包含：圖案化第一基板以經由第一基板形成第一開口；使用蝕刻製程及使用作為硬遮罩層之第一互連結構形成第二開口，其中第二開口係經由第一金屬間介電層且局部經由第二金屬間介電層而形成；及在第一開口及第二開口內電鍍導電材料。
儘管已詳細描述本發明之實施例及本發明之優點，但應理解，在不脫離如藉由隨附申請專利範圍所定義之 本發明之精神及範疇的情況下，在本文中可進行各種改變、替換及變更。
此外，本申請案之範疇不意欲局限於本說明書中所描述之製程、機器、製造、物質之組成、手段、方法及步驟之特定實施例。因為一般技術者將易於由本發明之揭示內容瞭解到，可根據本發明利用目前存在或以後將開發之製程、機器、製造、物質之組成、手段、方法或步驟，此等目前存在或以後將開發之製程、機器、製造、物質之組成、手段、方法或步驟執行實質上與本文描述之對應實施例相同的功能或達成實質上與本文描述之對應實施例相同的結果。因此，隨附申請專利範圍意欲包括在此申請專利範圍之範疇內包括此等製程、機器、製造、物質之組成、手段、方法或步驟。
100‧‧‧堆疊半導體裝置
102‧‧‧第一基板
104‧‧‧金屬間介電層
106‧‧‧金屬接線
108‧‧‧金屬接線
202‧‧‧第二基板
204‧‧‧金屬間介電層
206‧‧‧金屬接線
208‧‧‧金屬接線
404‧‧‧開口
406‧‧‧開口

Claims (9)

  1. 一種半導體裝置，包含：一第一晶片，包含：一第一基板；以及複數個第一互連元件，形成於第一金屬間介電層內且在該第一基板上，其中該第一互連元件包含一硬遮罩層；一第二晶片，接合於該第一晶片上，其中該第二晶片包含：一第二基板；以及複數個第二互連元件，形成於第二金屬間介電層內且在該第二基板上；以及一導電插塞，經由該第一基板及該等第一金屬間介電層而形成且經由該等第二金屬間介電層而局部形成，其中該導電插塞係耦接在該等第一互連元件與該等第二互連元件之間，位於該硬遮罩層之上的導電插塞具有一寬度大於位於該硬遮罩層之下的導電插塞的一寬度，且位於該第一基板之內的導電插塞具有一寬度大於位於該硬遮罩層之上的導電插塞的寬度。
  2. 如請求項1所述之半導體裝置，其中：該硬遮罩層係由兩個第一互連元件而形成。
  3. 如請求項1所述之半導體裝置，其中：該硬遮罩層係由該第一晶片之兩個接觸面而形成。
  4. 如請求項1所述之半導體裝置，其中： 該硬遮罩層係由該第一晶片之兩個再分配接線而形成。
  5. 一種半導體裝置製造方法，包含：將一第一半導體晶圓接合於一第二半導體晶圓上，其中：該第一半導體晶圓包含一第一基板、第一金屬間介電層及第一互連結構，該等第一互連結構形成於該等第一金屬間介電層內且在該第一基板上，其中任兩個第一互連元件形成一硬遮罩層；以及該第二半導體晶圓包含一第二基板、第二金屬間介電層及第二互連結構，該等第二互連結構形成於該等第二金屬間介電層內且在該第二基板上；圖案化該第一基板以在該第一基板內形成一第一開口；使用一蝕刻製程及使用作為一硬遮罩層之該等第一互連結構形成一第二開口，其中該第二開口係經由該等第一金屬間介電層且局部經由該等第二金屬間介電層而形成；以及在該第一開口及該第二開口內電鍍一導電材料以形成一導電插塞，其中，位於該硬遮罩層之上的導電插塞具有一寬度大於位於該硬遮罩層之下的導電插塞的一寬度，且位於該第一基板之內的導電插塞具有一寬度大於位於該硬遮罩層之上的導電插塞的寬度。
  6. 如請求項5所述之方法，進一步包含：於該第一半導體晶圓之一背側上沉積一底部抗反射塗層；以 及移除該第一基板之一部分以形成該第一開口。
  7. 如請求項5所述之方法，進一步包含：使用作為該硬遮罩層之該第一半導體晶圓之複數個金屬接線形成該第二開口。
  8. 如請求項5所述之方法，進一步包含：使用作為該硬遮罩層之該第一半導體晶圓之複數個接觸面形成該第二開口。
  9. 如請求項5所述之方法，進一步包含：使用作為該硬遮罩層之該第一半導體晶圓之複數個再分配接線形成該第二開口。
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