CN105161427B - 半导体基板、半导体封装与半导体装置的制造方法 - Google Patents
半导体基板、半导体封装与半导体装置的制造方法 Download PDFInfo
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Abstract
一种半导体基板被公开,该半导体基板包括载体、第一导电层与第二导电层。载体具有第一表面、第二表面以及用以容置半导体元件的凹部。第一导电层埋设在第一表面中,并形成多个电隔离的封装走线。第二导电层埋设在第二表面中,并与第一导电层电连接。半导体基板可以应用于半导体封装,用于容纳半导体芯片,且半导体基板与用于固定该芯片的填充结构结合。此外,多个半导体基板可以被堆叠且通过粘结层连接,以便形成具有复杂结构的半导体装置。
Description
本申请是申请日为2009年11月17日且发明名称为“半导体基板、封装与装置”的中国专利申请200980145387.7的分案申请。
本申请要求于2008年11月17日提交的美国申请第61/115,490号的权益,其主题通过引用结合于此。
技术领域
本发明大体上涉及一种半导体基板、半导体封装与半导体装置的制造方法。
背景技术
现今,随着消费者所期望的电子产品的微型化趋势,应用于各种电子产品中的半导体装置的尺寸也被限制以便满足所需的规格。然而,半导体装置的微型化涉及半导体装置的内部结构,当减小半导体装置的尺寸时这应该被考虑。举例来说,当诸如集成电路芯片的半导体装置需进行复杂的逻辑功能时,该半导体装置的内部导电走线的布局应该精确地被控制。然而,在这种情况下,难以减小半导体装置的尺寸,而限制了半导体装置的微型化。
半导体装置的电子封装结构包括单芯片封装和多芯片封装。对于封装上封装,多个半导体基板叠加,如此将使装置的总厚度增加不少。因此,难以达到微型化的目的。如何缓解上述微型化的情况在半导体装置的开发中是非常重要的。
发明内容
因此,本发明的目标是提供一种半导体基板、半导体封装、半导体装置及其制造方法。半导体基板具有用于容置半导体元件,诸如半导体芯片的凹部,从而降低整体厚度,有助于半导体装置的微型化。
本发明通过提供这样的半导体基板而实现上述目标,该半导体基板包括载体、第一导电层与第二导电层。载体具有第一表面和与第一表面相反的第二表面,其中载体还具有凹部,用以容置半导体元件。第一导电层埋设在第一表面中,并形成多个电隔离的封装走线。第二导电层埋设在第二表面中,并与第一导电层电连接。
本发明通过提供这样的半导体封装而实现上述目标,该半导体封装包括载体、第一导电层、第二导电层、半导体芯片与填充结构。载体具有第一表面和与第一表面相反的第二表面,其中载体还具有凹部。第一导电层埋设在第一表面中,并形成多个电隔离的封装走线。第二导电层埋设在第二表面中,并与第一导电层电连接。半导体芯片设置在凹部中。填充结构设置在凹部中,用于填充半导体芯片与载体之间的空隙。
本发明通过提供这样的半导体装置而实现上述目标,该半导体装置包括多个半导体基板和多个粘结层。多个半导体基板逐层设置。每个半导体基板包括载体、第一导电层与第二导电层。载体具有第一表面和与第一表面相反的第二表面,其中载体还具有凹部。第一导电层埋设在第一表面中,并形成多个电隔离的封装走线。第二导电层埋设在第二表面中,并与第一导电层电连接。粘结层设置在半导体基板之间,以结合半导体基板。
本发明通过提供这样的半导体基板的制造方法而实现上述目标。该半导体基板的制造方法包括:提供基层;形成第一导电层在基层上,以便形成多个电隔离的封装走线;形成第二导电层在第一导电层上;形成模制材料层,以覆盖第一导电层和第二导电层;在模制材料层中形成凹部,并暴露第二导电层,以形成载体;以及去除基层。
本发明通过提供这样的半导体封装的制造方法而实现上述目标。该半导体封装的制造方法包括步骤:提供基层;形成第一导电层在基层上,以便形成多个电隔离的封装走线;形成第二导电层在第一导电层上;形成模制材料层,以覆盖第一导电层和第二导电层;在模制材料层中形成凹部,并暴露第二导电层,以形成载体;去除基层;设置半导体芯片在凹部中;以及在凹部中形成填充结构,以填充半导体芯片与载体之间的空隙。
本发明通过提供这样的半导体装置的制造方法而实现上述目标。该制造方法包括步骤:提供多个半导体基板,其中每个半导体基板包括载体、第一导电层和第二导电层,载体具有凹部,第一导电层埋设在载体的第一表面中,第二导电层埋设在载体的与第一表面相反的第二表面中;在半导体基板之间提供多个粘结层;以及通过接合粘结层而结合半导体基板。
通过以下对优选但是是非限制性实施例的详细描述,本发明的其他目标、特征和优点将变得显而易见。参考附图进行以下说明。
附图说明
图1至14示出半导体基板的制造方法的工艺;
图15至21示出半导体基板的另一制造方法的工艺;
图22至26示出半导体基板的不同结构;
图27示出逐层设置的二个半导体基板;
图28至29示出将半导体芯片设置在半导体基板上的工艺;以及
图30至32示出半导体装置的制造方法的工艺。
具体实施方式
根据本发明优选实施例的半导体基板、半导体封装与半导体装置及其制造方法被公开。图1至图14示出半导体基板的制造方法的工艺。
如图1所示,提供基层100。基层100优选是材料为钢的导电结构。
接着,如图2所示,在基层100上形成光致抗蚀剂层102。光致抗蚀剂层102的材料可为正型抗蚀剂或负型抗蚀剂。
然后,如图3所示,通过例如光刻工艺图案化光致抗蚀剂层102。具有图案设计的光掩模104设置在光致抗蚀剂层102上方,使得光致抗蚀剂层102被辐射选择性曝光,光掩模104的图案被转移到光致抗蚀剂层102。光致抗蚀剂层102例如是正型光致抗蚀剂层,从而其的曝光部分102a会在后续显影工艺中采用的显影剂液体中溶解并被清洗掉。最后,保留图案化光致抗蚀剂层102b在基层100上,如图4所示。
接着,如图5所示,形成第一导电层106于基层100上,以便形成多个电隔离的封装走线(trace)。由于基层100上设置有图案化光致抗蚀剂层102b,第一导电层106的材料形成在图案化光致抗蚀剂层102b的开口中。第一导电层106可以通过电镀形成,且优选层数多于一层,其材料为Cu、Ni、Au或Sn。第一导电层106的多层结构及其所需的厚度可通过重复以上的相关步骤而实现。之后,图案化光致抗蚀剂层102b被去除,保留第一导电层106于基层100上,如图6所示。第一导电层106的封装走线可根据所需的走线图案布置,从而形成走线布局,这涉及装置的操作功能。
然后,如图7所示,形成另一光致抗蚀剂层108于基层100上并覆盖第一导电层106。光致抗蚀剂层108的材料也可为正型抗蚀剂或负型抗蚀剂。
接着,如图8所示,通过例如光刻工艺图案化光致抗蚀剂层108。光掩模110设置在光致抗蚀剂层108上方,使得光致抗蚀剂层108被辐射选择性曝光,光掩模110的图案被转移到光致抗蚀剂层108。光致抗蚀剂层108例如为正型光致抗蚀剂层,使得其的曝光部分108a会在后续显影工艺中采用的显影剂液体中溶解并被清洗掉。最后,保留图案化光致抗蚀剂层108b在基层100上,如图9所示。图案化光致抗蚀剂层108b的开口对应第一导电层106而定位。
然后,如图10所示,形成第二导电层112于第一导电层106上。由于基层100上设置有图案化光致抗蚀剂层108b,第二导电层112的材料形成在图案化光致抗蚀剂层108b的开口中。第二导电层112可以通过电镀形成,且层数多于一层,其材料为Cu、Ni、Au或Sn。第二导电层112的多层结构及其所需的厚度可通过重复以上的相关步骤而实现。之后,图案化光致抗蚀剂层108b被去除,保留第二导电层112于第一导电层106上,如图11所示。第二导电层112由多个导电柱组成。导电柱的位置与数量优选与第一导电层106的封装走线一致。上述与第一导电层106和第二导电层112的形成相关的步骤可重复好几次,从而形成用于进行所需功能的更多个导电层。
接着,形成模制材料层116以覆盖第一导电层106与第二导电层112,其中,模制材料层的材料优选为绝缘材料。如图12所示,具有突出114a的模子114用于在模制材料层116上形成凹部116a。
然后,通过研磨减薄模制材料层116,用于暴露第二导电层112的上表面。由此,如图13所示,形成载体120及其凹部120a。之后,去除基层100,如图14所示,完成半导体基板125的制造。
此外,根据工艺,第一导体层106和第二导体层112的暴露的走线或柱表面可突出于载体120的表面或是从载体120的表面凹入。举例来说,在暴露走线表面的步骤后,也可通过蚀刻进一步去除走线层,以使走线表面从载体120的表面凹入。另一方面,也可通过例如无电镀镍浸金(electroless nickel immersion gold,ENIG)工艺在走线表面添加额外的金属层,使得其突出于载体120的表面。相同的工艺也可用于柱表面。
半导体基板125亦可根据其他的方法被制造。图15至图21示出半导体基板的另一制造方法的工艺。该制造方法包括图1至图5所示的以上步骤,下面将不再重复描述。
如图15至图16所示,形成模制材料层130在基层100上并覆盖第一导电层106。模制材料层130的材料优选为绝缘材料。
接着,通过研磨将模制材料层130减薄以形成厚度较小的模制材料层130a,并暴露第一导电层106的上表面,如图17所示。
然后,如图18所示,采用与图7至图11中描述的相似的工艺形成第二导电层112于第一导电层106上。
接着,如图19所示,在模制材料层130a上形成另一模制材料层132以覆盖第一导电层106与第二导电层112。然后,与图12的模子14相似的模子用于在模制材料层上形成凹部。
之后,通过研磨将模制材料层减薄,以暴露第二导电层112的上表面。如图20所示,完成载体120及其凹部120a的形成。最后,去除基层100,完成半导体基板125(如图14所示)的制造。
备选地,如图21所示,可部分去除基层100的材料,用于形成环形结构100a。环形结构100a增强半导体基板125a与其他元件结合时的支撑强度。
如图14或图21所示,半导体基板125、125a的每个包括载体120。第一导电层106与第二导电层112电连接,且埋设在载体120二个相反表面中。载体120的凹部120a可用以容置任何半导体元件,如半导体芯片。半导体基板可具有其他的结构设计。图22至图26示出半导体基板的不同结构。
在图22中,半导体基板125b的载体120的凹部为贯穿孔120b。贯穿孔120b从载体120的上表面延伸至载体120的底表面。
在图23中,半导体基板125c的载体120的凹部为凹进120c。凹进120c从载体120的上表面朝载体120的底表面延伸直至第一导电层106,以部分暴露第一导电层106的表面,这使得凹进120c内的半导体芯片(未示出)能够与第一导电层106的电性连接。
在图24中,半导体基板125d的载体120的凹部为凹进120d的形式,凹进120d的凹进深度不同于图23的凹进123c。凹进120d从载体120的上表面朝载体120的底表面延伸,而不暴露第一导电层106。此外,在凹进120d的内表面设置金属屏蔽层134,用于提供静电放电(ESD)防护功能。另外,金属屏蔽层134可延伸至载体120的上表面。图27示出半导体基板125d叠层设置在另一半导体基板400之上。设置在半导体基板125d的凹进120d内的半导体芯片136电性连接到半导体基板125的上表面。凹进120d的金属屏蔽层134作为半导体芯片136的静电防护层,使半导体芯片136与上半导体基板125d及另一半导体芯片138隔离。
在图25中,半导体基板125e的载体120具有凹进120e形式的凹部,凹进120e具有台阶120f。台阶120f与载体120的上表面之间具有高度差。当设置金属屏蔽层(如图24的金属屏蔽层134)在凹进120e中时,金属屏蔽层还可延伸至台阶120f,用以与其他元件电性连接。
在图26中,半导体基板125f还包括钝化层140和142,钝化层140和142分别设置在载体120的底表面与上表面上。优选地,钝化层140、142可通过丝网印刷(screen printing)接着固化而形成,且具有开口用于暴露第一导电层106与第二导电层112,使得第一导电层106与第二导电层112能够通过焊料层144、146与其他元件电性连接。焊料层144、146优选通过电镀(electroplating)或焊料膏印刷(solder paste printing)工艺形成。钝化层可以仅设置在载体120的上表面或底表面上。钝化层的布置和数量取决于对半导体装置的需求。
图28至图29示出半导体芯片设置在半导体基板上的工艺。以上公开的所有半导体基板可以与至少一个半导体芯片结合,但这里将图23的半导体基板125c作为示例。
如图28所示,半导体基板125c定位于接合平台160上,半导体基板125c的凹进120c朝上。以倒装芯片(flip-chip)封装为例。当半导体芯片170制作完成后,半导体芯片170设置在接合头162上,接合头160与半导体芯片170同时反转并移动到凹进120c上方的位置。优选地,在半导体芯片170移动到凹进120c之前,设置在半导体芯片170上的连接结构首先对齐第一导电层106。优选地,连接结构包括铜块(copper bump)172与焊料层174,用以电连接半导体芯片170与第一导电层106。半导体芯片170到第一导电层106的附着通过热压接合实现。
接着,如图29所示,在凹进120c中形成填充结构180,以填充半导体芯片170与载体120之间的空隙,由此形成半导体封装190。填充结构180包括至少一种填充材料,例如,第一填充材料182和第二填充材料184。第一填充材料182位于半导体芯片170与载体120之间。第二填充材料184围绕半导体芯片170和第一填充材料182。优选地,第一填充材料182是底层填充粘合剂(underfill adhesive),用于辅助半导体芯片170与载体120之间的附着。第二填充材料184优选是模塑料(molding compound),用以密封半导体芯片170与第一填充材料182且加强载体120对半导体芯片170的支撑。优选地,半导体芯片170的上表面被暴露,用于更好的散热。备选地,第二填充材料184可完全包封半导体芯片170,以提供更好的保护。
半导体基板和半导体封装还应用于不同种类的半导体装置。图30至图32示出半导体装置的制造方法的工艺。首先,如图30所示,提供相同结构或不同结构的多个半导体基板200、300和400。半导体基板200包括第一导电层206、第二导电层212与载体220。第一导电层206与第二导电层212电性连接,且分别埋设在载体220的上表面与底表面中。在装配前,多个导电焊垫(或焊料层)对应于第一导电层206设置在载体220的上表面上,用以电连接至其他半导体基板或电子部件。导电焊垫的材料可为诸如Au、Ag等的金属材料。另外,在载体220的底表面上可对应于第二导电层212设置多个焊料层260(或导电焊垫),用以连接至半导体基板300。焊料层260的材料可为诸如Sn、Ag等的金属。优选地,在半导体基板200被装配前,半导体芯片270和填充结构280已经设置在载体220的凹进220a中。
半导体基板300包括第一导电层306、第二导电层312和载体320。第一导电层306与第二导电层312电性连接,且分别埋设在载体320的上表面和底表面中。优选地,多个导电焊垫350(或焊料层)对应于第一导电层306设置在载体320的上表面上,用于电连接到半导体基板200的焊料层260。导电焊垫350的材料可为诸如Au、Ag等的金属。多个焊料层360(或导电焊垫)对应于第二导电层312设置在载体320的底表面上,用以连接至半导体基板400。焊料层360的材料可为诸如Sn、Ag等的金属。优选地,在半导体基板300被装配之前,载体320的凹进320a中已设置半导体芯片370和填充结构380。
半导体基板400包括第一导电层406、第二导电层412与载体420。第一导电层406与第二导电层412电性连接,且分别埋设在载体420的上表面和底表面中。优选地,在载体420的上表面上对应于第一导电层406设置多个焊料层450(或导电焊垫),用以电连接至半导体基板300的焊料层360。在载体420的底表面上对应于第二导电层412设置多个焊料层460(或导电焊垫),用以连接至其他半导体基板或电子部件。焊料层450和460的材料可为诸如Sn、Ag等的金属。优选地,焊料层260、360、450和460与导电焊垫250、350通过电镀形成在第一导电层206、306和406以及第二导电层212、312和412的暴露表面上。
接着,在半导体基板之间设置多个粘结层。如图31所示,粘结层502位于半导体基板200与300之间。优选地,粘结层502直接涂布在半导体基板300的上表面上。另一粘结层504位于半导体基板300与400之间。优选地,粘结层504直接涂布在半导体基板400的上表面上。粘结层502和504的材料优选为绝缘材料。
然后,半导体基板通过接合粘结层而结合。如图31和32所示,半导体基板200、300和400对齐且通过压力彼此靠近,以便装配且堆叠在一起。同时,堆叠在一起的半导体基板200、300和400也被固化,以形成粘结层、焊垫层以及导电焊垫之间的连接。这里,完成了半导体装置510的制作。半导体装置510还可通过导电焊垫250以及焊料层460连接到其他电子部件或基板,从而扩充半导体装置510的结构以及操作性能。
以上公开了根据本发明优选实施例的半导体基板、半导体封装和半导体装置及其制造方法。半导体基板具有凹部,用于容置诸如半导体芯片的半导体元件,这不仅降低了装置的整体厚度,且有助于具有堆叠基板的半导体装置的微型化。半导体基板的凹部可为选择性的暴露封装走线的贯穿孔或凹进,该封装走线用于电连接到半导体芯片或其他元件。另外,凹部中可形成底层填充粘合剂和模塑料。堆叠的半导体基板和半导体芯片之间的电性连接通过导电焊垫和焊料层实现。如此一来,半导体装置以其厚度被有效地控制而可扩展,且与常规装置相比在半导体市场中更有竞争力。
虽然本发明通过示例且根据优选实施例已经被描述,但应该理解的是,本发明不限于此。相反,其旨在覆盖各种修改、相似的布置和程序,本发明的权利要求的范围应该符合最宽的解释,以便包括所有这样的修改、相似的布置和程序。
Claims (41)
1.一种半导体基板、封装或装置的制造方法,包括:
提供基层;
形成多个走线在所述基层上;
形成多个导电柱在所述走线上;
形成模制材料层在所述基层上,以覆盖该些走线和该些导电柱,其中所述模制材料层构成载体,所述载体具有第一表面与第二表面,所述第一表面邻近所述基层,所述第二表面与所述基层相对;在所述载体的所述第二表面上形成凹部,所述凹部没有暴露所述走线;以及
去除所述基层。
2.如权利要求1所述的制造方法,还包括:
减薄所述模制材料层以形成载体,其中该些走线和该些导电柱埋设在所述载体中,并电性连接所述第一表面至所述第二表面。
3.如权利要求1所述的制造方法,还包括:设置半导体芯片在所述凹部中。
4.如权利要求3所述的制造方法,其中所述凹部为贯穿孔,所述贯穿孔从所述载体的所述第一表面延伸至所述第二表面。
5.如权利要求4所述的制造方法,其中,所述凹部暴露部分之该些走线,且所述半导体芯片电连接到该些走线。
6.如权利要求5所述的制造方法,其中所述半导体芯片到该些走线的附着通过热压接合实现。
7.如权利要求3所述的制造方法,还包括:在所述凹部中形成填充结构,用以密封所述半导体芯片。
8.如权利要求7所述的制造方法,其中形成所述填充结构的步骤包括:
形成第一填充材料在所述半导体芯片与所述载体之间;以及
形成第二填充材料,用以密封所述半导体芯片和所述第一填充材料。
9.如权利要求1所述的制造方法,还包括:在所述凹部的表面上形成金属屏蔽层。
10.如权利要求2所述的制造方法,还包括:
在所述载体上形成钝化层;
在所述钝化层中形成多个开口;以及
在所述开口中形成多个焊料层或导电焊垫。
11.如权利要求1所述的制造方法,其中,所述基层为部分去除,以形成环形结构。
12.如权利要求1所述的制造方法,其中,在形成所述凹部之前,将该些走线和该些导电柱以及所述模制材料层的形成步骤重复几次,从而形成多层结构。
13.一种半导体基板、封装或装置的制造方法,包括:
提供基层;
形成第一导电层在所述基层上;
形成第一模制材料层在所述基层上,以覆盖所述第一导电层;
形成第二导电层在所述第一模制材料层上;
形成第二模制材料层在所述第一模制材料层上,以覆盖所述第二导电层,其中所述第一模制材料层和所述第二模制材料层构成载体,所述载体具有第一表面与第二表面,所述第一表面邻近所述基层,所述第二表面与所述基层相对;
在所述载体的所述第二表面上形成凹部,所述凹部没有暴露所述第一导电层;以及
去除所述基层。
14.如权利要求13所述的制造方法,其中所述第一导电层和所述第二导电层埋设在所述载体中,并电性连接所述第一表面至所述第二表面。
15.如权利要求14所述的制造方法,其中所述凹部为贯穿孔,所述贯穿孔从所述载体的所述第一表面延伸至所述第二表面。
16.如权利要求13所述的制造方法,还包括:
减薄所述第一模制材料层和所述第二模制材料层,以形成载体。
17.如权利要求13所述的制造方法,还包括:设置半导体芯片在所述凹部中。
18.如权利要求17所述的制造方法,其中,所述凹部暴露部分之所述第一导电层,且所述半导体芯片电连接到所述第一导电层。
19.如权利要求18所述的制造方法,其中所述半导体芯片到所述第一导电层的附着通过热压接合实现。
20.如权利要求17所述的制造方法,还包括:在所述凹部中形成填充结构,用以密封所述半导体芯片。
21.如权利要求20所述的制造方法,其中形成所述填充结构的步骤包括:
形成第一填充材料在所述半导体芯片与所述载体之间;以及
形成第二填充材料,用以密封所述半导体芯片和所述第一填充材料。
22.如权利要求13所述的制造方法,还包括:在所述凹部的表面上形成金属屏蔽层。
23.如权利要求13所述的制造方法,还包括:
在所述载体上形成钝化层;
在所述钝化层中形成多个开口;以及
在所述开口中形成多个焊料层或导电焊垫。
24.如权利要求13所述的制造方法,其中,所述基层为部分去除,以形成环形结构。
25.如权利要求13所述的制造方法,其中,所述形成第一导电层的步骤包括形成多个走线。
26.如权利要求13所述的制造方法,其中,所述形成第二导电层的步骤包括形成多个导电柱在所述第一导电层上。
27.如权利要求13所述的制造方法,其中,在形成所述凹部之前,将所述导电层以及所述模制材料层的形成步骤重复几次,从而形成多层结构。
28.一种半导体装置的制造方法,包括:
提供多个半导体基板,其中至少一个所述半导体基板的形成方法包括如下步骤:
提供基层;
形成多个走线在所述基层上;
形成多个导电柱在所述走线上;
形成模制材料层在所述基层上,以覆盖该些走线和该些导电柱,其中所述模制材料层构成载体,所述载体具有第一表面与第二表面,所述第一表面邻近所述基层,所述第二表面与所述基层相对;
在所述载体的所述第二表面上形成凹部,所述凹部没有暴露所述走线;
去除所述基层;
以及
层叠设置该些半导体基板;
其中,对应所述凹部的位置设置有一半导体芯片。
29.如权利要求28所述的制造方法,还包括:
减薄所述模制材料层,以暴露该些导电柱;
去除所述基层以露出该些走线。
30.如权利要求28所述的制造方法,其中,该些半导体基板通过施加压力层叠设置,并相互之间电性连接。
31.如权利要求30所述的制造方法,还包括:
在该些半导体基板之间设置粘结层,使该些半导体基板通过所述粘结层而结合。
32.如权利要求29所述的制造方法,还包括:
在暴露出的该些走线和该些导电柱上,形成多个焊料层和导电焊垫。
33.如权利要求32所述的制造方法,其中,在所述层叠设置该些半导体基板的步骤中,该些半导体基板之间通过该些焊料层和导电焊垫而电性连接。
34.如权利要求29所述的制造方法,其中,所述凹部暴露部分之该些走线,且所述半导体芯片电连接到该些走线。
35.如权利要求34所述的制造方法,其中所述半导体芯片到该些走线的附着通过热压接合实现。
36.如权利要求28所述的制造方法,还包括:在所述凹部中形成填充结构,用以密封所述半导体芯片。
37.如权利要求36所述的制造方法,其中形成所述填充结构的步骤包括:
形成第一填充材料在所述半导体芯片与所述载体之间;以及
形成第二填充材料,用以密封所述半导体芯片和所述第一填充材料。
38.如权利要求28所述的制造方法,还包括:在所述凹部的表面上形成金属屏蔽层。
39.如权利要求28所述的制造方法,其中所述凹部为贯穿孔,形成于所述模制材料层中。
40.如权利要求28所述的制造方法,还包括:对应于邻近的第二半导体基板的所述凹部,设置半导体元件在第一半导体基板上。
41.如权利要求28所述的制造方法,其中,在形成所述凹部之前,将该些走线和该些导电柱以及所述模制材料层的形成步骤重复几次,从而形成多层结构。
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TWI418009B (zh) * | 2011-12-08 | 2013-12-01 | Unimicron Technology Corp | 層疊封裝的封裝結構及其製法 |
US9564415B2 (en) * | 2012-09-14 | 2017-02-07 | Maxim Integrated Products, Inc. | Semiconductor package device having passive energy components |
US9754899B2 (en) * | 2013-02-21 | 2017-09-05 | Advanpack Solutions Pte Ltd | Semiconductor structure and method of fabricating the same |
CN103633056B (zh) * | 2013-12-06 | 2017-09-01 | 矽力杰半导体技术(杭州)有限公司 | 引线框、封装组件及其制造方法 |
TWI563606B (en) * | 2014-01-29 | 2016-12-21 | Siliconware Precision Industries Co Ltd | Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof |
TWI567889B (zh) * | 2014-08-29 | 2017-01-21 | 萬國半導體股份有限公司 | 用於帶有厚背面金屬化的模壓晶片級封裝的晶圓製作方法 |
KR20170067947A (ko) * | 2015-12-08 | 2017-06-19 | 에스케이하이닉스 주식회사 | 측면 차폐부를 가지는 반도체 패키지 및 제조 방법 |
CN109478516B (zh) * | 2016-04-29 | 2023-06-13 | 库利克和索夫工业公司 | 将电子组件连接至基板 |
CN113808958A (zh) * | 2021-09-17 | 2021-12-17 | 成都奕斯伟系统集成电路有限公司 | 一种芯片封装结构制作方法及芯片封装结构 |
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