JP2012231176A - 半導体装置用基板、樹脂封止型半導体装置、半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法 - Google Patents
半導体装置用基板、樹脂封止型半導体装置、半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 216
- 239000004065 semiconductor Substances 0.000 title claims abstract description 180
- 239000011347 resin Substances 0.000 title claims abstract description 39
- 229920005989 resin Polymers 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000010410 layer Substances 0.000 claims description 118
- 238000007747 plating Methods 0.000 claims description 94
- 229910052737 gold Inorganic materials 0.000 claims description 29
- 238000007789 sealing Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 19
- 229910052709 silver Inorganic materials 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 229910052763 palladium Inorganic materials 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 20
- 239000000463 material Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 4
- 206010040844 Skin exfoliation Diseases 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 235000019270 ammonium chloride Nutrition 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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Abstract
【解決手段】半導体装置用基板10は、基板1と、基板1上に平面状に配置され、基板1側を向いた外部端子面12pb,12qbを有する複数の外部端子部12p,12qと、基板1上に平面状に配置され、基板1に対して反対側を向いた内部端子面11aを有する複数の内部端子部11と、を備えている。内部端子部11と外部端子部12p,12qとは配線部17によって接続されている。一部の外部端子部12pは、基板1上であって、半導体素子50が配置される配置予定領域A内に配置されている。一部の外部端子部12p以外の外部端子部12qは、基板1上であって、配線予定領域A外に配置されている。
【選択図】図2
Description
金属製の基板と、
基板上に平面状に配置され、基板側を向いた外部端子面を有する複数の外部端子部と、 基板上に平面状に配置され、基板に対して反対側を向いた内部端子面を有する複数の内部端子部と、
内部端子部と外部端子部とを基板上で平面状に接続する配線部と、を備え、
少なくとも一部の外部端子部が、基板上であって、半導体素子が配置される配置予定領域内に配置されている。
平面状に配置され、一方側を向いた内部端子面を有する複数の内部端子部と、
平面状に配置され、他方側を向いた外部端子面を有する複数の外部端子部と、
内部端子部と外部端子部とを平面状に接続する配線部と、
一部の外部端子部の一方側に、絶縁性の樹脂層(例えばダイアタッチフィルム、絶縁性ダイアタッチ剤など)を介して載置された半導体素子と、
半導体素子と内部端子部の内部端子面とを接続する内部接続部と、
少なくとも外部端子部の外部端子面が露出するように、内部端子部、外部端子部、半導体素子、内部接続部および配線部を封止する樹脂封止部と、
を備えている。
内部端子部は、一方側の端部が内部接続用めっき層からなり、
外部端子部は、他方側の端部が外部接続用めっき層からなり、
内部端子部、外部端子部および配線部の他方の側の面は、Ni、Pd、Ag、Auから選ばれる1種類以上の金属であることが好ましい。
金属製の基板の表面に、所望のパターンでレジストを設ける工程と、
基板の表面側にめっきを施して、基板と反対側の端部に内部端子面を有する複数の内部端子部と、基板側の端部に外部端子面を有する複数の外部端子部と、内部端子部と外部端子部とを接続する配線部とを形成する工程と、を備え、
一部の外部端子部が、基板上であって、半導体素子が配置される配置予定領域内に形成される。
金属製の基板の表面および裏面に感光性レジストを設ける工程と、
表面の感光性レジストに内部端子部と外部端子部と配線部のパターンを露光し、裏面の感光性レジストに基板を機械的に位置決めする治具穴を含む孔部のパターンを露光する工程と、
表面および裏面の感光性レジストを現像する工程と、
レジストが形成された基板の表面にめっきを施して内部端子部、外部端子部および配線部を形成し、裏面をエッチングして治具穴含む孔部を形成する工程と、
をさらに備えることが好ましい。
金属製の基板の表面に、所望のパターンでレジストを設ける工程と、
基板の表面側にめっきを施して、基板と反対側の端部に内部端子面を有する複数の内部端子部と、基板側の端部に外部端子面を有する複数の外部端子部と、内部端子部と外部端子部とを接続する配線部とを形成する工程と、
一部の外部端子部の基板と反対側の端部に絶縁性の樹脂層を介して半導体素子を載置する工程と、
内部接続部によって、半導体素子と内部端子部の内部端子面とを接続する工程と、
内部端子部、外部端子部、半導体素子、内部接続部および配線部を樹脂封止部によって封止する工程と、
基板を除去し、少なくとも外部端子部の外部端子面を露出させる工程と、
を備えている。
金属製の基板と、
基板上に平面状に配置され、基板側の端部が外部端子面を有する外部接続用めっき層からなる複数の外部端子部と、
基板上に平面状に配置され、基板に対して反対側の端部が内部端子面を有する内部接続用めっき層からなる複数の内部端子部と、
内部端子部と外部端子部とを基板上で平面状に接続する配線部と、を備え、
内部端子部、外部端子部および配線部の基板と接する部分がNi、Pd、Ag、Auのいずれかの金属であり、
外部端子部のうち外部接続用めっき層を除く部分の側面が、基板の法線方向に延在するとともに、外部接続用めっき層が形成されておらず、
内部端子部のうち内部接続用めっき層を除く部分の側面が、基板の法線方向に延在するとともに、内部接続用めっき層が形成されておらず、
少なくとも一部の外部端子部が、基板上であって、半導体素子が配置される配置予定領域内に配置されている。
以下、本発明に係る半導体装置用基板および樹脂封止型半導体装置の実施の形態について、図面を参照して説明する。ここで、図1乃至図5(a)−(f)は本発明の実施の形態を示す図である。
より具体的には、これらの内部端子部11は、配置予定領域A外で、上述した6行6列のマトリックス状の外部端子部12pを囲むようにして配置されている。一方フリップチップ実装の場合、内部端子部11はバンプの位置に対応して半導体素子50が配置される配置予定領域A内に配置されるように変更されるが、一部の外部端子部12pは配置予定領域A内に配置されていることは変わらない。
最初に、図4(a)−(e)を用いて、半導体装置用基板10の製造方法について説明する。なお、以下に説明する方法では、内部端子部11、外部端子部12p,12qおよび配線部17が同じ層構成からなり、内部端子部11および外部端子部12p,12qの各々が、基板1側(下方側)の端部に外部接続用めっき層62を有し、基板1に対して反対側(上方側)の端部に内部接続用めっき層61を有するものを用いて説明する。
このため、半導体装置用基板10を平面方向(厚さ方向に垂直な方向)で小型化することができる。
次に、図5(a)−(f)を用いて、上述のようにして製造された半導体装置用基板10を使用して、樹脂封止型半導体装置を製造する方法について説明する。
1a 孔部
10 半導体装置用基板
11 内部端子部
11a 内部端子面
12p,12q 外部端子部
12pb,12qb 外部端子面
17 配線部
20 ソルダーレジスト(絶縁層)
25 半田ボール(外部接続部)
27 開口部
30 ワイヤまたはバンプ(内部接続部)
35 絶縁性接着剤層(ダイアタッチフィルム)
40 樹脂封止部
50 半導体素子
61 内部接続用めっき層
62 外部接続用めっき層
A 配置予定領域
Claims (18)
- 金属製の基板と、
基板上に平面状に配置され、基板側を向いた外部端子面を有する複数の外部端子部と、 基板上に平面状に配置され、基板に対して反対側を向いた内部端子面を有する複数の内部端子部と、
内部端子部と外部端子部とを基板上で平面状に接続する配線部と、を備え、
内部端子部、外部端子部および配線部の基板と接する部分はNi、Pd、Ag、Auのいずれかの金属であり、
一部の外部端子部は、基板上であって、半導体素子が配置される配置予定領域内に配置され、
半導体素子の配置予定領域内に配置された前記一部の外部端子部以外の外部端子部は、基板上であって、配線予定領域外に配置されていることを特徴とする半導体装置用基板。 - 内部端子部は、基板上であって、半導体素子が配置される配線予定領域内に全て配置されていることを特徴とする請求項1に記載の半導体装置用基板。
- 内部端子部は、基板に対して反対側の端部が内部接続用めっき層からなり、
外部端子部は、基板側の端部が外部接続用めっき層からなることを特徴とする請求項1又は2のいずれかに記載の半導体装置用基板。 - 平面状に配置され、一方側を向いた内部端子面を有する複数の内部端子部と、
平面状に配置され、他方側を向いた外部端子面を有する複数の外部端子部と、
内部端子部と外部端子部とを平面状に接続する配線部と、
一部の外部端子部の一方側に、絶縁性の樹脂層を介して載置された半導体素子と、
半導体素子と内部端子部の内部端子面とを接続する内部接続部と、
少なくとも外部端子部の外部端子面が露出するように、内部端子部、外部端子部、半導体素子、内部接続部および配線部を封止する樹脂封止部と、
を備え、
絶縁性の接着剤層を介して半導体素子が載置された前記一部の外部端子部以外の外部端子部は、半導体素子に対して平面方向外方に配置されていることを特徴とする樹脂封止型半導体装置。 - 樹脂封止部のうち外部端子部の外部端子面側に配置され、当該外部端子面に対応する開口部を有する外部絶縁層と、
絶縁層の開口部に埋設され、外部端子部の外部端子面に接続された外部接続部と、
をさらに備えたことを特徴とする請求項4に記載の樹脂封止型半導体装置。 - 内部端子部は、半導体素子に対して平面方向外方に配置されていることを特徴とする請求項4又は5のいずれかに記載の樹脂封止型半導体装置。
- 絶縁性の接着剤層を介して半導体素子が載置された前記一部の外部端子部以外の外部端子部は、内部端子部に対して平面方向外方に配置されていることを特徴とする請求項6に記載の樹脂封止型半導体装置。
- 半導体と接続されている内部端子部は、半導体素子に対して平面方向内方に全て配置されていることを特徴とする請求項4、5又は7のいずれか1項に記載の樹脂封止型半導体装置。
- 内部端子部は、一方側の端部が内部接続用めっき層からなり、
外部端子部は、他方側の端部が外部接続用めっき層からなり、
内部端子部、外部端子部および配線部の他方の側の面はNi、Pd、Ag、Auから選ばれる1種類以上の金属あることを特徴とする請求項4乃至8のいずれか1項に記載の樹脂封止型半導体装置。 - 金属製の基板の表面に、所望のパターンでレジストを設ける工程と、
基板の表面側にめっきを施して、基板と反対側の端部に内部端子面を有する複数の内部端子部と、基板側の端部に外部端子面を有する複数の外部端子部と、内部端子部と外部端子部とを接続する配線部とを形成する工程と、を備え、
一部の外部端子部は、基板上であって、半導体素子が配置される配置予定領域内に形成され、
前記一部の外部端子部以外の外部端子部は、基板上であって、半導体素子が配置される配線予定領域外に形成されることを特徴とする半導体装置用基板の製造方法。 - 金属製の基板の表面および裏面に感光性レジストを設ける工程と、
表面の感光性レジストに内部端子部と外部端子部と配線部のパターンを露光し、裏面の感光性レジストに基板を機械的に位置決めする治具穴を含む孔部のパターンを露光する工程と、
表面および裏面の感光性レジストを現像する工程と
レジストが形成された基板の表面にめっきを施して内部端子部、外部端子部および配線部を形成し、裏面をエッチングして治具穴を含む孔部を形成する工程と、
をさらに備えたことを特徴とする請求項10に記載の半導体装置用基板の製造方法。 - 金属製の基板の表面に、所望のパターンでレジストを設ける工程と、
基板の表面側にめっきを施して、基板と反対側の端部に内部端子面を有する複数の内部端子部と、基板側の端部に外部端子面を有する複数の外部端子部と、内部端子部と外部端子部とを接続する配線部とを形成する工程と、
一部の外部端子部の基板と反対側の端部に絶縁性の樹脂層を介して半導体素子を載置する工程と、
内部接続部によって、半導体素子と内部端子部の内部端子面とを電気的に接続する工程と、
内部端子部、外部端子部、半導体素子、内部接続部および配線部を樹脂封止部によって封止する工程と、
基板を除去し、少なくとも外部端子部の外部端子面を露出させる工程と、
を備え、
前記一部の外部端子部以外の外部端子部は、半導体素子に対して平面方向外方に配置されることを特徴とする樹脂封止型半導体装置の製造方法。 - 樹脂封止部のうち外部端子部の外部端子面側に、当該外部端子面に対応する開口部を有する絶縁層を設ける工程と、
絶縁層の開口部に、外部端子部の外部端子面に接続される外部接続部を埋設する工程と、
をさらに備えたことを特徴とする請求項12に記載の樹脂封止型半導体装置の製造方法。 - 基板を除去して外部端子面を露出する工程は、エッチングにより基板を除去することを特徴とした請求項12又は13のいずれかに記載の樹脂封止型半導体装置の製造方法。
- 金属製の基板と、
基板上に平面状に配置され、基板側の端部が外部端子面を有する外部接続用めっき層からなる複数の外部端子部と、
基板上に平面状に配置され、基板に対して反対側の端部が内部端子面を有する内部接続用めっき層からなる複数の内部端子部と、
内部端子部と外部端子部とを基板上で平面状に接続する配線部と、を備え、
内部端子部、外部端子部および配線部の基板と接する部分はNi、Pd、Ag、Auのいずれかの金属であり、
外部端子部のうち外部接続用めっき層を除く部分の側面は、基板の法線方向に延在するとともに、外部接続用めっき層が形成されておらず、
内部端子部のうち内部接続用めっき層を除く部分の側面は、基板の法線方向に延在するとともに、内部接続用めっき層が形成されておらず、
一部の外部端子部は、基板上であって、半導体素子が配置される配置予定領域内に配置され、
前記一部の外部端子部以外の外部端子部は、基板上であって、配線予定領域外に配置されていることを特徴とする半導体装置用基板。 - 基板は、銅または銅合金からなり、
外部接続用めっき層および内部接続用めっき層の各々が、電解めっき法を用いて形成されることを特徴とする請求項15に記載の半導体装置用基板。 - 内部端子部は、基板上であって、半導体素子が配置される配線予定領域内および配置予定領域外の両方に配置されていることを特徴とする請求項15又は16のいずれかに記載の半導体装置用基板。
- 配置予定領域内に配置されている前記一部の外部端子部は、内部端子部に対して平面方向内方に配置され、
当該一部の外部端子部以外の外部端子部は、内部端子部に対して平面方向外方に配置され、
内部端子部は、外部端子部よりも大きさが小さくなっていることを特徴とする請求項15乃至17のいずれか1項に記載の樹脂封止型半導体装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7825514B2 (en) * | 2007-12-11 | 2010-11-02 | Dai Nippon Printing Co., Ltd. | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device |
US20110248392A1 (en) * | 2010-04-12 | 2011-10-13 | Texas Instruments Incorporated | Ball-Grid Array Device Having Chip Assembled on Half-Etched metal Leadframe |
JP5714361B2 (ja) * | 2011-03-01 | 2015-05-07 | 日本碍子株式会社 | 端子電極形成方法及びそれを用いた圧電/電歪素子の製造方法 |
CN102403282B (zh) * | 2011-11-22 | 2013-08-28 | 江苏长电科技股份有限公司 | 有基岛四面无引脚封装结构及其制造方法 |
CN102376656B (zh) * | 2011-11-28 | 2013-11-27 | 江苏长电科技股份有限公司 | 无基岛四面无引脚封装结构及其制造方法 |
JP6562495B2 (ja) * | 2014-12-26 | 2019-08-21 | 大口マテリアル株式会社 | 半導体装置の製造方法 |
JP2016122808A (ja) * | 2014-12-25 | 2016-07-07 | Shマテリアル株式会社 | 半導体装置用基板及びその製造方法 |
JP6562493B2 (ja) * | 2014-12-25 | 2019-08-21 | 大口マテリアル株式会社 | 半導体装置用基板及びその製造方法 |
JP6562494B2 (ja) * | 2014-12-26 | 2019-08-21 | 大口マテリアル株式会社 | 半導体装置の製造方法 |
KR102403960B1 (ko) | 2014-12-25 | 2022-05-30 | 오쿠치 마테리얼스 가부시키가이샤 | 반도체 장치용 기판, 반도체 장치용 배선부재 및 그 제조 방법 및 반도체 장치용 기판을 이용한 반도체 장치의 제조 방법 |
JP2016122807A (ja) * | 2014-12-25 | 2016-07-07 | Shマテリアル株式会社 | 半導体装置用基板及びその製造方法 |
JP2016122809A (ja) * | 2014-12-25 | 2016-07-07 | Shマテリアル株式会社 | 半導体装置用配線部材及びその製造方法 |
US9997439B2 (en) * | 2015-04-30 | 2018-06-12 | Qualcomm Incorporated | Method for fabricating an advanced routable quad flat no-lead package |
DE102016117389B4 (de) * | 2015-11-20 | 2020-05-28 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung |
JP6512609B2 (ja) | 2016-05-20 | 2019-05-15 | 大口マテリアル株式会社 | 多列型半導体装置用配線部材及びその製造方法 |
JP2017208516A (ja) | 2016-05-20 | 2017-11-24 | Shマテリアル株式会社 | 多列型半導体装置用配線部材及びその製造方法 |
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JP7039245B2 (ja) * | 2017-10-18 | 2022-03-22 | 新光電気工業株式会社 | リードフレーム及びその製造方法と電子部品装置 |
JP2022133486A (ja) * | 2019-07-30 | 2022-09-14 | 株式会社デンソー | 半導体パッケージおよび半導体装置 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07312404A (ja) * | 1994-05-18 | 1995-11-28 | Hitachi Ltd | 樹脂封止型半導体装置 |
JPH1126643A (ja) * | 1997-06-27 | 1999-01-29 | Nec Corp | 半導体装置 |
JPH1174404A (ja) * | 1997-08-28 | 1999-03-16 | Nec Corp | ボールグリッドアレイ型半導体装置 |
JPH11233683A (ja) * | 1998-02-10 | 1999-08-27 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材および樹脂封止型半導体装置の製造方法 |
JP2000208663A (ja) * | 1999-01-12 | 2000-07-28 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
DE10147376A1 (de) * | 2001-09-26 | 2003-04-24 | Infineon Technologies Ag | Elektronisches Bauteil und Systemträger sowie Verfahren zur Herstellung derselben |
JP2004119727A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2004179622A (ja) * | 2002-11-15 | 2004-06-24 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2004282098A (ja) * | 1994-03-18 | 2004-10-07 | Hitachi Chem Co Ltd | 半導体パッケージの製造方法 |
JP2007227961A (ja) * | 2007-04-20 | 2007-09-06 | Hitachi Chem Co Ltd | 半導体搭載基板とそれを用いた半導体パッケージ並びにそれらの製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208756A (ja) | 1983-05-12 | 1984-11-27 | Sony Corp | 半導体装置のパツケ−ジの製造方法 |
JP2002016181A (ja) | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP2002289739A (ja) | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 |
JP5259053B2 (ja) * | 2005-12-15 | 2013-08-07 | パナソニック株式会社 | 半導体装置および半導体装置の検査方法 |
JP5230997B2 (ja) * | 2007-11-26 | 2013-07-10 | 新光電気工業株式会社 | 半導体装置 |
US7825514B2 (en) * | 2007-12-11 | 2010-11-02 | Dai Nippon Printing Co., Ltd. | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device |
-
2008
- 2008-12-09 US US12/314,372 patent/US7825514B2/en active Active
- 2008-12-11 JP JP2008315805A patent/JP2009164594A/ja active Pending
-
2010
- 2010-09-28 US US12/923,569 patent/US7947598B2/en active Active
-
2012
- 2012-07-26 JP JP2012166130A patent/JP2012231176A/ja active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004282098A (ja) * | 1994-03-18 | 2004-10-07 | Hitachi Chem Co Ltd | 半導体パッケージの製造方法 |
JPH07312404A (ja) * | 1994-05-18 | 1995-11-28 | Hitachi Ltd | 樹脂封止型半導体装置 |
JPH1126643A (ja) * | 1997-06-27 | 1999-01-29 | Nec Corp | 半導体装置 |
JPH1174404A (ja) * | 1997-08-28 | 1999-03-16 | Nec Corp | ボールグリッドアレイ型半導体装置 |
JPH11233683A (ja) * | 1998-02-10 | 1999-08-27 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材および樹脂封止型半導体装置の製造方法 |
JP2000208663A (ja) * | 1999-01-12 | 2000-07-28 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
DE10147376A1 (de) * | 2001-09-26 | 2003-04-24 | Infineon Technologies Ag | Elektronisches Bauteil und Systemträger sowie Verfahren zur Herstellung derselben |
JP2004119727A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2004179622A (ja) * | 2002-11-15 | 2004-06-24 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2007227961A (ja) * | 2007-04-20 | 2007-09-06 | Hitachi Chem Co Ltd | 半導体搭載基板とそれを用いた半導体パッケージ並びにそれらの製造方法 |
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