CN1050699C - 快速电可擦可编程只读存储器单元及其制造方法 - Google Patents

快速电可擦可编程只读存储器单元及其制造方法 Download PDF

Info

Publication number
CN1050699C
CN1050699C CN96107224A CN96107224A CN1050699C CN 1050699 C CN1050699 C CN 1050699C CN 96107224 A CN96107224 A CN 96107224A CN 96107224 A CN96107224 A CN 96107224A CN 1050699 C CN1050699 C CN 1050699C
Authority
CN
China
Prior art keywords
floating boom
deielectric
polysilicon
silicon chip
floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96107224A
Other languages
English (en)
Other versions
CN1145534A (zh
Inventor
蒋尚焕
韩星英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1145534A publication Critical patent/CN1145534A/zh
Application granted granted Critical
Publication of CN1050699C publication Critical patent/CN1050699C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5612—Multilevel memory cell with more than one floating gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明涉及一种快速EEPROM(电可擦可编程只读存贮器)单元及其制造方法，特别地，通过根据两个浮栅是否被编程或删除而使有效沟道长度改变以及偏置连接，使得这种EEPROM单元具有三种不同的输出电平，其中两个浮栅形成于沟道区中。

Description

快速电可擦可编程只读存储器单元及其制造方法
本发明涉及一种快速EEPROM(电可擦可编程只读存贮器)单元及其制造方法，特别地，通过根据两个浮栅是否被编程或删除而使有效沟道长度改变以及偏置连接，而使得这种EEPROM单元具有三种不同的输出电平，其中两个浮栅形成于沟道区中。
具有编程和电可擦功能的EEPROM半导体器件由于其独特的优点而已在市场上被广泛地接受。但是，EEPROM器件的每位生产成本较高，因而，通过增加单元的集成度来降低成本。这样，由于与DRAM单元相比，EEPROM单元具有相对复杂的结构，因此，在集成EEPROM单元时存在许多困难。
因此，本发明的一个目的是提供一种EEPROM单元及其制造方法以解决上述问题，其方法就是通过根据两个浮栅是否被编程或删除而使有效沟道长度改变以及偏置连接，而获得三种不同的输出电平。
为了实现上述目的，根据本发明的一个EEPROM单元包括第一和第二浮栅，从硅基片上通过下面的隧道氧化膜而使二者电绝缘，并且二者在形成时是相互平行地相邻，还包括一个介质膜垫片，此垫片位于第一浮栅和第二浮栅之间，还包括一个在第一浮栅和第二浮栅之上形成的控制栅极，其中此控制栅极与第一浮栅和第二浮栅之间电绝缘，还包括一个源区和一个漏区，它们在硅基片上形成并且与上述两个浮栅的两端的一部分重叠。
一种制造EEPROM单元的方法，包括下列步骤：在硅基片上形成第一隧道氧化膜，形成第一多晶硅图形以确定第一浮栅的宽度和一边，在第一多晶硅图形的壁上形成一个介质膜垫片，在已产生的结构上形成第二隧道氧化物，在与第一多晶硅图形平行的位置上形成第二多晶硅图形以确定第二浮栅的宽度和一边，然后形成一介质膜和第三多晶硅膜，通过采用控制栅的掩膜而蚀刻第三多晶硅膜形成一控制栅极，其中第一和第二多晶硅图形的其它边被连续地蚀刻，在硅基片上采用离子注入处理而形成一个源区和一个漏区。
为了更充分地理解本发明的原理和目的，下面的详细描述中将参考的附图为：
图1A和1D表示了根据本发明制造的快速EEPROM单元的剖面图；
图2是1B的一个顶视图；以及
图3A和3C是一个器件的剖面图，此器件用于解释根据本发明的快速EEPROM的操作。
在上面的几个附图中，相似的参考序号涉及相似的部分。
图1A至图1D是说明根据本发明的快速EEPROM单元的制造方法的一个器件的剖面图；
在图1A中，第一隧道氧化物(2)和第一多晶硅膜在硅基片(1)上顺序地形成，构图第一多晶硅以确定第一浮栅的宽度和一边，因而形成第一多晶硅图形(3)。一介质膜垫片(4)在第一多晶硅图形(3)的一个蚀刻的壁上形成。此第一多晶硅图形(3)在一有源区(A)中形成，如图1所示。
参考图1B，在形成介质膜垫片后产生的结构上，顺序地形成第二隧道氧化物(5)和第二多晶硅，并且第二多晶硅被构图以确定第二浮栅的宽度和一边，从而形成第二多晶硅图形(6)。并且图1B也是图2所示的沿X-X’线的剖面图。如图2所示，第二多晶硅图形(6)形成在除了形成有第一多晶硅图形(3)的区域的有源区的剩余区域，其中的由第二多晶硅图形(6)确定的一边与由第一多晶硅图形确定的一边重叠。第一和第二多晶硅图形(3和6)延伸到场区(B)而完全覆盖住有源区(A)。
如图1C所示，介质膜(7)和第三多晶硅膜顺序地淀积。
在图1D中，通过用控制栅的掩模(未示出)蚀刻第三多晶硅膜(8)而形成控制栅极(8A)。同时，通过采用控制栅的掩模自对准蚀刻方法顺序地蚀刻介质膜(7)、第二多晶硅图形(6)、第二隧道氧化物(5)、第一多晶硅图形(3)和第一隧道氧化物(2)。然后通过离子注入处理而在硅基片(1)中形成源和漏(10和9)。如上所述，通过采用控制栅掩模的自对准蚀刻方法，第一和第二多晶硅图形(3和6)的其它边被确定，从而变成与有源区(A)平行的相邻的第一和第二浮栅(3A和6A)。
本发明的优点如下。由于金属氧化物半导体(MOS)晶体管的饱和电流随着其沟道长度的变化而变化，当有效沟道长度改变时，其饱和电流相应地变化，使得不同的饱和电流可以用于不同的逻辑电平。本发明能够提供三种不同的输出电平。例如，在一般的设计中，为了得到八种不同的输出，需要三个单元。而根据本发明仅仅需要两个单元应可得到九个不同的输出，因此器件的集成度可大大增加。
现在参考图3A至图3C，这些图中显示了上述的利用本技术原理制造快速EEPROM单元的操作。
为了对单元编程，即在浮栅中存储电荷，一个地电位加到源(10)和漏(9)并且一个约+12V的高电压设置到控制栅极(8A)。然后对第一和第二浮栅(3A和6A)顺序地编程。在擦除操作中，当源(10)和漏(9)设置为5V并且控制栅极(8A)设置成-12V时，存储在第一和第二浮栅(3A和6A)中的电荷通过隧道效应引出，如图3C所示。为了用类似的方法对第一或第二浮栅(3A和6A)的其中一个浮栅编程，在用与图3A所示的同样的方法对第一和第二浮栅(3A和6A)编程后，设置源(10)，漏(9)和控制栅极(8A)和分别为0V，5V和-12V，从而使第一浮栅(3A)被擦除，如图3B所示。反之，擦除第二浮栅(6A)是可能的。
如上所述，读入的编程数据的情况分成三种类型，(1)两个浮栅都被编程的情况，(2)一个浮栅被编程时另一浮栅被擦除，(3)两个浮栅都被擦除。
对于上述三种类型，第二种类型(例如，在这种情况下假设所述的第一浮栅(3A)被擦除)的读操作将在下面说明。
如果Vtp(第一种类型的阈值电压)被加到控制栅极(8A)，那么在第一浮栅(3A)下的一个沟道会转换而足够形成一个实际的漏。这样，此实际的漏产生同样的作用，即沟道长度减少到与第一浮栅的长度一样，使得与第一种类型相比，饱和电流更大。因此，采用本发明的原理，具有三种不同的输出的快速EEPROM单元可以采用上述的三种类型而实现。
如上所述，当采用本发明时，随着沟道长度的变化可获得不同的饱和电流，并且能够产生三种不同的输出电平，从而使得在增加器件的集成度而不增加费用方面具有显著的作用。
尽管在最佳实施例的描述中采用了一些特例，但是前面的描述仅仅用于说明本发明的原理，不难理解的是本发明不应限制在这里所说明和公开的最佳实施例。因此，根据本发明的精神而作的所有变化都包括在本发明的其它实施例中。

Claims (3)

1.一种快速EEPROM单元，包括：
第一浮栅，由第一隧道氧化膜与硅基片电绝缘；
第二浮栅，由第二隧道氧化膜与所述硅基片电绝缘，该第二浮栅靠近且平行于所述第一浮栅，第二浮栅的一边与第一浮栅的一边重叠；
一介质膜垫片，形成在所述第一浮栅和第二浮栅之间；
一介质膜，形成在所述第一浮栅和第二浮栅上；
一控制栅极，形成在所述第一浮栅和第二浮栅之上，其中该控制栅极与所述第一和第二浮栅之间由所述介质膜电绝缘；
一个源区，形成在所述硅基片中，并且与所述第一浮栅另一边的一部分重叠；以及
一个漏区，形成在所述硅基片中，并且与所述第二浮栅另一边的一部分重叠。
2.一种制造EEPROM单元的方法，包括如下步骤：
在硅基片上形成第一隧道氧化膜；
形成第一多晶硅图形以确定第一浮栅的宽度和一边；
在第一多晶硅图形的壁上形成一介质膜垫片；
在形成所述介质膜垫片后产生的结构上形成第二隧道氧化物；
在与第一多晶硅图形平行的位置上形成第二多晶硅图形以确定第二浮栅的宽度和一边；
顺序地形成一介质膜和第三多晶硅膜；
通过采用掩模而蚀刻第三多晶硅膜形成一控制栅极，其中第一和第二多晶硅图形的其它边被连续地蚀刻；并且
在硅基片上采用离子注入处理而形成一个源区和一个漏区。
3.如权利要求2所述的方法，其特征在于，所述第二浮栅的一边与所述第一浮栅的一边重叠。
CN96107224A 1995-03-22 1996-03-22 快速电可擦可编程只读存储器单元及其制造方法 Expired - Fee Related CN1050699C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR6086/95 1995-03-22
KR1019950006086A KR0142604B1 (ko) 1995-03-22 1995-03-22 플래쉬 이이피롬 셀 및 그 제조방법

Publications (2)

Publication Number Publication Date
CN1145534A CN1145534A (zh) 1997-03-19
CN1050699C true CN1050699C (zh) 2000-03-22

Family

ID=19410344

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96107224A Expired - Fee Related CN1050699C (zh) 1995-03-22 1996-03-22 快速电可擦可编程只读存储器单元及其制造方法

Country Status (6)

Country Link
US (1) US5674768A (zh)
KR (1) KR0142604B1 (zh)
CN (1) CN1050699C (zh)
DE (1) DE19611438B4 (zh)
GB (1) GB2299449B (zh)
TW (1) TW300340B (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0870054A (ja) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100187656B1 (ko) * 1995-05-16 1999-06-01 김주용 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법
JP2910647B2 (ja) * 1995-12-18 1999-06-23 日本電気株式会社 不揮発性半導体記憶装置の製造方法
DE19614011C2 (de) 1996-04-09 2002-06-13 Infineon Technologies Ag Halbleiterbauelement, bei dem die Tunnelgateelektrode und die Kanalgateelektrode an der Grenzfläche zum Tunneldielektrikum bzw. Gatedielektrikum durch eine Isolationsstruktur unterbrochen sind
JP2870478B2 (ja) * 1996-04-25 1999-03-17 日本電気株式会社 不揮発性半導体記憶装置及びその動作方法
US5658814A (en) * 1996-07-09 1997-08-19 Micron Technology, Inc. Method of forming a line of high density floating gate transistors
US5714412A (en) * 1996-12-02 1998-02-03 Taiwan Semiconductor Manufacturing Company, Ltd Multi-level, split-gate, flash memory cell and method of manufacture thereof
US5963806A (en) 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US5963824A (en) * 1997-07-09 1999-10-05 Advanced Micro Devices, Inc. Method of making a semiconductor device with adjustable threshold voltage
KR100451491B1 (ko) * 1997-12-08 2005-04-06 주식회사 하이닉스반도체 플래쉬이이피롬셀및그의제조방법
TW363230B (en) * 1997-12-26 1999-07-01 Taiwan Semiconductor Mfg Co Ltd Manufacturing method for the flash memory cell with split-gate
US6243289B1 (en) * 1998-04-08 2001-06-05 Micron Technology Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
KR100316709B1 (ko) * 1998-07-13 2001-12-12 윤종용 불휘발성 메모리 장치 제조 방법
KR20000043886A (ko) * 1998-12-29 2000-07-15 김영환 멀티 비트 플래쉬 메모리 셀, 그 제조 방법 및 구동 방법
US6376868B1 (en) 1999-06-15 2002-04-23 Micron Technology, Inc. Multi-layered gate for a CMOS imager
KR100298586B1 (ko) * 1999-07-13 2001-11-01 윤종용 비휘발성 메모리 소자
DE19941684B4 (de) * 1999-09-01 2004-08-26 Infineon Technologies Ag Halbleiterbauelement als Verzögerungselement
KR100387267B1 (ko) * 1999-12-22 2003-06-11 주식회사 하이닉스반도체 멀티 레벨 플래쉬 이이피롬 셀 및 그 제조 방법
US6482700B2 (en) * 2000-11-29 2002-11-19 Taiwan Semiconductor Manufacturing Co., Ltd Split gate field effect transistor (FET) device with enhanced electrode registration and method for fabrication thereof
DE10106804A1 (de) * 2001-02-14 2002-09-05 Infineon Technologies Ag Informationsredundante nichtflüchtige Halbleiterspeicherzelle sowie Verfahren zu deren Herstellung und Programmierung
US6624027B1 (en) * 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers
US6911370B2 (en) * 2002-05-24 2005-06-28 Hynix Semiconductor, Inc. Flash memory device having poly spacers
KR100466197B1 (ko) * 2002-07-18 2005-01-13 주식회사 하이닉스반도체 플래시 메모리 셀 및 그 제조방법
US6897533B1 (en) * 2002-09-18 2005-05-24 Advanced Micro Devices, Inc. Multi-bit silicon nitride charge-trapping non-volatile memory cell
KR100937651B1 (ko) * 2002-12-31 2010-01-19 동부일렉트로닉스 주식회사 반도체 장치 및 이의 제조 방법
KR20060097884A (ko) 2005-03-07 2006-09-18 삼성전자주식회사 스플리트 게이트형 비휘발성 메모리 소자 및 그 형성 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4988635A (en) * 1988-06-07 1991-01-29 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing non-volatile semiconductor memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS622662A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体装置およびその製造方法
JPS62109367A (ja) * 1985-11-07 1987-05-20 Toshiba Corp 半導体記憶装置
JPS63278275A (ja) * 1987-05-08 1988-11-15 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
JPH07120721B2 (ja) * 1988-02-19 1995-12-20 三菱電機株式会社 不揮発性半導体記憶装置
JP2600301B2 (ja) * 1988-06-28 1997-04-16 三菱電機株式会社 半導体記憶装置およびその製造方法
US5036378A (en) * 1989-11-01 1991-07-30 At&T Bell Laboratories Memory device
JPH03245575A (ja) * 1990-02-22 1991-11-01 Mitsubishi Electric Corp 半導体記憶装置及びその製造方法
US5045491A (en) * 1990-09-28 1991-09-03 Texas Instruments Incorporated Method of making a nonvolatile memory array having cells with separate program and erase regions
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
JPH06150369A (ja) * 1992-11-10 1994-05-31 Pioneer Electron Corp 光記録媒体
JPH06345863A (ja) * 1993-06-10 1994-12-20 Mitsubishi Kasei Corp 液晶性ポリエステルアミド
US5596529A (en) * 1993-11-30 1997-01-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US5429969A (en) * 1994-05-31 1995-07-04 Motorola, Inc. Process for forming electrically programmable read-only memory cell with a merged select/control gate
US5429971A (en) * 1994-10-03 1995-07-04 United Microelectronics Corporation Method of making single bit erase flash EEPROM

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4988635A (en) * 1988-06-07 1991-01-29 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing non-volatile semiconductor memory device

Also Published As

Publication number Publication date
KR960036090A (ko) 1996-10-28
KR0142604B1 (ko) 1998-07-01
GB2299449A (en) 1996-10-02
CN1145534A (zh) 1997-03-19
GB9605768D0 (en) 1996-05-22
DE19611438A1 (de) 1996-09-26
DE19611438B4 (de) 2006-01-12
TW300340B (zh) 1997-03-11
GB2299449B (en) 1999-04-14
US5674768A (en) 1997-10-07

Similar Documents

Publication Publication Date Title
CN1050699C (zh) 快速电可擦可编程只读存储器单元及其制造方法
US6266278B1 (en) Dual floating gate EEPROM cell array with steering gates shared adjacent cells
US5412238A (en) Source-coupling, split-gate, virtual ground flash EEPROM array
US6091633A (en) Memory array architecture utilizing global bit lines shared by multiple cells
US5583811A (en) Transistor structure for erasable and programmable semiconductor memory devices
EP0495492B1 (en) Non-volatile memory cell structure and process for forming same
CN1230786A (zh) 多阶快闪存储器结构及其制造方法
JPH08340095A (ja) メモリ・アレイの製作方法、プログラム方法及びメモリ・アレイ
US5371030A (en) Method of fabricating field oxide isolation for a contactless flash EPROM cell array
JPS6311784B2 (zh)
CN1277314C (zh) 互补非易失性存储电路
KR100286728B1 (ko) 비휘발성반도체메모리장치
KR100358070B1 (ko) 멀티 비트 플래쉬 메모리 셀 및 이를 이용한 프로그램 방법
US5461249A (en) Nonvolatile semiconductor memory device and manufacturing method therefor
CN1199189C (zh) 在非易失性半导体存储器件中擦除数据的方法
CN1407614A (zh) 程序化及抹除p型信道sonos记忆单元的操作方法
KR100660904B1 (ko) 단일 게이트 구조를 갖는 ｅｅｐｒｏｍ의 프로그래밍 방법
JP3474614B2 (ja) 不揮発性半導体メモリ装置及びその動作方法
KR100387267B1 (ko) 멀티 레벨 플래쉬 이이피롬 셀 및 그 제조 방법
JPH0629552A (ja) 電気的にプログラム可能な１トランジスタ形ｉｃメモリ
KR100241524B1 (ko) 플래쉬 메모리 셀
CN100359603C (zh) 具有多阶输出电流的非易失存储器编程、读取与擦除方法
CN1146912C (zh) 擦除闪速存储器的方法
KR100199380B1 (ko) 플래쉬 이이피롬 셀
Van Houdt et al. Optimization of a submicron HIMOS Flash E 2 PROM cell for implementation in a virtual ground array configuration

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20000322

Termination date: 20130322