CN104956482A - 用于光子及电子结构的半导体衬底及制造方法 - Google Patents

用于光子及电子结构的半导体衬底及制造方法 Download PDF

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CN104956482A
CN104956482A CN201380068593.9A CN201380068593A CN104956482A CN 104956482 A CN104956482 A CN 104956482A CN 201380068593 A CN201380068593 A CN 201380068593A CN 104956482 A CN104956482 A CN 104956482A
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trench isolation
isolation region
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CN104956482B (zh
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罗伊·米迪
古尔特杰·桑胡
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Micron Technology Inc
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Abstract

本发明提供一种形成具有适合于集成电子及光子装置的隔离区域的衬底的方法。使用共同中间掩模及光刻技术来制造界定用于在衬底中蚀刻第一及第二区域的开口的掩模，其中用于所述第二沟槽隔离区域的所述开口比用于所述第一沟槽隔离区域的所述开口宽。通过所述掩模在所述衬底中蚀刻且用氧化物材料填充所述第一及第二沟槽隔离区域。从所述第二沟槽隔离区域的底部移除所述氧化物材料。将所述第二沟槽隔离区域进一步蚀刻为比所述第一沟槽隔离区域深，且接着用氧化物材料填充所述第二沟槽隔离区域。可在所述衬底上形成且由所述第一沟槽隔离区域电隔离电装置，且可在所述第二沟槽隔离区域上方形成光子装置且使所述光子装置与所述衬底光学上隔离。

Description

用于光子及电子结构的半导体衬底及制造方法
技术领域
本文中描述的实施例涉及一种共同半导体衬底及其形成方法，所述衬底及方法使在所述衬底上所制造的电子装置与光子装置隔离。
背景技术
当前趋向于在同一半导体衬底上集成光子装置及电子装置。绝缘体上硅(SOI)衬底可用作用于此类集成的支撑衬底。然而，与电子装置的电隔离通常所需要的较薄埋式氧化物(BOX)相比较，光子结构(例如建造在SOI衬底上方的波导)通常在SOI衬底中需要厚BOX以用于光学隔离。举例来说，为了防止光子波导芯与BOX下方的支撑硅的渐消型耦合，BOX材料必须相对厚，例如，大于1.0μm且常常为2.0μm到3.0μm厚。当BOX材料具有此类厚度时，其抑制到下层硅的热流动，所述下层硅充当用于电子装置及光子装置两者的热耗散器。比较起来，当某些电子装置(例如，高速逻辑电路)与光子装置集成在同一SOI衬底上时，SOI衬底的BOX应薄得多，例如，在100nm到200nm的范围内。虽然此类BOX绝缘体为电子装置提供良好的SOI衬底，但其不足以防止波导芯与SOI衬底的下层支撑硅的光学耦合，这造成不理想的光学信号损失。因此，需要复杂多掩模过程来提供具有合适电及光学隔离的SOI衬底或非SOI衬底，所述电及光学隔离在用于电子装置及光子装置的衬底的不同区域中具有不同深度。
此外，虽然SOI衬底常常用于在同一衬底上制造电子装置及光子装置，但与非SOI衬底相比较，SOI衬底生产起来是相对昂贵的，且还常常可具有有限供应量。
因此，需要简化方法来提供具有用于隔离电子装置及光子装置的具有不同深度的隔离区域的共同半导体衬底。
附图说明
图1为根据本发明的实施例的展示早期制造阶段的硅衬底的横截面图；
图2为在图1所展示的制造阶段之后的制造阶段时的衬底的横截面图；
图3为在图2所展示的制造阶段之后的制造阶段时的衬底的横截面图；
图4为在图3所展示的制造阶段之后的制造阶段时的衬底的横截面图；
图5为在图4所展示的制造阶段之后的制造阶段时的衬底的横截面图；
图6为在图5所展示的制造阶段之后的制造阶段时的衬底的横截面图；
图7为在图6所展示的制造阶段之后的制造阶段时的衬底的横截面图；及
图8说明在形成深沟槽时的沟槽的宽度与侧壁的宽度之间的关系。
具体实施方式
在以下详细描述中，参考形成详细描述的部分且其中作为说明而展示可实践的特定实施例的随附图式。充分详细地描述这些实施例以使所属领域的技术人员能够制造及使用这些实施例，且应理解，可在不脱离本发明的精神及范围的情况下对所揭示的特定实施例作出结构、逻辑或程序上改变。
本文中描述的实施例提供一种用于形成半导体衬底结构的简化方法，可在所述半导体衬底结构上形成光子装置及电子电路，其中浅沟槽电隔离用于电子装置且深沟槽光学隔离用于光子装置，例如，波导、检测器、分接头、分离器、调制器、解调器及其它光子装置。
所描述的实施例使用共同中间掩模来形成具有第一及第二沟槽隔离区域开口的共同蚀刻掩模。所述第二沟槽隔离区域开口比所述第一沟槽隔离区域开口宽。掩模界定的第一及第二沟槽隔离区域开口用以在半导体衬底中分别蚀刻第一及第二沟槽。最初将所述第一及第二沟槽蚀刻为相同深度且用氧化物填充所述第一及第二沟槽。所述氧化物完全地填充所述第一较窄沟槽且部分地填充所述第二较宽沟槽。从第二沟槽的底部移除所述氧化物且接着进一步蚀刻所述第二沟槽，使得其比所述第一沟槽深，此后用氧化物填充所述第二沟槽。接着平面化所述衬底，且所述衬底在其中具有浅沟槽隔离区及深沟槽隔离区两者。可在不具有绝缘体上硅构造的半导体衬底中形成所述隔离区。在所述衬底的具有提供电绝缘的浅隔离沟槽的区域中制造电子装置。在提供光子装置与下层衬底之间的光学绝缘的深沟槽隔离区上方制造光子装置。
现在参看图1到7描述实施例。图1说明在沟槽隔离形成的早期阶段时的半导体(例如，硅或多晶硅)衬底101。将垫氧化物103(例如，二氧化硅)生长或沉积在衬底101的上表面上以保护所述衬底免受随后形成的硬掩模105的影响。将由(例如)氮化硅形成的硬掩模105沉积在垫氧化物103上方。如图2所展示，可与单一中间掩模一起使用光刻技术来图案化硬掩模105，使得硬掩模105具有用于蚀刻用于形成浅沟槽隔离区的第一沟槽107的第一较窄开口及用于蚀刻用于形成较深沟槽隔离区的第二沟槽109的第二较宽开口。用于蚀刻沟槽107的第一开口可各自为约20nm到约150nm宽。第二沟槽109可为约2μm到10μm宽。因为第二沟槽109将用以隔离由具有包层的硅形成的光子装置(例如，波导/二氧化硅(例如，二氧化硅))，所以掩模105的第二开口可针对约300nm到约2μm的光子装置宽度具有在约2μm到约4μm的范围内的宽度。湿蚀刻或干蚀刻可用以通过经图案化的硬掩模105中的第一及第二开口在硅衬底101中共同地蚀刻第一沟槽107及第二沟槽109。经蚀刻的沟槽107、109将具有对应于硬掩模105中的第一及第二开口的宽度的宽度。经蚀刻的沟槽107及109的深度可为约200nm到约300nm。
一旦蚀刻第一沟槽107及第二沟槽109(如图2所展示)，就在衬底101上方沉积及/或在衬底101上生长薄沟槽隔离氧化物111(例如，二氧化硅)以填充第一沟槽107及第二沟槽109且覆盖硬掩模105，如图3所展示。所述氧化物可具有为所述沟槽的深度的约一半的厚度，例如约100nm到约150nm。如图4所展示，较窄的第一沟槽107由氧化物111完全地填充，而较宽的第二沟槽由氧化物111部分地填充。
如图4所展示，接着可将氧化物111平面化到硬掩模105的水平，且接着可使用各向异性湿蚀刻或等离子干蚀刻从第二沟槽109的底部112选择性地移除氧化物111，从而在沟槽109的侧壁处留下氧化物111的小部分作为侧壁间隔物111a。沟槽107的宽度应使得从第二沟槽的底部112移除氧化物会使沟槽107至少部分地(而非完全地)填充有氧化物。这种蚀刻暴露衬底101以用于对沟槽109的进一步蚀刻。
图8说明沟槽的宽度W与侧壁间隔物(111a)的宽度w之间的关系，所述关系可用以实现硅衬底101的暴露。当W>2w时，通过沟槽109暴露衬底101以用于进一步蚀刻。因此，在一个实例中，如果侧壁间隔物宽度w为100nm，那么第二沟槽109可具有至少200nm的宽度w以确保衬底101的暴露。相反地，如果W<2w，那么将不充分地蚀刻氧化物111以暴露衬底101。
应注意，侧壁间隔物111a为在第二沟槽109处移除氧化物111的人造物。取决于选定的湿蚀刻及/或干蚀刻条件，可在蚀刻期间完全地移除侧壁间隔物111a以暴露衬底101。
如图5所展示，可使用侧壁氧化物间隔物111a(如果存在)及硬掩模105的第二开口作为蚀刻掩模在第二沟槽109上执行不干扰氧化物111的进一步各向异性湿蚀刻或等离子干蚀刻，以将第二沟槽109蚀刻到比第一沟槽107的深度深的深度，例如，蚀刻到为第一沟槽107的深度的至少两倍的深度。对于光子装置隔离，第二沟槽109的深度可在约1.2μm到1.5μm的范围内。如果不存在侧壁氧化物间隔物111a，那么这种进一步蚀刻由硬掩模105的第二开口单独地界定。
在以关于图5所描述的方式进一步蚀刻第二沟槽109之后，可在衬底101上方沉积第二氧化物(例如，二氧化硅)以填充第二沟槽109，此后使用CMP或其它已知平面化技术将整个结构平面化到衬底101的表面，以移除衬底101的表面上方的氧化物以及氧化物垫103及硬掩模105。替代地，可通过磷酸衬底蚀刻来移除氧化物硬掩模105及垫氧化物103。在图6中说明所得的经平面化结构。
图6的衬底101具有用于电隔离随后制造的电子装置的浅第一沟槽隔离区113，及用以光学上隔离在其上方制造的光子装置与半导体衬底101的第二较深沟槽隔离区115。图6的衬底可用于在同一衬底101上制造CMOS电路及光子装置及电路两者。图6还展示表示衬底101上的其中可形成CMOS装置及电路以及光子装置及电路的相应区域的虚线114。
图7展示部分制造的CMOS/光子集成电路结构的实例。半导体衬底101具有晶体管117，晶体管117具有掺杂源极区119及漏极区121以及在栅极氧化物125上方的栅极123，及栅极氧化物125上所制造的栅极氧化物侧壁129。浅第一沟槽隔离区域113隔离晶体管117与衬底101上所制造的其它电子装置。图7还展示被形成为硅波导芯131的光子装置，硅波导芯131在隔离较深沟槽隔离区115上方及上。波导芯131要求周围包层具有低于硅的折射率，其为约3.47。这个包层在波导芯131的任一侧上且在波导131上方由第二较深沟槽隔离区115且由氧化物材料133提供。具有第二沟槽区域115的氧化物及围绕波导芯131的氧化物具有(例如)约1.54的折射率。还可使用具有其它折射率的其它材料。氧化物材料133可为二氧化硅或BPSG氧化物材料133，所述材料还可用作与用以电互连衬底10上所制造的电子装置及光子装置的一或多个金属层135相关联的层间电介质(ILD)结构的一部分。
所描述的实施例提供一种形成具有适合于在同一衬底上集成电子装置及光子装置两者的浅沟槽隔离区及深沟槽隔离区的非SOI衬底的方法，所述方法使用单一中间掩模以形成用于蚀刻的硬掩模结构。
虽然上文描述了方法及结构的实例实施例，但此类描述不应被认作限制本发明，这是因为可在不脱离本发明的精神或范围的情况下作出各种修改。因此，本发明仅受到所附权利要求书的范围限制。

Claims (24)

1.一种在半导体衬底中形成具有不同深度的隔离区的方法，所述方法包括：
在半导体衬底上方形成蚀刻掩模材料；
在光刻过程中使用单一中间掩模来图案化所述蚀刻掩模材料以界定用于形成第一及第二沟槽隔离区域的第一及第二开口，所述第二开口比所述第一开口宽；
使用所述经图案化的蚀刻掩模材料在所述半导体衬底中蚀刻第一及第二沟槽隔离区域；
在所述第一及第二沟槽隔离区域中的每一者内形成隔离材料；
在所述第二沟槽隔离区域的底部处移除隔离材料以暴露所述半导体衬底，同时在所述第一沟槽隔离区域中留下沟槽隔离材料；
在所述第二沟槽隔离区域处进一步蚀刻所述经暴露的半导体衬底，使得所述第二沟槽隔离区域的深度超过所述第一沟槽隔离区域的深度；
在所述较深的第二沟槽隔离区域内形成沟槽隔离材料；
在所述衬底上形成由第一沟槽隔离区域电隔离的电子装置；及，
在所述第二沟槽隔离区域内的所述沟槽隔离材料上方形成光子装置，使得所述光子装置与所述衬底光学上隔离。
2.根据权利要求1所述的方法，其中对所述第一及第二沟槽隔离区域的蚀刻在所述第二沟槽隔离区域的侧壁上留下隔离材料，所述隔离材料形成用于所述进一步蚀刻的蚀刻掩模。
3.根据权利要求1所述的方法，其进一步包括在所述较深的第二隔离区域内形成所述沟槽隔离材料之后平面化到所述衬底的上表面的水平。
4.根据权利要求3所述的方法，其中所述半导体衬底包括硅衬底。
5.根据权利要求3所述的方法，其进一步包括在所述蚀刻掩模材料与衬底之间形成垫氧化物，其中所述单一中间掩模及光刻过程图案化所述蚀刻掩模材料及垫氧化物。
6.根据权利要求5所述的方法，其中所述垫氧化物包括二氧化硅。
7.根据权利要求1所述的方法，其中所述蚀刻掩模材料包括氮化硅。
8.根据权利要求1所述的方法，其中所述沟槽隔离材料包括二氧化硅。
9.根据权利要求1所述的方法，其中各向异性地蚀刻所述第二沟槽隔离区域内的所述隔离材料来移除所述沟槽隔离材料以暴露所述半导体衬底，使得所述沟槽隔离材料的一部分余留在所述第二沟槽隔离区域的所述侧壁处且用作用于对所述经暴露的半导体衬底的所述进一步蚀刻的掩模。
10.根据权利要求1所述的方法，其中以各向异性蚀刻从所述第二沟槽隔离区域移除所述隔离材料。
11.根据权利要求1所述的方法，其中以等离子蚀刻从所述第二沟槽隔离区域移除所述隔离材料。
12.根据权利要求1所述的方法，其中所述进一步蚀刻产生第二沟槽隔离区域，所述第二沟槽隔离区域的深度为所述第一沟槽隔离区域的至少两倍。
13.根据权利要求12所述的方法，其中所述第一沟槽隔离区域为约200nm到约300nm深。
14.根据权利要求12所述的方法，其中所述第二沟槽隔离区域为约1.2μm到约1.5μm深。
15.根据权利要求1所述的方法，其中所述第二沟槽隔离区域的宽度比所述第一沟槽隔离区域的宽度宽。
16.根据权利要求2所述的方法，其中所述第二沟槽隔离区域的所述宽度大于所述第二沟槽侧壁隔离材料的宽度的两倍。
17.一种形成电路结构的方法，所述方法包括：
在光刻过程中使用单一中间掩模来图案化半导体衬底上方所提供的蚀刻掩模，所述图案界定用于在所述衬底中蚀刻第一及第二沟槽隔离区域的开口，用于蚀刻所述第二沟槽隔离区域的所述开口比用于蚀刻所述第一沟槽隔离区域的所述开口宽；
在所述蚀刻掩模中使用所述第一及第二开口从所述衬底移除半导体材料以提供所述第一及第二沟槽隔离区域；
在所述第一及第二沟槽隔离区域内提供电介质材料；
从所述第二沟槽隔离区域移除所述电介质材料以暴露所述衬底；
进一步蚀刻所述经暴露的衬底，使得所述第二沟槽隔离区域比所述第一沟槽隔离区域深；
用电介质材料填充所述第二较深沟槽隔离区域；
将所述第一及第二沟槽隔离区域平面化到所述衬底的水平；
在所述衬底上形成由所述第一沟槽区域电隔离的电子装置；及
在所述经平面化的第二沟槽隔离区域上形成光子装置。
18.根据权利要求19所述的方法，其中所述第一沟槽隔离区域具有约20nm到约150nm的宽度。
19.根据权利要求17所述的方法，其中所述第二沟槽隔离区域具有约2μm到约10μm的宽度。
20.根据权利要求19所述的方法，其中所述第二沟槽隔离区域具有约2μm到约4μm的宽度。
21.根据权利要求17所述的方法，其中将所述第二沟槽隔离区域的深度蚀刻为所述第一沟槽隔离区域的至少两倍。
22.根据权利要求17所述的方法，其进一步包括在侧上且在所述光子装置上方制造光学隔离区域。
23.根据权利要求17所述的方法，其中所述光子装置是选自由波导、检测器、分接头、分离器、调制器及解调器组成的群组。
24.根据权利要求22所述的方法，其中所述光子装置上方的光学绝缘为层间电介质结构的一部分。
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JP6144777B2 (ja) 2017-06-07
EP2939266A1 (en) 2015-11-04
US9305826B2 (en) 2016-04-05
TW201432786A (zh) 2014-08-16
US20140341503A1 (en) 2014-11-20
US20140175596A1 (en) 2014-06-26
EP2939266B1 (en) 2016-12-21
US20150243546A1 (en) 2015-08-27
US8652934B1 (en) 2014-02-18
US9034724B2 (en) 2015-05-19
CN104956482B (zh) 2019-04-09
JP2016507894A (ja) 2016-03-10
KR20150092284A (ko) 2015-08-12
WO2014105319A1 (en) 2014-07-03

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