TW201432786A - 用於光電結構之半導體基板及製造方法 - Google Patents

用於光電結構之半導體基板及製造方法 Download PDF

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TW201432786A
TW201432786A TW102145181A TW102145181A TW201432786A TW 201432786 A TW201432786 A TW 201432786A TW 102145181 A TW102145181 A TW 102145181A TW 102145181 A TW102145181 A TW 102145181A TW 201432786 A TW201432786 A TW 201432786A
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trench isolation
isolation regions
substrate
trench
regions
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Roy Meade
Gurtej Sandhu
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/1225—Basic optical elements, e.g. light-guiding paths comprising photonic band-gap structures or photonic lattices
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
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    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/121—Channel; buried or the like

Abstract

本發明提供一種形成具有適合於整合電子裝置及光子裝置之隔離區域之一基板之方法。使用一共同光罩及光微影技術以製造界定用於在一基板中蝕刻第一及第二區域之開口之一遮罩，其中用於該等第二溝渠隔離區域之該等開口比用於該等第一溝渠隔離區域之該等開口寬。通過該遮罩在該基板中蝕刻該等第一及第二溝渠隔離區域且以氧化物材料填充該等第一及第二溝渠隔離區域。自該等第二溝渠隔離區域之底部移除該氧化物材料。將該等第二溝渠隔離區域進一步蝕刻至比該等第一溝渠隔離區域深，且以氧化物材料填充該等第二溝渠隔離區域。可在該基板上形成電裝置且可藉由該等第一溝渠隔離區域電隔離該等電裝置，且可在該等第二溝渠隔離區域上形成光子裝置且可使該等光子裝置與該基板光學隔離。

Description

用於光電結構之半導體基板及製造方法
本文中描述之實施例係關於一共同半導體基板且係關於形成該共同半導體基板之一方法，該方法使在該基板上製造之電子裝置與光子裝置隔離。
當前趨向於在同一半導體基板上整合光子裝置及電子裝置。一絕緣體上矽(SOI)基板可用作用於此整合之支撐基板。然而，與電子裝置之電隔離所需之一較薄埋藏氧化物(BOX)相比，光子結構(諸如建置在一SOI基板上之波導)一般在SOI基板中需要一較厚埋藏氧化物以用於光學隔離。舉例而言，為防止一光子波導芯與BOX下方之支撐矽之消散耦合，BOX材料必須為較厚的，舉例而言，大於1.0微米且通常為2.0微米至3.0微米厚。當BOX材料具有此一厚度時，其抑制至下層矽之熱流動，該下層矽充當用於電子裝置及光子裝置兩者之一熱消散器。藉由比較，當某些電子裝置(諸如，高速邏輯電路)整合在與光子裝置相同之SOI基板上時，SOI基板之BOX應薄得多，舉例而言，在100奈米至200奈米之範圍中。此BOX絕緣體雖然為電子裝置提供一良好SOI基板，但其不足以防止波導芯與SOI基板之下層支撐矽之光學耦合，此引起不當之光學信號損失。因此，需要一複雜多遮罩 程序來提供具有合適電及光學隔離之一SOI基板或非SOI基板，該電及光學隔離在用於電子裝置及光子裝置之基板之不同區域中具有不同深度。
此外，雖然SOI基板通常用於在同一基板上製造電子裝置及光子裝置，但與非SOI基板相比，SOI基板製造起來係較昂貴的且通常供應量有限。
因此，需要一簡化方法來提供具有用於隔離電子裝置與光子裝置之具有不同深度之隔離區域之一共同半導體基板。
101‧‧‧半導體基板/矽基板/基板
103‧‧‧氧化物墊/墊氧化物
105‧‧‧硬遮罩/遮罩
107‧‧‧第一溝渠/經蝕刻溝渠
109‧‧‧第二溝渠/經蝕刻溝渠
111‧‧‧溝渠隔離氧化物111/氧化物
111a‧‧‧壁氧化物間隔物/側壁間隔物
112‧‧‧底部
113‧‧‧淺第一淺溝渠隔離區域/淺第一溝渠隔離區域/氧化物材料
114‧‧‧虛線
115‧‧‧第二較深溝渠隔離區域/較深溝渠隔離區域
117‧‧‧電晶體
119‧‧‧摻雜源極
121‧‧‧汲極
123‧‧‧閘極
125‧‧‧閘極氧化物
129‧‧‧閘極氧化物側壁
131‧‧‧矽波導芯/波導芯
133‧‧‧氧化物材料/BPSG氧化物材料
135‧‧‧金屬層
w‧‧‧寬度
W‧‧‧寬度
圖1為根據本發明之一實施例之展示一較早製造階段之一矽基板之一橫截面圖；圖2為在圖1中展示之製造階段之後之一製造階段處之該基板之一橫截面圖；圖3為在圖2中展示之製造階段之後之一製造階段處之該基板之一橫截面圖；圖4為在圖3中展示之製造階段之後之一製造階段處之該基板之一橫截面圖；圖5為在圖4中展示之製造階段之後之一製造階段處之該基板之一橫截面圖；圖6為在圖5中展示之製造階段之後之一製造階段處之該基板之一橫截面圖；圖7為在圖6中展示之製造階段之後之一製造階段處之該基板之一橫截面圖；以及圖8繪示形成深溝渠中之一溝渠之一寬度與一側壁之一寬度之間之一關係。
在以下詳細描述中，參考形成該詳細描述之一部分且在其中藉由繪示展示可實踐之特定實施例之隨附圖式。充分詳細地描述此等實施例以使得熟習此項技術者能夠製造且使用此等實施例，且應理解，可在不背離本發明之精神及範圍之情況下對所揭示之特定實施例作出結構、邏輯或程序改變。
本文中描述之實施例提供一種用於形成一半導體基板結構之簡化方法，可在該半導體基板上形成光子裝置及電子電路，其中一淺溝渠電隔離用於電子裝置且深溝渠光學隔離用於光子裝置(諸如，波導、偵測器、分接頭、分光器、調變器、解調變器及其他光子裝置)。
所描述之實施例使用一共同光罩來形成具有第一及第二溝渠隔離區域開口之一共同蝕刻遮罩。該等第二溝渠隔離區域開口比該等第一溝渠隔離區域開口寬。遮罩界定之第一及第二溝渠隔離區域開口用於在一半導體基板中分別蝕刻第一及第二溝渠。初始地將該等第一及第二溝渠蝕刻至同一深度且以氧化物填充該等第一及第二溝渠。該氧化物完全填充該等第一較窄溝渠且部分填充該等第二較寬溝渠。自第二溝渠之底部移除氧化物且接著進一步蝕刻該等第二溝渠使得其等比該等第一溝渠深，在此之後以氧化物填充該等第二溝渠。接著，使該基板平坦化且該基板在其中具有淺溝渠隔離區域及深溝渠隔離區域。可在不具有一絕緣體上矽構造之一半導體基板中形成該等隔離區域。可在基板之具有提供電絕緣之淺隔離溝渠之一區域中製造電子裝置。在提供光子裝置與下層基板之間之光學絕緣之深溝渠隔離區域上製造光子裝置。
現將參考圖1至圖7描述實施例。圖1繪示處於溝渠隔離形成之一較早階段處之一半導體(諸如，矽或多晶矽)基板101。將一墊氧化物103(諸如，二氧化矽)生長或沈積在基板101之上表面上以保護該基板 免遭一後續形成之硬遮罩105。將由(諸如)氮化矽形成之硬遮罩105沈積在墊氧化物103上。如圖2中所展示，可以一單一光罩使用光微影技術來圖案化硬遮罩105，使得硬遮罩105具有用於蝕刻用於形成淺溝渠隔離區域之第一溝渠107之第一較窄開口及用於蝕刻用於形成較深溝渠隔離區域之第二溝渠109之第二較寬開口。用於蝕刻溝渠107之第一開口可各自為自約20奈米至約150奈米寬。該等第二溝渠109可自約2微米寬至約10微米寬。因為第二溝渠109將用於隔離由具有覆層之矽形成之一光子裝置(諸如，一波導/二氧化矽(諸如，二氧化矽))，所以遮罩105之第二開口可針對自約300奈米至約2微米之光子裝置寬度具有在約2微米至約4微米之範圍中之一寬度。一濕蝕刻或乾式蝕刻可用於通過經圖案化硬遮罩105中之該等第一及第二開口在矽基板101中共同蝕刻第一溝渠107及第二溝渠109。經蝕刻溝渠107、109將具有對應於硬遮罩105中之第一及第二開口之寬度。經蝕刻溝渠107及109之深度可為自約200奈米至約300奈米。
在蝕刻第一溝渠107及第二溝渠109之後(如圖2中所展示)，在基板101上方沈積且/或在基板101上面生長一薄溝渠隔離氧化物111(諸如，二氧化矽)以填充第一溝渠107及第二溝渠109且覆蓋硬遮罩105，如圖3中所展示。該氧化物可具有約為該等溝渠之深度之一半之一厚度，諸如約100奈米至約150奈米。如圖4中所展示，較窄第一溝渠107由氧化物111完全填充，而較寬第二溝渠由氧化物111部分填充。
如圖4中所展示，接著可將氧化物111平坦化至硬遮罩105之位準，且接著可使用各向異性濕蝕刻或一電漿乾式蝕刻自第二溝渠109之底部112選擇性地移除氧化物111，從而在溝渠109之側壁處留下氧化物111之一小部分作為一側壁間隔物111a。溝渠107之寬度應使得自第二溝渠之底部112移除氧化物使溝渠107至少部分地(若非完全地)以氧化物填充。此蝕刻使基板101曝露以用於對溝渠109之進一步蝕刻。
圖8繪示一溝渠之寬度W與一側壁間隔物(111a)之一寬度w之間之可用於達成矽基板101之曝露之一關係。當W>2w時，通過溝渠109使基板101曝露以用於進一步蝕刻。因此，若在一實例中側壁間隔物寬度w為100奈米，則第二溝渠109可具有至少200奈米之一寬度w以確保基板101之曝露。相反地，若W<2w，則將不充分蝕刻氧化物111以使基板101曝露。
應注意，側壁間隔物111a為在第二溝渠109處移除氧化物111之一人造物。取決於選定之濕蝕刻及/或乾式蝕刻條件，可在蝕刻期間完全移除側壁間隔物111a以使基板101曝露。
如圖5中所展示，可使用側壁氧化物間隔物111a(若存在)及硬遮罩105之第二開口作為一蝕刻遮罩在第二溝渠109上執行不干擾氧化物111之一進一步各向異性濕蝕刻或一電漿乾式蝕刻，以將第二溝渠109蝕刻至比第一溝渠107之深度更深之一深度，舉例而言，蝕刻至至少為第一溝渠107之深度之兩倍之一深度。對於光子裝置隔離，第二溝渠109之深度可在約1.2微米至約1.5微米之範圍中。若側壁氧化物間隔物111a不存在，則此進一步蝕刻由硬遮罩105之第二開口單獨界定。
在以上文關於圖5描述之方式進一步蝕刻第二溝渠109之後，可在基板101上沈積一第二氧化物(諸如，二氧化矽)以填充第二溝渠109，在此之後，使用CMP或其他已知平坦化技術將整個結構平坦化至基板101之表面，以移除基板101之表面上之氧化物以及氧化物墊103及硬遮罩105。替代地，可藉由一磷酸基板蝕刻移除氧化物硬遮罩105及墊氧化物103。在圖6中繪示所得之經平坦化結構。
圖6之基板101具有淺第一淺溝渠隔離區域113(其等用於電隔離隨後製造之電子裝置)及第二較深溝渠隔離區域115(其等用於光學隔離在其等上製造之光子裝置與半導體基板101)。圖6之基板可用於在同一基板101上製造CMOS電路及光子裝置及電路。圖6亦展示表示可 形成CMOS裝置及電路及光子裝置及電路之基板101上之各自區域之一虛線114。
圖7展示一經部分製造之CMOS/光子積體電路結構之一實例。半導體基板101具有電晶體117，該電晶體117具有摻雜源極119及汲極121區域及一閘極氧化物125上之一閘極123及製造在該閘極氧化物125之閘極氧化物側壁129。淺第一溝渠隔離區域113隔離電晶體117與製造在基板101上之其他電子裝置。圖7亦展示形成為一矽波導芯131之一光子裝置，該矽波導芯131在一隔離較深溝渠隔離區域115上方及上面。波導芯131要求周圍覆層具有低於矽之一折射率，其為約3.47。此覆層在波導芯131之任一側上且在波導131上方由第二較深溝渠隔離區域115且由氧化物材料113提供。第二溝渠區域115之氧化物及圍繞波導芯131之氧化物具有(諸如)約1.54之一折射率。亦可使用具有其他折射率之其他材料。氧化物材料133可為二氧化矽或BPSG氧化物材料133，該等材料亦可用作與用於電互連製造在基板101上製造之電子裝置及光子裝置之一或多個金屬層135相關聯之一層間介電(ILD)結構之一部分。
所描述之實施例提供形成具有適於在同一基板上整合電子裝置及光子裝置兩者之淺溝渠隔離區域及深溝渠隔離區域之一非SOI基板之一方法，該方法使用一單一光罩以形成用於蝕刻之一硬遮罩結構。
雖然上文描述了一方法及結構之實例實施例，但此描述不應理解為限制本發明，此係因為可在不背離本發明之精神或範圍之情況下作出各種修改。因此，本發明僅由隨附申請專利範圍之範疇限制。
101‧‧‧半導體基板/矽基板/基板
113‧‧‧淺第一淺溝渠隔離區域/淺第一溝渠隔離區域/氧化物材料
114‧‧‧虛線
115‧‧‧第二較深溝渠隔離區域/較深溝渠隔離區域
117‧‧‧電晶體
119‧‧‧摻雜源極
121‧‧‧汲極
123‧‧‧閘極
125‧‧‧閘極氧化物
129‧‧‧閘極氧化物側壁
131‧‧‧矽波導芯/波導芯
133‧‧‧氧化物材料/BPSG氧化物材料
135‧‧‧金屬層

Claims (24)

  1. 一種在一半導體基板中形成具有不同深度之隔離區域之方法，該方法包括：在一半導體基板上形成一蝕刻遮罩材料；在一光微影程序中使用一單一光罩來圖案化該蝕刻遮罩材料以界定用於形成第一及第二溝渠隔離區域之第一及第二開口，該等第二開口比該等第一開口寬；使用該經圖案化之蝕刻遮罩材料在該半導體基板中蝕刻第一及第二溝渠隔離區域；在該等第一及第二溝渠隔離區域之各者內形成一隔離材料；在該等第二溝渠隔離區域之底部處移除隔離材料以使該半導體基板曝露，同時在該等第一溝渠隔離區域中留下溝渠隔離材料；在該等第二溝渠隔離區域處進一步蝕刻該經曝露半導體基板，使得該等第二溝渠隔離區域之深度超過該等第一溝渠隔離區域之深度；在該等較深第二溝渠隔離區域內形成一溝渠隔離材料；在該第一基板上形成藉由該等第一溝渠隔離區域電隔離之一電子裝置；及在該等第二溝渠隔離區域內之該溝渠隔離材料上形成一光子裝置使得該光子裝置與該基板光學隔離。
  2. 如請求項1之方法，其中對該等第一及第二溝渠隔離區域之蝕刻在該等第二溝渠隔離區域之側壁上留下隔離材料，該隔離材料形成用於該進一步蝕刻之一蝕刻遮罩。
  3. 如請求項1之方法，其進一步包括在該等較深第二隔離區域內形 成該溝渠隔離材料之後平坦化至該基板之一上表面之位準。
  4. 如請求項3之方法，其中該半導體基板包括一矽基板。
  5. 如請求項3之方法，其進一步包括在該蝕刻遮罩材料與該基板之間形成一墊氧化物，其中該單一光罩及光微影圖案程序圖案化該蝕刻遮罩材料及該墊氧化物。
  6. 如請求項5之方法，其中該墊氧化物包括二氧化矽。
  7. 如請求項1之方法，其中該蝕刻遮罩材料包括氮化矽。
  8. 如請求項1之方法，其中該溝渠隔離材料包括二氧化矽。
  9. 如請求項1之方法，其中以各向異性方式蝕刻該等第二溝渠隔離區域內之該隔離材料來移除該溝渠隔離材料以使該半導體基板曝露，使得該溝渠隔離材料之一部分餘留在該等第二溝渠隔離區域之該等側壁處且用作用於對該經曝露之半導體基板之該進一步蝕刻之一遮罩。
  10. 如請求項1之方法，其中以各向異性蝕刻自該等第二溝渠隔離區域移除該隔離材料。
  11. 如請求項1之方法，其中以電漿蝕刻自該等第二溝渠隔離區域移除該隔離材料。
  12. 如請求項1之方法，其中該進一步蝕刻產生第二溝渠隔離區域，該等第二溝渠隔離區域之深度至少為該等第一溝渠隔離區域之兩倍。
  13. 如請求項12之方法，其中該等第一溝渠隔離區域為約200奈米至約300奈米深。
  14. 如請求項12之方法，其中該等第二溝渠隔離區域為約1.2微米至約1.5微米深。
  15. 如請求項1之方法，其中該等第二溝渠隔離區域之一寬度比該等第一溝渠隔離區域之寬度寬。
  16. 如請求項2之方法，其中該等第二溝渠隔離區域之該寬度大於該等第二溝渠側壁隔離材料之寬度之兩倍。
  17. 一種形成一電路結構之方法，該方法包括：在一光微影程序中使用一單一光罩來圖案化提供在一半導體基板上之一蝕刻遮罩，該圖案界定用於在該基板中蝕刻第一及第二溝渠隔離區域之開口，用於蝕刻該等第二溝渠隔離區域之該等開口比用於蝕刻該等第一溝渠隔離區域之該等開口寬；使用該蝕刻遮罩中之該等第一及第二開口自該基板移除半導體材料以提供該等第一及第二溝渠隔離區域；在該等第一及第二溝渠隔離區域內提供一介電材料；自該等第二溝渠隔離區域移除該介電材料以使該基板曝露；進一步蝕刻該經曝露基板使得該等第二溝渠隔離區域比該等第一溝渠隔離區域深；以一介電材料填充該等第二較深溝渠隔離區域；將該等第一及第二溝渠隔離區域平坦化至該基板之位準；在該基板上形成藉由該等第一溝渠區域電隔離之一電子裝置；及在該等經平坦化第二溝渠隔離區域上形成一光子裝置。
  18. 如請求項19之方法，其中該等第一溝渠隔離區域具有約20奈米至約150奈米之一寬度。
  19. 如請求項17之方法，其中該等第二溝渠隔離區域具有約2微米至約10微米之一寬度。
  20. 如請求項19之方法，其中該等第二溝渠隔離區域具有約2微米至約4微米之一寬度。
  21. 如請求項17之方法，其中該等第二溝渠隔離區域經蝕刻以至少為該等第一溝渠隔離區域之兩倍深。
  22. 如請求項17之方法，其進一步包括在該側上且在該光子裝置上方製造光學隔離區域。
  23. 如請求項17之方法，其中該光子裝置選自由一波導、一偵測器、一分接頭、一分光器、一調變器及一解調變器組成之群組。
  24. 如請求項22之方法，其中該光子裝置上之光學絕緣件為一層間介電結構之一部分。
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EP2939266B1 (en) 2016-12-21
US20140341503A1 (en) 2014-11-20
US8815704B2 (en) 2014-08-26
US8652934B1 (en) 2014-02-18
US20150243546A1 (en) 2015-08-27
WO2014105319A1 (en) 2014-07-03
US20140175596A1 (en) 2014-06-26
EP2939266A1 (en) 2015-11-04
KR20150092284A (ko) 2015-08-12
KR101687127B1 (ko) 2016-12-15
CN104956482A (zh) 2015-09-30
US9305826B2 (en) 2016-04-05
US9034724B2 (en) 2015-05-19
CN104956482B (zh) 2019-04-09
JP6144777B2 (ja) 2017-06-07
JP2016507894A (ja) 2016-03-10

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