CN104952840B - 薄的堆叠封装 - Google Patents
薄的堆叠封装 Download PDFInfo
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- CN104952840B CN104952840B CN201510078454.5A CN201510078454A CN104952840B CN 104952840 B CN104952840 B CN 104952840B CN 201510078454 A CN201510078454 A CN 201510078454A CN 104952840 B CN104952840 B CN 104952840B
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- semiconductor chip
- circuit pattern
- convex block
- opening
- substrate
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
本发明提供一种薄的堆叠封装。本发明的一种堆叠封装包括:基板本体层,其具有上表面和下表面;第一电路图案,其设置在所述基板本体层的下表面上;第二电路图案,其设置在所述基板本体层的上表面上;第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其包括第二凸块。所述第一凸块延伸穿过所述基板本体层,以电耦接到所述第一电路图案,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁,以电耦接到所述第二电路图案。所述第二半导体芯片被堆叠在所述第一半导体芯片上。
Description
相关申请的交叉参考
本申请主张2014年3月28日于韩国知识产权局所提交的韩国申请第10-2014-0036526号的优先权,通过引用将该韩国专利申请整体并入本文中,如同在本文进行了完整的阐述。
技术领域
本案实施例涉及封装技术,更具体地说,涉及薄的堆叠封装。
背景技术
在许多电子系统中使用的半导体装置可以包括各种电子电路组件。电子电路组件可以被集成在半导体装置中的半导体基板中及/或半导体基板上。半导体装置也可称为半导体芯片或半导体小片(die)。存储器半导体芯片可以用在各种电子系统中。在电子系统中使用诸如存储器半导体芯片的半导体装置之前,半导体装置可以被囊封以创建半导体封装。半导体封装可以在电子系统中使用,其中该电子系统可以例如包括计算机、移动系统或数据存储介质。
由于诸如智能手机的移动系统日益更轻且更小,在移动系统中使用的半导体封装已在尺寸上缩小。此外,随着多功能移动系统的发展,对相对大容量的半导体封装的需求在增加。在许多情况下,一直朝着将多个半导体芯片放置在单个封装中努力,以试图提供相对大容量的半导体封装。这样的半导体封装的一个例子是堆叠封装。
发明内容
薄的堆叠封装的一实施例包括:基板,其包括第一电路图案和位于与所述第一电路图案不同水平高度的第二电路图案;第一半导体芯片,其包括电耦接到所述第一电路图案的第一凸块;以及第二半导体芯片,其包括电耦接到所述第二电路图案的第二凸块。所述第二半导体芯片被堆叠在所述第一半导体芯片的与所述基板相反的表面上,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁。
在一实施例中,薄的堆叠封装包括:基板本体层,其具有上表面和下表面;第一电路图案,其设置在所述基板本体层的下表面上;第二电路图案,其设置在所述基板本体层的上表面上;第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其包括第二凸块。所述第一凸块延伸穿过所述基板本体层以电耦接到所述第一电路图案,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁以电耦接到所述第二电路图案。所述第二半导体芯片被堆叠在所述第一半导体芯片上,其中沿着所述第二半导体芯片的长度的中心线大致垂直于沿着所述第一半导体芯片的长度的中心线。
在一实施例中,薄的堆叠封装包括:第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其堆叠在所述第一半导体芯片上。所述第二半导体芯片包括第二凸块。基板包括第一电路图案和第二电路图案,其中所述第二电路图案被设置在与所述第一电路图案不同的水平高度处。所述第一电路图案电耦接至所述第一凸块,并且所述第二电路图案电耦接至所述第二凸块。所述第一电路图案由第一介电层覆盖,以及所述第二电路图案由第二介电层覆盖。第一半导体芯片和第二半导体芯片由保护层覆盖。
在一实施例中,存储卡包括存储器和被配置为控制所述存储器的操作的存储器控制器。所述存储器和所述存储器控制器中的至少一个包括:基板,其包括第一电路图案和设置在与所述第一电路图案不同的水平高度处的第二电路图案;第一半导体芯片,其包括电耦接到所述第一电路图案的第一凸块;以及第二半导体芯片,其包括电耦接到所述第二电路图案的第二凸块。所述第二半导体芯片被堆叠在所述第一半导体芯片的与所述基板相反的表面上,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁。
在一实施例中,存储卡包括存储器和被配置为控制所述存储器的操作的存储器控制器。所述存储器和所述存储器控制器中的至少一个包括:基板本体层,其具有上表面和下表面;第一电路图案,其设置在所述基板本体层的下表面上;第二电路图案,其设置在所述基板本体层的上表面上;第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其包括第二凸块。所述第一凸块延伸穿过所述基板本体层以电耦接到所述第一电路图案,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁以电耦接到所述第二电路图案。所述第二半导体芯片被堆叠在所述第一半导体芯片上,并且沿着所述第二半导体芯片的长度的中心线大致垂直于沿着所述第一半导体芯片的长度的中心线。
在一实施例中,存储卡包括存储器和控制所述存储器的操作的存储器控制器。所述存储器和所述存储器控制器中的至少一个包括:第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其堆叠在所述第一半导体芯片上。所述第二半导体芯片包括第二凸块。基板包括第一电路图案和第二电路图案,其中所述第二电路图案被设置在与所述第一电路图案不同的水平高度处。所述第一电路图案电耦接至所述第一凸块,并且所述第二电路图案电耦接至所述第二凸块。所述第一电路图案由第一介电层覆盖,以及所述第二电路图案由第二介电层覆盖。所述第一半导体芯片和第二半导体芯片由保护层覆盖。
在一实施例中,电子系统包括存储器和经由总线耦接到所述存储器的控制器。所述存储器和所述控制器中至少一个包括:基板,其包括第一电路图案和位于与所述第一电路图案不同的水平高度处的第二电路图案;第一半导体芯片,其包括电耦接到所述第一电路图案的第一凸块;以及第二半导体芯片,其包括电耦接到所述第二电路图案的第二凸块。所述第二半导体芯片被堆叠在所述第一半导体芯片的与所述基板相反的表面上,使得所述第二凸块延伸经过所述第一半导体芯片的侧壁。
在一实施例中,电子系统包括存储器和经由总线耦接到所述存储器的控制器。所述存储器和所述控制器中至少一个包括:基板本体层,其具有上表面和下表面;第一电路图案,其设置在所述基板本体层的下表面上;第二电路图案,其设置在所述基板本体层的上表面上;第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其包括第二凸块。所述第一凸块延伸穿过所述基板本体层以电耦接到所述第一电路图案,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁以电耦接到所述第二电路图案。所述第二半导体芯片被堆叠在所述第一半导体芯片上,其中沿着所述第二半导体芯片的长度的中心线大致垂直于沿着所述第一半导体芯片的长度的中心线。
在一实施例中,电子系统包括存储器和经由总线耦接到所述存储器的控制器。所述存储器和所述控制器中至少一个包括:第一半导体芯片,其包括第一凸块;以及第二半导体芯片,其堆叠在所述第一半导体芯片上。所述第二半导体芯片包括第二凸块。基板包括第一电路图案和第二电路图案,其中所述第二电路图案被设置在与所述第一电路图案不同的水平高度处。所述第一电路图案电耦接至所述第一凸块,并且所述第二电路图案电耦接至所述第二凸块。所述第一电路图案由第一介电层覆盖,以及所述第二电路图案由第二介电层覆盖。所述第一半导体芯片和所述第二半导体芯片由保护层覆盖。
附记:
附记1、一种堆叠封装,该堆叠封装包括:
基板,该基板包括第一电路图案和位于与所述第一电路图案不同水平高度的第二电路图案;
第一半导体芯片,该第一半导体芯片包括电耦接到所述第一电路图案的第一凸块;以及
第二半导体芯片,该第二半导体芯片包括电耦接到所述第二电路图案的第二凸块,
其中,所述第二半导体芯片被堆叠在所述第一半导体芯片的与所述基板相反的表面上,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁。
附记2、如附记1所述的堆叠封装,
其中,所述基板包括具有上表面和下表面的基板本体层;以及
其中,所述第一电路图案被设置在所述基板本体层的下表面上,并且所述第二电路图案被设置在所述基板本体层的上表面上。
附记3、如附记2所述的堆叠封装,该堆叠封装进一步包括至少一个导电贯孔,该导电贯孔延伸穿过所述基板本体层,以将所述第一电路图案中的一个电路图案与所述第二电路图案中的一个电路图案电耦接。
附记4、如附记2所述的堆叠封装,其中,所述第二电路图案被设置在所述基板本体层和所述第一半导体芯片之间。
附记5、如附记4所述的堆叠封装,
其中,所述第一电路图案的至少一部分经由延伸穿过所述基板本体层的第一开口露出;并且
其中,所述第一凸块延伸到所述第一开口内。
附记6、如附记5所述的堆叠封装,其中,所述第一开口中的每个开口具有大致狭缝形状,并且所述第一凸块中的至少两个第一凸块延伸到所述第一开口中的相应开口内。
附记7、如附记5所述的堆叠封装,其中,所述第一开口中的每个开口具有通孔形状,并且所述第一凸块中的每个第一凸块延伸到所述第一开口中的相应开口内。
附记8、如附记5所述的堆叠封装,
其中,所述基板进一步包括第一介电层,所述第一介电层与所述基板本体层的下表面相邻设置并且露出所述第一电路图案中的至少一个电路图案;并且
其中,外部连接端子电耦接至所露出的第一电路图案。
附记9、如附记5所述的堆叠封装,
其中,所述基板进一步包括第二介电层,所述第二介电层与所述基板本体层的上表面相邻设置并且覆盖所述第二电路图案;并且
其中,所述第二电路图案中的至少一部分经由延伸穿过所述第二介电层的第二开口露出。
附记10、如附记9所述的堆叠封装,其中,所述第一开口中的每个开口与第三开口中的相应开口基本上垂直地对齐,其中所述第三开口延伸穿过所述第二介电层。
附记11、如附记9所述的堆叠封装,其中,所述第二开口中的每个开口具有大致狭缝形状,并且所述第二凸块中的至少两个第二凸块延伸到所述第二开口中的相应开口内。
附记12、如附记1所述的堆叠封装,所述堆叠封装进一步包括第一黏着层,所述第一黏着层设置在所述基板和所述第一半导体芯片之间。
附记13、如附记1所述的堆叠封装,所述堆叠封装进一步包括第二黏着层,所述第二黏着层设置在所述第一半导体芯片和所述第二半导体芯片之间。
附记14、如附记13所述的堆叠封装,其中,所述第二凸块的长度相对大于所述第一半导体芯片和所述第二黏着层的总组合厚度。
附记15、如附记1所述的堆叠封装,其中,所述第二凸块沿着所述第二半导体芯片的一个边缘或所述第二半导体芯片的两个相对边缘被设置。
附记16、如附记1所述的堆叠封装,其中,所述第二凸块具有与所述第一凸块基本上相同的长度。
附记17、如附记1所述的堆叠封装,所述堆叠封装进一步包括设置在所述基板上的、围绕所述第一半导体芯片的侧壁和所述第二半导体芯片的侧壁的保护层,
其中,所述保护层覆盖或露出所述第二半导体芯片的与所述第一半导体芯片相反的表面。
附记18、如附记1所述的堆叠封装,其中,所述第二半导体芯片的长度以相对于所述第一半导体芯片的长度大致垂直的配置方式来堆叠,以与所述第一半导体芯片交叉或提供阶梯结构。
附图说明
图1是堆叠封装的一实施例的平面视图;
图2和图3是沿着图1的线X-X'所截取的堆叠封装的截面视图;
图4是用在堆叠封装的一个实施例中的封装基板的截面视图;
图5和图6是用在堆叠封装的一个实施例中的半导体芯片的立体图;
图7是用在堆叠封装的一个实施例中的半导体芯片的堆叠结构的立体图;
图8和图9是用在堆叠封装的一个实施例中的具有黏着层的半导体芯片的立体图;
图10是用在堆叠封装的一个实施例中的具有开口的封装基板的平面视图;
图11是用在堆叠封装的一个实施例中的具有开口的封装基板的平面视图;
图12是沿着图11的线X2-X2'所截取的基板的截面视图;
图13是沿着图11的线X2-X2'所截取的封装的截面视图;
图14是沿着图1的线X-X'所截取的截面视图;
图15是包括堆叠封装的一个实施例的电子系统的方块图表示;以及
图16是包括堆叠封装的一个实施例的电子系统的方块图表示。
具体实施方式
应当理解的是,尽管术语第一、第二、第三等等可以在本文中用来描述各种组件,但是这些组件不应该受这些术语所限制。这些术语仅用于将一个组件与另一个组件相区分。因此,在一些实施例中的第一组件在其它实施例中可以被称为第二组件。
还应当理解的是,当一个组件被称为在另一组件“上”、“上面”、“下面”或“下”时,它可以直接分别在其它组件“上”、“上面”、“下面”或“下”,或者也可以存在中间组件。因此,在本文中使用的诸如“上”、“上面”、“下面”或“下”的术语仅用于描述各种实施例的目的。
还应当理解的是,当一个组件被称为“连接”或“耦接”到另一组件时,它可以直接连接或耦接到另一组件,或者可以存在中间组件。相反地,当一个组件被称为“直接连接”或“直接耦接”到另一组件时,则不存在中间组件。用于描述组件或层之间的关系的其它词语应当以类似的方式来解释。半导体芯片可以通过使用小片切割过程将电子电路所集成的半导体基板或晶片(wafer)分离成多个片而得到。
所述半导体芯片可以对应于存储器芯片或逻辑芯片。存储器芯片可包括集成在所述半导体基板上及/或集成在所述半导体基板中的动态随机存取存储器(dynamic randomaccess memory,DRAM)电路、静态随机存取存储器(static random access memory,SRAM)电路、闪存电路、磁性随机存取存储器(magnetic random access memory,MRAM)电路、电阻性随机存取存储器(resistive random access memory,ReRAM)电路、铁电性随机存取存储器(ferroelectric random access memory,FeRAM)电路或相变随机存取存储器(phasechange random access memory,PcRAM)电路。逻辑芯片可以包括集成在所述半导体基板上及/或集成在所述半导体基板中的逻辑电路。在一些情况下,本文所用的术语“半导体基板”也可以解释为形成有集成电路的半导体芯片或半导体小片。
参见图1,堆叠封装10的实施例可以包括封装基板100和竖直地堆叠在封装基板100上的第一半导体芯片200和第二半导体芯片300。第一半导体芯片200和第二半导体芯片300可以是倒装芯片。第一半导体芯片200和第二半导体芯片300可以在双小片封装结构中以大致垂直的方向来堆叠。多个第一凸块210可以沿着第一半导体芯片200的下表面的边缘设置并且可被操作以将第一半导体芯片200电耦接到封装基板100。同样地,多个第二凸块310可以沿着第二半导体芯片300的下表面的边缘设置并且可被操作以将第二半导体芯片300电耦接至封装基板100。第三半导体芯片(未示出)可以被堆叠在第二半导体芯片300的与面向第一半导体芯片200的表面相反的表面上。
第二半导体芯片300和第一半导体芯片200可以被布置为如图1的平面视图所示。第一第二半导体芯片200和第二半导体芯片300可以各自具有大致矩形形状。沿着第一半导体芯片200的长度延伸的中心线可以设置成基本上垂直于沿着所述第二半导体芯片300的长度延伸的中心线,如图1所示。第一凸块210可以沿着第一半导体芯片200的下表面的相对边缘设置,并且第二凸块310可以沿着第二半导体芯片300的边缘的下表面的相对边缘设置。第一凸块210和第二凸块310所沿着设置的第一半导体芯片200和第二半导体芯片300的边缘可以对应于在第一半导体芯片200和第二半导体芯片300之间的非重迭区域。沿着第一半导体芯片200的每个边缘设置的第一凸块210可以被布置在第一方向上,并且沿着第二半导体芯片300的每个边缘设置的第二凸块310可以被布置在第二方向上,其中所述第二方向基本上垂直于所述第一方向。在一些实施例中,第一凸块210可以沿着第一半导体芯片200的两个相对边缘中的一个边缘来设置。类似地,在一些实施例中,第二凸块310可以沿着第二半导体芯片300的两个相对边缘中的一个边缘来设置。
虽然图1说明第一半导体芯片200和第二半导体芯片300的长度的中心线被设置成相对于彼此基本上为直角的例子,但是第一半导体芯片200和第二半导体芯片300可以以另选的配置方式来布置。例如,在一个实施例中,第一半导体芯片200和第二半导体芯片300以阶梯结构配置方式来堆叠。即,第二半导体芯片300可以相对于第一半导体芯片200横向偏移,使得第二半导体芯片300的边缘从第一半导体芯片200的侧壁横向地突出。更具体地,如图1所示的第二半导体芯片300以基本上90度顺时针方向或逆时针方向旋转,以与第一半导体芯片200完全重叠。经旋转的第二半导体芯片300在一个方向上横向偏移以露出第一半导体芯片200的边缘。经旋转和偏移的第二半导体芯片300以及第一半导体芯片200的配置可以是阶梯结构配置方式。
参照图1和图2,第一半导体芯片200和第二半导体芯片300可以基本上垂直地堆叠在封装基板100上,如上所述。封装基板100可以包括第一电路图案150和第二电路图案130。第一半导体芯片200的第一凸块210可以电耦接到第一电路图案150,并且第二半导体芯片300的第二凸块310可以电耦接到第二电路图案130。
封装基板100可以包括由介电材料所构成的基板本体层110。所述第一电路图案150和第二电路图案130可以设置在基板本体层110上。第一电路图案150和第二电路图案130可以使用包含例如金属层的导电材料的材料来形成。所述金属层可以是例如铜层。虽然在图中没有示出,第一电路图案150和第二电路图案130可以将第一半导体芯片200、和第二半导体芯片300电耦接到外部装置或外部模块基板。基板本体层110可以包括由介电材料所构成的核心层,或者可以是具有多层互连基板结构的预浸料层。在一个实施例中,封装基板100可以具有双层互连基板结构,该双层互连基板结构包括核心层。第一电路图案150和第二电路图案130可以设置在核心层的两个相反的表面上。可替代地,封装基板100可以包括对应于基板本体层110的预浸料层。第一电路图案150和第二电路图案130可以设置在预浸料层的两个相反的表面上。第三电路图案(未示出)可以设置在预浸料层中。第三电路图案可以设置在单层结构或多层结构的预浸料层中。
第一电路图案150可以设置在不同于第二电路图案130的水平高度处。即,第一电路图案150可以设置在相对高于或相对低于第二电路图案130的水平高度的水平高度处。第一电路图案150可以被布置在基板本体层110的表面上,并且第二电路图案130可以被布置在基板本体层110的不同表面上。可替换地,第一电路图案150和第二电路图案130可以被布置在基板本体层110的不同水平高度处。
如上所述,第一电路图案150可以设置在相对高于或相对低于第二电路图案130的水平高度的水平高度处。例如,第一电路图案150可以设置在基板本体层110的表面上,并且第二电路图案130可以被布置在基板本体层110的和与第一电路图案150相关联的表面相反的不同表面上。可能存在对应于在第一电路图案150和第二电路图案130之间的基板本体层110的厚度的水平高度差。在这样的情况下,第一电路图案150可以设置在基板本体层110的与第一半导体芯片200反向的下表面上,并且第二电路图案130可以设置在基板本体层110的与第一电路图案150反向的上表面上。
虽然图2示出了第一电路图案150被布置在基板本体层110的下表面上并且第二电路图案130被布置在基板本体层110的上表面上的例子,可以使用另选的排列方式来相对于第二电路图案130排列第一电路图案150。例如,虽然图中未示出,但是基板本体层110可以包括阶梯表面,该阶梯表面包括第一表面及第二表面,其中第一表面和第二表面是在不同水平高度。第一电路图案150和第二电路图案130可以分别设置在阶梯表面的第一表面和第二表面上。
返回参照图2,第一开口142可以延伸穿过基板本体层110。第一开口142可以用于将第一半导体芯片200的第一凸块210电耦接至封装基板100的第一电路图案150。第一开口142可以对应于延伸穿过基板本体层110的通孔,以露出第一电路图案150。第一半导体芯片200可以设置在封装基板100上,使得每个第一凸块210被插入第一开口142中的相应开口内。第一凸块210可以经由第一导电黏着层211电耦接到第一电路图案150,其中第一导电黏着层211设置在通过第一开口142露出的第一电路图案150上。
在一实施例中,第一介电层160可以包括阻焊材料。各个外部连接端子600可以是连接部件,例如,电耦接到外部装置或模块基板的焊料球。
封装基板100可以包括设置在基板本体层110的上表面上并且覆盖第二电路图案130的第二介电层140。与第二凸块310交叠的第二电路图案130可以经由延伸穿过第二介电层140的第二开口143而露出。第二介电层140可以包括与基板本体层110相同的介电材料。在一个实施例中,第二介电层140可以包括阻焊材料。每个第二凸块310可以插入在第二开口143中的相应开口内。第二凸块310可以经由设置在通过第二开口143露出的第二电路图案130上的第二导电黏着层311而电耦接到第二电路图案130。每个第二导电黏着层311可以包括焊料材料。另外,第三开口145可以延伸穿过第二介电层140。第三开口145可以延伸穿过第二介电层140以露出第一开口142。即,第三开口145可以与第一开口142基本上垂直对准。因此,第一开口142和第三开口145可以提供将第一凸块210插入其中的通孔。第二半导体芯片300可以被堆叠在第一半导体芯片200上,使得第二凸块310延伸经过第一半导体芯片200的侧壁,以电耦接到第二电路图案130。
导电贯孔113可以延伸穿过基板本体层110以将至少一个第一电路图案150电耦接到至少一个第二电路图案130。因此,第二凸块310可以经由导电贯孔113而电耦接到外部连接部件600。保护层500可以被布置在封装基板100上,以覆盖第一半导体芯片200和第二半导体芯片300。保护层500可以通过模塑环氧树脂模塑化合物(epoxy molding compound,EMC)材料所形成。另选地,保护层500可以通过在封装基板100上层叠介电层或介电膜来形成,以将第一半导体芯片200和第二半导体芯片300嵌入其中。在这样的情况下,封装10可以具有嵌入式封装形式。
第一半导体芯片200可以被附接到封装基板100。第二半导体芯片300可以使用置于第一半导体芯片200和第二半导体芯片300之间的黏着层430而附接到第一半导体芯片200。黏着层430可以包括绝缘材料。黏着层430可以抑制或防止与第一半导体芯片200和第二半导体芯片300的翘曲相关的一些故障。基本上类似于层430的额外的黏着层(未示出)可以被置于第一半导体芯片200和第二介电层140之间。
第一半导体芯片200和第二半导体芯片300的厚度可以减小以创建相对薄的堆叠封装10。在这种情况下,如果相对薄的堆叠封装10遭受热过程期间的热,施加到半导体芯片200、300的钝化层或施加到由介电层所组成的封装基板100的拉伸应力可能会增加,并且导致半导体芯片200、300的翘曲。结果,在凸块210、310和电路图案150和130之间可能发生接触故障。此外,当设置在凸块210、310和电路图案150、130之间的第一导电黏着层211和第二导电黏着层311的焊料层回流时,凸块210、310可以可能导致焊料层的非湿故障的方式将电路图案150、130隔开。利用上述黏着层430的实施例可能降低或防止第一半导体芯片200和第二半导体芯片300的翘曲,并且可以防止在凸块210、310和电路图案150、130之间接触故障。因此,即使相对减小第一半导体芯片200和第二半导体芯片300的厚度,利用黏着层430可以减少或防止在薄的堆叠封装中的第一半导体芯片200和第二半导体芯片300的翘曲。
参见图4所示,封装基板100可以包括设置在基板本体层110的上表面上的第一电路图案150以及配置在基板本体层110的下表面上的第二电路图案130。因此,第一电路图案150可以相对于第二电路图案130位于不同的水平高度。如图2所示,第一开口142可以延伸穿过基板本体层110,以露出第一电路图案150。第一开口142可以延伸到堆叠在基板本体层110上的第二介电层140中,以提供通孔。将第一半导体芯片200电耦接到第一电路图案150的第一凸块210被插入到通孔中。在这样的情况下,第一开口142的深度D可以通过第一凸块(图2的210)的长度来确定。第一开口142可以具有基本上等于第一凸块210的长度的深度。实际上,第一开口142可以具有基本上等于第一凸块210的长度和黏着层211的厚度之和的深度。延伸穿过第二介电层140的第二开口143可以露出第二电路图案130的部分,并且可以提供通孔。第二凸块130被插入到通孔中。第一开口142和第二开口143的进气口可以基本上设置在与第二介电层140的上表面相同的水平高度处。因此,第二开口143的深度可以比第一开口142的深度D相对较浅。第一开口142的深度D和第二开口143的深度之间的差异可以基本上等于基板本体层110的厚度和第二电路图案130的厚度之和。
参见图5所示,第一半导体芯片200可以包括设置在其第一表面201上的第一凸块210。第一凸块210可以从第一表面201垂直地延伸。第一凸块210可以被布置在第一半导体芯片200的第一表面201的两个相对边缘上并且可以具有大致圆柱形状。第一凸块210可以包括各种导电材料中的任何一种。例如,第一凸块210可以由从铜材料、金材料、锡材料和它们的任意组合所组成的群组中所选择的导电材料来形成。参照图2和图5所示,第一半导体芯片200可以设置在封装基板100上,使得第一半导体芯片200的第一表面201面向封装基板100。第二半导体芯片300可以被堆叠在第一半导体芯片200的与封装基板100反向的第二表面203上。第一半导体芯片200的第一表面201可以是前表面,其邻近于主动层,在该主动层处集成诸如晶体管之类的电路组件。
参见图6所示,第二半导体芯片300可以包括设置在其第三表面301上的第二凸块310。第二凸块310可以从第三表面301垂直地延伸。第二凸块310可以被布置在第二半导体芯片300的第三表面301的相对边缘上,并且具有大致圆柱形状。第二凸块310可以包括各种导电材料中的任何一种。例如,第二凸块310可以由从铜材料、金材料、锡材料和它们的任意组合所组成的群组中所选择的导电材料来形成。如图2所示,第二半导体芯片300可以被堆叠在第一半导体芯片200上,使得第二凸块310延伸经过第一半导体芯片200的侧壁并且电连接到第二电路图案130。
第二凸块310可以具有长度L2,该长度L2使得能够与第二电路图案130电接触。因此,第二凸块310的长度L2可以相对大于第一半导体芯片200的厚度(图5中的T1)。第二半导体芯片300的厚度T2可以基本上等于第一半导体芯片200的厚度T1。第二半导体芯片300可以具有与第一半导体芯片200基本上相同的结构配置。第二凸块310可以具有与第一凸块210基本上相同的结构配置或与第一凸块210基本上相同的长度。如图2和图3所示,第二半导体芯片300可以被堆叠在封装基板100上方,使得第二半导体芯片300的第三表面301面向封装基板100,并且第二半导体芯片300的与第三表面301相反的整个第四表面303与保护层500接触。
参照图2和图7,第二半导体芯片300可以被堆叠在第一半导体芯片200上,使得第二半导体芯片300的一部分与第一半导体芯片200的一部分重叠。在这样的情况下,第二半导体芯片300可以被堆叠在第一半导体芯片200上,使得所有第一凸块210和第二凸块310面向封装基板100。第二半导体芯片300可以基本上成直角地与第一半导体芯片200交叉,如图1所示。在这种情况下,第一半导体芯片200和第二半导体芯片300中的每一个可以具有大致矩形的形状。即,第一半导体芯片200和第二半导体芯片300中的每一个可以具有宽度和长度,其中长度相对大于宽度。
参照图2和图8,第一黏着层420可以设置在封装基板100和第一半导体芯片200之间,并且可以减少或防止第一半导体芯片200的翘曲。第一黏着层420可以包括绝缘材料,并且可以附接到第一表面201。第一黏着层420可以被布置在第一半导体芯片200的两个相对边缘之间的第一表面201上,其中第一凸块210被排列在第一半导体芯片200的两个相对边缘。
参照图2和图9,第二黏着层430可以设置在第一半导体芯片200和第二半导体芯片300之间,并且可以减少或防止第一半导体芯片200和第二半导体芯片300的翘曲。黏着层430可以包括绝缘材料并且可以附接到第三表面301。黏着层430可以被布置在第二半导体芯片300的两个相对边缘之间的第三表面301上,其中第二凸块310被排列在第二半导体芯片300的两个相对边缘。
参照图2、图4和图10,延伸穿过第二介电层140的每个第二开口143可以具有大致狭缝形状,并且可以露出排列在基板本体层110的边缘并且彼此隔开的第二电路图案130。延伸穿过基板本体层110和第二介电层140的第一开口142和第三开口145可以具有通孔,这些通孔作用为露出第一电路图案150中的相应电路图案。第一凸块210可以延伸到第一开口142和第三开口145中。第一开口142(或与第一开口142对准的第三开口145)可以被设置成与第一电路图案150的相应电路图案重叠。在一个实施例中,第二开口143可以被形成为具有分离的通孔形状,其基本上类似于第一开口142和第三开口145的形状。每个第二开口143被形成为具有狭缝形状,并且可以露出至少两个或更多个第二电路图案130,这些第二电路图案130被排列在基板本体层110的边缘上以作为接合衬垫。当第二凸块310被插入到第二开口143中,可以创建更大的对准限度(margin)。
如上所述,堆叠封装10的实施例可以通过垂直堆叠两个或更多的半导体芯片200、300以及通过在倒装芯片技术中使用的凸块210、310将半导体芯片200、300电耦接到封装基板100来实现。半导体芯片200、300可以电耦接到封装基板100并且经由凸块210、310而无需使用接合导线而与封装基板100物理上组合。因此,覆盖半导体芯片200、300的保护层500的厚度可以减小,以实现相对较薄的堆叠封装。黏着层430可以设置在封装基板100和半导体芯片200、300之间,并且可以减少或防止在半导体芯片200、300的翘曲。半导体芯片200、300的厚度可以被减小到实现相对较薄的堆叠封装。
参照图11、图12和图13,堆叠封装15可以包括封装基板1100以及在封装基板1100上以倒装芯片形式垂直堆叠的第一半导体芯片1200和第二半导体芯片1300。多个第一凸块1210可以设置在第一半导体芯片1200的两个相对的边缘的下表面(对应于前表面)上,以将所述第一半导体芯片1200电耦接到封装基板1100。多个第二凸块1310可以设置在第二半导体芯片1300的两个相对的边缘的下表面(对应于前表面)上,以将第二半导体芯片1300电耦接到封装基板1100。另一半导体芯片(未示出)可以被堆叠在第二半导体芯片1300的与第一半导体芯片1200反向的表面上。
封装基板1100可以包括第二开口1143,该第二开口1143延伸穿过第二介电层1140以露出电耦接到第二凸块1310的第二电路图案1130。每个第二开口1143可以具有大致狭缝状并且露出排列在基板本体层1110的边缘上与彼此分隔开的第二电路图案1130。第一开口1142和与第一开口1142对齐的第三开口1145可以延伸穿过基板本体层1110和第二介电层1140,并且可以露出设置在基板本体层1110的下表面上的第一电路图案1150。每个第一开口1142和对应的第二开口1145可以具有大致狭缝形状,并且可以露出排列在基板本体层1110的边缘的下表面上并且彼此分隔开的第一电路图案1150。因为第一开口1142和第三开口1145具有大致狭缝形状,所以每个第一开口1142和对应的第三开口1145可以露出至少两个或更多个第一电路图案1150,这些第一电路图案1150排列在基板本体层1110的边缘上以作为接合衬垫。在这样的情况下,当第一凸块1210插在第一开口1142和第三开口1145中时,可以增加对准限度。
再次参考图12和图13,第一凸块1210可以经由设置在第一电路图案1150上的第一导电黏着层1211而电耦接至第一电路图案1150,其中第一电路图案1150通过第一开口1142露出。第一介电层1160可以被布置在基板本体层1110的下表面上,以覆盖第一电路图案1150。至少一个第一电路图案1150可以经由延伸穿过第一介电层1160的接触窗口1161露出。外部连接端子1600可以附接到通过接触窗口1161所露出的第一电路图案1150。第二凸块1310可以经由设置在第二电路图案1130上的第二导电黏着层1311而电耦接到第二电路图案1130,其中第二电路图案1130通过第二开口1143所露出。导电贯孔1113可以延伸穿过基板本体层1110以将至少一个第一电路图案1150电耦接到至少一个第二电路图案1130。因此,第二凸块1310可以经由导电贯孔1113而电耦接至外部连接部件1600。保护层1500可以被布置在封装基板1100上以覆盖第一半导体芯片1200和第二半导体芯片1300。第一半导体芯片1200可以使用黏着层(未示出)而附接到封装基板1100,其中该黏着层设置在第一半导体芯片1200和第二介电层1140之间。第二半导体芯片1300可以使用黏着层1430而附接到第一半导体芯片1200,其中该黏着层1430设置在第一半导体芯片1200和第二半导体芯片1300之间。
参见图14,堆叠封装19可以包括封装基板2100以及在封装基板2100上以倒装芯片形式垂直地堆叠的第一半导体芯片2200和第二半导体芯片2300。多个第一凸块2210可以设置在第一半导体芯片2200的两个相对的边缘的下表面(对应于前表面)上并且可以将第一半导体芯片2200电耦接到封装基板2100。多个第二凸块2310可以布置在第二半导体芯片2300的两个相对的边缘的下表面(对应于前表面)上并且可以将第二半导体芯片2300电耦接到封装基板2100。
封装基板2100可以包括第二开口2143,该第二开口2143延伸穿过第二介电层2140以露出电耦接到第二凸块2310的第二电路图案2130。每个第二开口2143可以具有大致狭缝形状,并且可以露出排列在基板本体层2110的边缘上并且彼此分隔开的第二电路图案2130。第一开口2142和与第一开口2142对齐的第三开口2145可以延伸穿过基板本体层2110和第二介电层2140,并且可以露出设置在基板本体层2110的下表面上的第一电路图案2150。每个第一开口2142和对应的第二开口2145可以具有大致狭缝形状,并且可以露出排列在基板本体层2110的边缘的下表面上并且彼此分隔开的第一电路图案2150。因为在第一开口2142和第三开口2145具有大致狭缝形状,所以每个第一开口2142和对应的第三开口2145可以露出至少两个或更多个第一电路图案2150,这些第一电路图案2150排列在基板本体层2110的边缘上以作为接合衬垫。在这样的情况下,当第一凸块2210插入在第一开口2142和第三开口2145中时,可以相对增加对准限度。
第一凸块2210可以经由设置在第一电路图案2150上的第一导电黏着层2211而电耦接至第一电路图案2150,其中第一电路图案2150通过第一开口2142露出。第一介电层2160可以设置在基板本体层2110的下表面上,以覆盖第一电路图案2150。至少一个第一电路图案2150可以经由延伸穿过第一介电层2160的接触窗口2161而露出。外部连接端子2600可以附接到通过接触窗口2161所露出的第一电路图案2150。第二凸块2310可以经由设置在第二电路图案2130上的第二导电黏着层2311而电耦接到第二电路图案2130,其中第二电路图案2130通过第二开口2143露出。导电贯孔2113可以延伸穿过基板本体层2110以将至少一个第一电路图案2150电耦接到至少一个第二电路图案2130。因此,第二凸块2310可以经由导电贯孔2113而电耦接至外部连接部件2600。
保护层2500可以被布置在封装基板2100上,并且可以围绕第一半导体芯片2200和第二半导体芯片2300。保护层2500可以被布置在封装基板2100上,以露出第二半导体芯片2300的与第一半导体芯片2200相反的表面。保护层2500可以覆盖第一半导体芯片2200和第二半导体芯片2300的侧壁。保护层2500可以具有与第二半导体芯片2300的上表面基本上共面或者位于相对低于第二半导体芯片2300的上表面的水平高度处的上表面。
第一半导体芯片2200可以使用黏着层(未示出)而附接到封装基板2100,其中黏着层布置在第一半导体芯片2200和第二介电层2140之间。第二半导体芯片2300可以使用黏着层2430而附接至第一半导体芯片2200,其中黏着层2430设置在第一半导体芯片2200和第二半导体芯片2300之间。
图15是利用至少一个堆叠封装的一个实施例的包括存储卡1800的电子系统的方块图表示。
参见图15所示,存储卡1800可以包括诸如非易失性存储装置的存储器1810以及存储器控制器1820。存储器1810和存储器控制器1820可以存储数据或读出所存储的数据。存储器1810和存储器控制器1820中的至少一个可以包括一个或多个堆叠封装中的一个或多个实施例。
存储器1810可以包括一个或多个实施例的技术所应用于的非易失性存储器芯片。存储器控制器1820可以发出命令到存储器1810,以响应于来自主机1830的读/写请求而管理所存储的数据的读出或数据的存储。
图16是包括堆叠封装的一实施例的电子系统2710的方块图表示。
该电子系统2710可以包括控制器2711、输入/输出单元2712和存储器2713。控制器2711、输入/输出单元2712和存储器2713可以经由总线2715而彼此电性耦接。总线2715提供了数据移动的途径。
在一实施例中,控制器2711可以包括以下中的一个或多个:至少一个微处理器、至少一个数字信号处理器、至少一个微控制器以及能够进行与这些构件基本上相同功能的逻辑装置。控制器2711或存储器2713可以包括堆叠封装的至少一个实施例。输入/输出单元2712可以包括袖珍键盘、键盘、显示装置、触控屏幕等中的一个或多个。存储器2713是用于存储数据的装置。存储器2713可以存储数据及/或发出命令以通过控制器2711来执行等等。
存储器2713可以包括诸如DRAM的易失性存储装置及/或诸如闪存的非易失性存储装置。例如,闪存可以被安装到诸如移动终端或桌上型计算机的信息处理系统。闪存可以是例如固态磁盘(solid state disk,SSD)的构件。电子系统2710可以在闪存系统中存储相对大量的数据。
所述电子系统2710可以包括接口2714,该接口2714被配置为向通信网络发送数据以及从通信网络接收数据。接口2714可以是有线或无线型接口2714。例如,接口2714可以包括天线或有线的或无线的收发器。
所述电子系统2710可以作为移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统来实现。例如,移动系统可以是个人数字助理(PDA)、便携式计算机、平板式计算机、移动电话、智能手机、无线手机、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中任何一种。
如果电子系统2710被配置成进行无线通信时,电子系统2710可以用在通信系统中,诸如CDMA(code division multiple access,码分多址接入)系统、GSM(global systemfor mobile communications,全球移动通信系统)系统、NADC(North American DigitalCellular,北美数字移动蜂窝)系统、E-TDMA(enhanced-time division multiple access,增强的时分多址接入)系统、WCDMA(wideband code division multiple access,宽带码分多址接入)系统、CDMA2000、LTE(long term evolution,长期演进)系统以及Wibro(wireless broadband internet,无线宽带网络)系统。
虽然已经在上面描述了某些实施例,但对于本领域技术人员来说应理解为所描述的实施例仅仅是作为示例的方式。因此,薄的堆叠封装、包含该薄的堆叠封装的存储卡以及本文所描述包括该薄的堆叠封装的电子系统不应基于所描述的实施例而被限制。相反地,薄的堆叠封装、包含该薄的堆叠封装的存储卡以及本文所描述包括该薄的堆叠封装的电子系统应该只受结合上述描述和附图考虑的所附权利要求书所限制。
Claims (18)
1.一种堆叠封装,该堆叠封装包括:
基板,该基板包括第一电路图案和位于与所述第一电路图案不同水平高度的第二电路图案;
第一半导体芯片,该第一半导体芯片包括电耦接到所述第一电路图案的第一凸块;以及
第二半导体芯片,该第二半导体芯片包括电耦接到所述第二电路图案的第二凸块,
其中,所述第二半导体芯片被堆叠在所述第一半导体芯片的与所述基板相反的表面上,并且所述第二凸块延伸经过所述第一半导体芯片的侧壁,
其中,所述第二半导体芯片的长度以相对于所述第一半导体芯片的长度垂直的配置方式来堆叠,以与所述第一半导体芯片交叉或者提供阶梯结构。
2.如权利要求1所述的堆叠封装,
其中,所述基板包括具有上表面和下表面的基板本体层;并且
其中,所述第一电路图案被设置在所述基板本体层的下表面上,并且所述第二电路图案被设置在所述基板本体层的上表面上。
3.如权利要求2所述的堆叠封装,该堆叠封装还包括至少一个导电贯孔,所述至少一个导电贯孔延伸穿过所述基板本体层,以将所述第一电路图案中的一个与所述第二电路图案中的一个电耦接。
4.如权利要求2所述的堆叠封装,其中,所述第二电路图案被设置在所述基板本体层和所述第一半导体芯片之间。
5.如权利要求4所述的堆叠封装,
其中,所述第一电路图案的至少一部分经由延伸穿过所述基板本体层的第一开口露出;并且
其中,所述第一凸块延伸到所述第一开口内。
6.如权利要求5所述的堆叠封装,其中,所述第一开口中的每一个具有狭缝形状,并且所述第一凸块中的至少两个第一凸块延伸到所述第一开口中的相应一个内。
7.如权利要求5所述的堆叠封装,其中,所述第一开口中的每一个具有通孔形状,并且所述第一凸块中的每个第一凸块延伸到所述第一开口中的相应一个内。
8.如权利要求5所述的堆叠封装,
其中,所述基板还包括第一介电层,所述第一介电层与所述基板本体层的下表面相邻设置并且露出所述第一电路图案中的至少一个;并且
其中,外部连接端子电耦接至所露出的第一电路图案。
9.如权利要求5所述的堆叠封装,
其中,所述基板还包括第二介电层,所述第二介电层与所述基板本体层的上表面相邻设置并且覆盖所述第二电路图案;并且
其中,所述第二电路图案中的至少一部分经由延伸穿过所述第二介电层的第二开口露出。
10.如权利要求9所述的堆叠封装,其中,所述第一开口中的每一个与第三开口中的相应一个垂直地对齐,所述第三开口延伸穿过所述第二介电层。
11.如权利要求9所述的堆叠封装,其中,所述第二开口中的每一个具有狭缝形状,并且所述第二凸块中的至少两个延伸到所述第二开口中的相应一个内。
12.如权利要求1所述的堆叠封装,该堆叠封装还包括第一黏着层,所述第一黏着层设置在所述基板和所述第一半导体芯片之间。
13.如权利要求1所述的堆叠封装,该堆叠封装还包括第二黏着层,所述第二黏着层设置在所述第一半导体芯片和所述第二半导体芯片之间。
14.如权利要求13所述的堆叠封装,其中,所述第二凸块的长度相对大于所述第一半导体芯片和所述第二黏着层的总组合厚度。
15.如权利要求1所述的堆叠封装,其中,所述第二凸块沿着所述第二半导体芯片的一个边缘或所述第二半导体芯片的两个相对边缘设置。
16.如权利要求1所述的堆叠封装,其中,所述第二凸块具有与所述第一凸块相同的长度。
17.如权利要求1所述的堆叠封装,该堆叠封装还包括保护层,该保护层按照包围所述第一半导体芯片的侧壁和所述第二半导体芯片的侧壁的方式设置在所述基板上,
其中,所述保护层覆盖或露出所述第二半导体芯片的与所述第一半导体芯片相反的表面。
18.一种堆叠封装,该堆叠封装包括:
基板本体层,该基板本体层具有上表面和下表面;
第一电路图案,所述第一电路图案设置在所述基板本体层的下表面上;
第二电路图案,所述第二电路图案设置在所述基板本体层的上表面上;
第一半导体芯片,该第一半导体芯片包括第一凸块,所述第一凸块延伸穿过所述基板本体层以电耦接到所述第一电路图案;以及
第二半导体芯片,该第二半导体芯片包括第二凸块,所述第二凸块延伸经过所述第一半导体芯片的侧壁以电耦接到所述第二电路图案,
其中,所述第二半导体芯片被堆叠在所述第一半导体芯片上,其中,沿着所述第二半导体芯片的长度的中心线垂直于沿着所述第一半导体芯片的长度的中心线。
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US9721924B2 (en) | 2017-08-01 |
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US9985002B2 (en) | 2018-05-29 |
US20150279819A1 (en) | 2015-10-01 |
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US20170287879A1 (en) | 2017-10-05 |
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