CN104851907A - 具有背侧插入结构的半导体器件及其制造方法 - Google Patents

具有背侧插入结构的半导体器件及其制造方法 Download PDF

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CN104851907A
CN104851907A CN201510079099.3A CN201510079099A CN104851907A CN 104851907 A CN104851907 A CN 104851907A CN 201510079099 A CN201510079099 A CN 201510079099A CN 104851907 A CN104851907 A CN 104851907A
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cavity
semiconductor
insert structure
semiconductor layer
layer
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CN104851907B (zh
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J·G·拉文
H-J·舒尔策
A·毛德
E·格瑞布尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

空腔形成在形成于半导体基底层的第一半导体层中。空腔从第一半导体层的处理表面延伸至基底层。凹陷的掩模衬垫形成在空腔侧壁的远离表面的部分上，或者掩模插塞形成在空腔的远离处理表面的部分中。第二半导体层通过外延生长在处理表面上。第二半导体层跨越空腔。

Description

具有背侧插入结构的半导体器件及其制造方法
背景技术
半导体器件的制造包括主要在诸如硅晶片之类的半导体衬底的前侧处导电和介电结构的形成和杂质区域的形成。在晶片前侧上的处理之后在背侧上形成介电结构和图形化杂质区域受到严格的工艺约束。例如，对于背侧处理可获得的热预算可以受限，从而导致关于可应用材料的进一步约束限制。需要提供一种简化了在晶片背侧处形成图形化结构的制造半导体器件的方法，以及用以提供具有图形化背侧的半导体器件。
发明内容
一个实施例涉及一种制造半导体器件的方法。方法包括在形成于半导体基底层上的第一半导体层中形成空腔。空腔从第一半导体层的处理表面延伸至基底层。凹进的掩模衬垫形成在空腔的侧壁的远离处理表面的部分上，或者掩模插塞形成在远离处理表面的空腔的一部分中。第二半导体层通过外延生长在处理表面上，其中第二半导体层跨越空腔。
根据另一实施例，半导体器件包括半导体本体，具有在前侧的第一表面和在背侧的平行于第一表面的第二表面、以及有源区域和边缘终止区域。边缘终止区域将有源区域与半导体本体的外表面分隔，其中外表面连接了第一表面和第二表面。有源区域中的元件结构主要形成为比第二表面更靠近第一表面。背侧插入结构从第二表面延伸进入边缘终端区域中的半导体本体中。
根据另一实施例，半导体器件包括半导体本体，具有在前侧的第一表面和在背侧的平行于第一表面的第二表面。元件结构主要形成为比第二表面更靠近第一表面。插入结构从第二表面延伸进入半导体本体中，其中插入结构包括相变材料、具有至少1E5cm/s的复合速度的复合结构、受主杂质或施主杂质。
本领域技术人员一旦阅读了以下详细说明书、以及一旦查看了附图将认识到额外的特征和优点。
附图说明
包括附图以提供对于本发明的进一步理解，并且包含在该说明书中并且构成了其一部分。附图示出了本发明的实施例，并且与说明书一起用于解释本发明的原理。通过参考以下详细说明书将使得本发明的其它一些实施例和有意优点变得更加易于理解。
图1A是用于示出了在形成在基底层上形成的第一半导体层中空腔之后的、根据一个实施例关于对准标记的制造半导体器件的方法的半导体衬底的一部分的示意性剖视图。
图1B是在通过外延在第一半导体层上生长第二半导体层之后的图1A的半导体衬底部分的示意性剖视图。
图1C是在移除了整个基底层之后的图1B的半导体衬底部分的示意性剖视图。
图1D包括在光致抗蚀剂层曝光期间图1C的半导体衬底部分的示意图剖视图。
图1E是在形成了与背侧插入结构对准的前侧结构的图1D的半导体衬底部分的示意性剖视图。
图1F是在移除了一部分基底层之后图1B的半导体衬底部分的示意性剖视图。
图2A是用于示出在形成了辅助焊盘之后根据包括过度生长空腔的一个实施例的制造半导体器件的方法的半导体衬底的一部分的示意性剖视图。
图2B是在辅助焊盘之间选择性生长第一半导体层之后的图2A的半导体衬底部分的示意性剖视图。
图2C是在提供了掩模层之后图2B的半导体衬底部分的示意性剖视图。
图2D是在凹进了掩模层之后图2C的半导体衬底部分的示意性剖视图。
图2E是在封盖了第一半导体层中空腔之后图2D的半导体衬底部分的示意性剖视图。
图2F是通过外延生长了第二半导体层之后图2E的半导体衬底部分的示意性剖视图。
图2G是在移除了基底层之后图2F的半导体衬底部分的示意性剖视图。
图3A是在边缘终止区域中提供了背侧插入结构的根据一个实施例的半导体器件的一部分的示意性剖视图。
图3B是图3A的半导体器件的示意性横向剖视图。
图4A是具有增大了反向阻挡能力的背侧插入结构的根据一个实施例的半导体器件的一部分的示意性剖视图。
图4B是图4A的半导体器件的示意性横向剖视图。
图5A是用于示出在提供具有包含杂质的处理材料的插入结构之后、提供了沿着背侧处插入结构形成的场停止部分的根据一个实施例的制造半导体器件的方法的半导体衬底的一部分的示意性剖视图。
图5B是在杂质向外扩散之后的图5A的半导体衬底部分的示意性剖视图。
图6是具有沿着背侧处插入结构形成的反掺杂岛的根据一个实施例的半导体器件的一部分的示意性剖视图。
图7是具有包括相变材料的背侧插入结构的根据一个实施例的半导体器件的一部分的示意性剖视图。
图8是具有沿着基底层和第一半导体层之间界面的空隙或介电岛的根据一个实施例的半导体器件的一部分的示意性剖视图。
具体实施方式
在以下详细说明书中，参考了形成其一部分的附图，其中借由解释说明了可以实施本发明的具体实施例而示出了附图。应该理解的是可以采用其它一些实施例，并且可以做出结构或逻辑改变而不脱离本发明的范围。例如，对于一个实施例说明或描述的特征可以用在其它一些实施例上或者与其结合以产生另一实施例。有意的是本发明包括这些修改和变形。使用特定语言描述示例，其不应构造为限定了所附权利要求的范围。附图并未按照比例并且仅用于示意性目的。为了简明，如果没有另外给出相反指示的话，在不同附图中由对应的附图标记表示相同的元件。
术语“具有”、“含有”、“包含”、“包括”等等是开放式的，并且术语指示了所述结构、元件或特征的存在，但是并未排除额外的元件或特征。冠词“一”、“一个”、“该”意在包括复数以及单数形式，除非上下文明确给出相反指示。
术语“电连接”描述了在电连接的元件之间的永久性低欧姆连接，例如在所述元件之间的直接接触或者经由金属和/或高掺杂半导体的低欧姆连接。术语“电耦合”包括适用于信号传输的一个或多个插入元件，可以电性地设置在电耦合元件之间，例如在第一状态下提供了低欧姆连接以及在第二状态下提供了高欧姆电退耦的元件。
附图通过在掺杂类型“n”或“p”之后指示了“-”或“+”而示出了相对掺杂浓度。例如，“n-”指示具有低于“n”掺杂区域的掺杂浓度的区域，而“n+”掺杂区域具有比“n”掺杂区域更高的掺杂浓度。相同相对掺杂浓度的掺杂区域并非必需具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可以具有相同或不同的绝对掺杂浓度。
图1A至图1E涉及形成背侧插入结构以及用于将前侧结构与背侧插入结构对准的对准标记的方法。
第一半导体层110a通过外延生长在半导体基底层105上。基底层105是单晶半导体材料的层或层结构，例如硅(Si)、锗(Ge)、硅锗晶体(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)或其它AIIIBV半导体。基底层105可以是同质层，或者可以包括基底衬底以及通过外延生长在基底衬底上的外延层，其中基底衬底和外延层可以在导电类型和/或杂质浓度方面不同。第一半导体层110a的晶格依照基底层105的晶格而生长。
一个或多个第一和第二空腔205a、205b可以形成在与基底层105相对的第一半导体层110a的处理表面101x中。例如，硬掩模可以通过光刻工艺形成在处理表面101x上，并且可以通过反应离子刻蚀而刻蚀空腔205a、205b，其中空腔205a、205b可以延伸进入基底衬底中。根据其它一些实施例，空腔205a、205b可以通过局部遮蔽第一半导体层110a的外延生长而形成。
图1A示出了从处理表面101x延伸至基底层105的第一空腔205a和第二空腔205b。第一空腔205a可以形成在半导体衬底500a的功能部分100a中，其形成了从包括基底层105和第一半导体层110a的半导体衬底500a获得的最终半导体器件的半导体本体的部分。第二空腔205b可以形成在切口部分100x中，其在分割工艺期间消耗或者移除以用于获得包括功能部分100a的多个相等的半导体裸片。第一空腔205a和第二空腔205b分别可以到达或者可以延伸进入基底层105中。
第一空腔205a的第一宽度w1可以小于第二空腔205b的第二宽度w2。空腔205a、205b可以采用掩模衬垫203加衬，其可以由一个或多个介电层构成或者包括一个或多个介电层，诸如氧化硅、氮氧化硅、氮化硅，和/或诸如钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或钨W之类的扩散阻挡层。掩模衬垫203可以完全填充第一空腔205a或者两个空腔205a、205b，或者可以留下空隙。另外的材料可以部分或完全填充第一空腔205a或两个空腔205a、205b。
第二半导体层120a形成在第一半导体层110a的处理表面101x上。第二半导体层120a跨越第一空腔205a，但是并未在第二空腔205b的垂直突起中生长或者至少在其中留下空隙。
根据一个实施例，生长第二半导体层120a包括采用第一半导体层110a的材料封盖第一空腔205a，并且随后在第一半导体层110a上通过外延来生长第二半导体层120a。封盖第一空腔205a可以包括使得部分第一半导体层110a流体化，并且随后重结晶。根据另一实施例，封盖第一空腔205a可以包括在支持足够横向生长的工艺条件下的外延工艺。
可以采用或不采用相反的材料219来部分或完全填充在第二空腔205b的垂直突起中由第二空腔205b和第二半导体层120a中对应空隙形成的扩展空腔，相反材料219例如是氧化硅、介电聚合物、相变材料或多晶硅。
图1B示出了跨越并且覆盖第一空腔205a的第二半导体层120a。第二半导体层120a可以在第二空腔205b的垂直突起中完全缺失，可以留下比第二空腔205b更窄的空隙，或者可以过度生长第二空腔205b，其中晶界可以形成在第二空腔205b的垂直突起中。
使用湿法刻蚀工艺、研磨工艺或例如CMP(化学机械抛光)的抛光工艺来部分或者完全地移除基底层105，其中半导体衬底500a减薄，并且暴露了第一空腔205a、第二空腔205b或两者，或者暴露了在至少第一空腔205a、第二空腔205b或两者的内部的材料。
图1C示出了减薄的半导体衬底500a，具有第二半导体层120a的暴露表面，从而形成了在半导体衬底500a的前侧上的第一表面101a和第一半导体层110a的相对表面，上述暴露表面通过在背侧形成第二表面102a的研磨或抛光工艺而暴露。第一表面101a和第二表面102a基本上相互平行。第一表面101a和第二表面102a之间的距离可以至少20μm，例如至少45μm，并且可以范围高达至数100μm。在功能部分100a中，从第一空腔205a得到的背侧插入结构250a从第二表面102a延伸进入包括第一半导体层110a和第二半导体层120a的半导体衬底500a中。从第二空腔205b得到的对准标记250b从第一表面101a穿过半导体衬底500a延伸至第二表面102a。
掩模层810a可以沉积在第一表面101a上。抗蚀剂层820a可以沉积在掩模层810a上。定位系统(registration system)920估计对准标记250b的位置。例如，定位系统920发射光，其以例如约45度的角度入射在第一表面101a上，并且估计从半导体衬底500a反射的光，在其中光在对准标记250b和第二半导体层120a之间的界面反射和/或散射。基于关于对准标记250b的位置信息，光刻设备910将照射掩模911对准至半导体衬底500a。由光刻设备910发射并且穿过或者在照射掩模911处反射的光束曝光了由照射掩模911的掩模图形所限定的光致抗蚀剂层820a的区段。
将已曝光的光致抗蚀剂层820a显影，其中移除了光致抗蚀剂层820a的已曝光或未曝光区段。光致抗蚀剂层820a的剩余区段形成了用作用于图形化掩模层810a的抗蚀剂掩模，或者可以用作注入掩模。
图1E示出了通过图形化掩模层810a得到的前侧结构810。前侧结构810可以是临时的刻蚀或注入掩模、或者最终器件的功能结构。背侧插入结构250a对准至前侧结构810以及通过使用前侧结构810作为刻蚀或注入掩模所形成的结构。可以良好的限定在背侧插入结构250a与前侧结构810的边缘之间的距离dx。方法允许在对准容差内将前侧上的结构对准至背侧上的结构，该对准容差不大于在相同侧面处通过两个独立光刻工艺获得的结构之间的对准容差。因为在处理前侧之前形成背侧插入结构250a，因此广泛的材料和工艺可以应用于背侧插入结构250a。
根据另一实施例，图1B的第二空腔205b是环形空腔，其围绕了包括诸如二极管结构和/或晶体管单元之类的半导体器件结构的有源芯片区域。第二空腔205b可以完全形成在分配至最终半导体器件的半导体裸片并且与半导体裸片的侧表面一定距离的半导体衬底500a的一部分内，其中侧表面连接最终半导体裸片的第一表面101a和第二表面102a，并且其中第二空腔205b有效地作为防止沿着侧表面产生的裂缝传播进入有源芯片区域中的破碎停止层。侧表面可以垂直于第一表面101a和第二表面102a。
根据另一实施例，第二空腔205b至少部分地形成在半导体衬底500a的切口区域中，并且在将多个等同半导体裸片从半导体衬底划片分割的工艺期间部分地消耗。根据另一实施例，沿着围绕有源芯片区域的线形成多个第二空腔205b，例如在切口区域内形成多个第二空腔205b。
图1F涉及具有延伸进入基底层105的图1B的第一空腔205a的一个实施例。基底层105可以仅部分移除，使得在减薄之后，基于图1B的第一空腔205a的背侧插入结构250a延伸进入图1B的基底层105的剩余部分105a中。
图2A至图2G示出了使用掩模外延生长的用于形成背侧插入结构的方法的细节。
基底层105包括单晶半导体材料的层或层结构，单晶半导体材料例如是硅(Si)、锗(Ge)、硅锗晶体(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)或其它AIIIBV半导体。基底层105可以是同质层，或者可以包括基底衬底105a和通过在基底衬底105a上外延生长的至少一个外延层105b，其中外延层105b的晶格锁入基底衬底105a的晶向。基底衬底105a和外延层105b可以具有不同的导电类型和/或不同的杂质浓度。外延层105b可以是n掺杂或p掺杂、或者本征的半导体材料。
辅助层例如通过热处理(例如基底层105的一部分的氧化)和/或沉积(例如化学气相沉积(CVD)、高密度等离子(HDP)沉积或等离子增强化学气相沉积(PECVD))形成在基底层105的表面上。光刻工艺将辅助层图形化以形成一个或多个隔离的(也即与辅助层空间分隔的)辅助焊盘201。辅助焊盘201可以是紧凑结构，其具有在相同幅度量级内的两个横向尺寸或平行的条带。根据一个实施例，至少一个辅助焊盘201可以形成环形结构。
图2A示出了在基底层105的表面101w上的辅助焊盘201。辅助焊盘201可以由介电材料构成或包含介电材料。辅助焊盘201可以展现出相对于基底层105的材料的高研磨选择性。根据一个实施例，辅助焊盘201由如下材料构成或者包含如下材料作为主要成分：氧化硅、氮化硅、氮氧化硅、碳、或所述材料中的至少两种的组合。
第一半导体层110a通过外延而生长在包括辅助焊盘201的基底层105的表面101w上，其中外延层105b可以有效地作为籽晶。辅助焊盘201局部地抑制了在由辅助焊盘201所覆盖的基底层105的区段中的外延生长。在外延生长期间可以改变第一半导体层110a中的杂质浓度。
图2B示出了具有形成在辅助焊盘201的垂直突起中的空腔205的第一半导体层110a。空腔205的侧壁可以垂直于与基底层105相对的第一半导体层110a的暴露处理表面101x，或者可以以减小的距离逐渐变细至暴露表面101x。
根据其它一些实施例，可以如参照图1A所述而形成空腔205。例如，连续的各向异性刻蚀工艺或步进式连续各向异性刻蚀工艺可以在半导体材料中形成空腔205。
空腔205的两个横向尺寸可以在相同幅度量级内，例如基本上相等。例如，在平行于处理表面101x的平面中空腔205的横截面可以是圆形、卵形、椭圆，或者具有或不具有圆化角部的矩形。根据另一实施例，空腔205可以是笔直的条带，或者具有尖锐弯折、弯曲或分支的条带。半导体衬底500a可以包括由半导体衬底500a获得的在半导体裸片的每个半导体本体100中的一个或多个环形空腔205。
掩模层203a形成在处理表面101x上以及沿着空腔205的内侧壁。形成掩模层203a可以包括在包含氧和/或氮的环境中对半导体衬底500a的热处理，和/或至少一个掩模材料的沉积。根据一个实施例，形成掩模层203a包括高度共形沉积和/或低共形沉积，例如使用TEOS(四乙基原硅酸盐)作为前驱物材料。
图2C示出了覆盖处理表面101x以及空腔205的侧壁的掩模层203a。至少掩模层203a的子层可以覆盖辅助焊盘201。
根据一个实施例，掩模层203a包括热生长的半导体氧化物或半导体氮化物或者由热生长的半导体氧化物或半导体氮化物构成，例如在第一半导体层110a是硅层的情形中该半导体氧化物或半导体氮化物是氧化硅或氮化硅。根据另一实施例，掩模层203a是近似的共形层。掩模层203a可以包括从氮氧化硅或氮化硅提供的子层。掩模层203a可以包括高度共形子层，使得掩模层203a完全填充空腔205。
根据另一实施例，掩模层203a包括低共形层，例如使用掩模插塞(例如氧化物插塞)封闭空腔205的HDP氧化物，从而在辅助焊盘201和掩模插塞之间留下空隙。掩模层203a以及辅助焊盘201可以展现出相对于第一半导体层110a的高研磨选择性。
掩模层203a或掩模插塞可以凹进，使得移除位于空腔205外一部分掩模层203a或掩模插塞，并且移除在空腔205的侧壁的邻接处理表面101x的一部分上的部分掩模层203a或掩模插塞。例如，可以各向同性地凹进形成了掩模插塞的掩模层203a。对于并未形成空腔205中的掩模层203a而言，可以沉积并凹进牺牲材料(例如抗蚀剂)以在朝向辅助焊盘201的空腔205的一部分中形成抗蚀剂插塞。抗蚀剂插塞可以在掩模层203a的凹进期间用作刻蚀掩模。在掩模层203a的凹进之后，可以移除抗蚀剂插塞。
图2D示出了由朝向辅助焊盘201的图2C的掩模层203a的剩余部分形成的掩模衬垫203，其中暴露了朝向处理表面101x的空腔205的一部分侧壁。
可以在包含氢的环境中在900摄氏度之上或1000摄氏度之上或在1050与1150摄氏度之间的高温下对半导体衬底500a退火至少5分钟或至少10分钟或更长。由于在含氢气氛中例如硅原子的高表面迁移率，第一半导体层110a的材料成为粘滞的，并且粘滞的硅的缓慢移动流闭塞了空腔205。当空腔205封闭时退火停止并且半导体材料重结晶。可以使用例如抛光工艺平坦化由重结晶的半导体材料所形成的改性处理表面101y。
在平坦化之前或之后，可以沉积辅助掩模层并且在空腔205的垂直突起中开口以形成辅助注入掩模。通过在辅助注入掩模中的开口，可以以低能量和高剂量注入氧以形成在处理表面101x、101y和空腔205之间的氧化物层。氧化物层、掩模焊盘层203以及如果可适用的话则辅助焊盘201可以完全覆盖空腔205的内表面。可以在氧注入之后移除辅助注入掩模。
图2E示出了封盖并且跨越了空腔205的重结晶的第一半导体层110a。空腔205形成了在辅助焊盘201的垂直突起中的封闭空隙。根据其它一些实施例，重结晶的第一半导体层110a可以完全填充空腔205，使得在辅助焊盘201的垂直突起中没有形成空隙。
外延工艺在平坦化的处理表面101y上生长第二半导体层120a，其中根据最终半导体器件的电压阻断需求和/或导通状态电阻需求设置第二半导体层120a的杂质浓度梯度和厚度。第二半导体层120a中掺杂剂浓度可以等于或者低于第一半导体层110a中掺杂剂浓度。
根据一个实施例，对准标记可以由空腔形成，其足够宽以使得在含氢环境中在退火期间第一半导体层110a的粘滞半导体材料不会闭塞分配至对准标记的空腔，并且生长第二半导体层120a在相关空腔之上留下了空隙。
通过施加至前侧的工艺，可以在控制结构615中形成电子部件的元件结构，诸如IGFET(绝缘栅场效应晶体管)、JFET(结型场效应晶体管)、IGBT(绝缘栅双极晶体管)和/或半导体闸流管的晶体管单元的源极区域和/或栅极电极，半导体二极管的阳极区域或者可控半导体二极管的控制电极以及超级结和补偿结构。元件结构可以包括杂质区域、导电结构以及绝缘结构。
载板900可以附接(例如粘合、接合或安装)至第一表面101a。载板900可以是玻璃载板。根据一个实施例，载板900可以是可重复使用的抛光(二)氧化硅碟盘或抛光的硅碟盘。
图2F示出了由与第一半导体层110a相对的第二半导体层120a的表面所形成的半导体衬底500a的第一表面101a。载板900安装在由第一表面101a限定的前侧上。控制结构615的元件结构主要形成为比第一半导体层110a与基底层105之间的界面更靠近由第一表面101a限定的前侧。
研磨或抛光工艺移除基底层105，以及由此减薄半导体衬底500a。辅助焊盘201可以有效地作为刻蚀停止结构和/或研磨停止层，并且可以提供指示了辅助焊盘201或空腔205内部另一材料的暴露的刻蚀停止信号和/或研磨停止信号。
根据一个实施例，研磨工艺从基底层105的暴露表面移除半导体材料直至邻接基底层105的辅助焊盘201的边缘。根据另一实施例，在辅助焊盘201的暴露之后，可以通过在预设研磨条件下以预设时间处理研磨工艺，使得部分地或者完全地移除了辅助焊盘201。
研磨包括具有几何未限定的切割边缘的任何切削。在开始处，研磨可以使用具有粗糙表面的第一研磨本体(例如研磨片或研磨轮)，在高的向下作用力下以获得高的移除速率。在预期研磨到达辅助焊盘201之前，可以采用具有更平滑表面的第二研磨本体替代第一研磨本体和/或可以减小向下作用力。例如，首先减小向下作用力，并且稍后更换研磨本体。随着研磨本体到达辅助焊盘201，移除速率大大减小，导致驱动研磨本体所需的功率或扭矩大大增大。更高的扭矩导致驱动研磨本体的电动机的更高电动机电流，并且可以通过监控驱动电流控制研磨。
可以为岛状焊盘、条带或框架、或者为在空腔205内的另一材料的辅助焊盘201阻止半导体材料的进一步移除。移除速率大大减小，从而导致驱动研磨本体的电动机电流大大增大。可以监控研磨的第二表面102的驱动电流和/或频谱响应以停止研磨。
在半导体衬底500a倾斜至研磨本体的研磨表面的情形中，当研磨工艺首先到达辅助焊盘201时，辅助焊盘201阻挡了半导体衬底500a的一部分中的材料的进一步移除。结果，研磨工艺自调整，并且对于在初始背表面与研磨本体的研磨表面之间的倾斜角自动补偿。取决于支撑研磨本体的材料的刚度或研磨本体自身的刚度，其可以发生在辅助焊盘之间，进一步以小量移除半导体材料，从而留下研磨的第二表面102a的成碟弯曲。可以通过研磨工具和研磨工艺的合适选择而控制并且减小该效应。
图2G示出了在与载板900分离之后的已减薄半导体衬底500a。在背侧处已研磨的第二表面102a暴露了辅助焊盘201，其可以分段或完全移除。可以在与载板900分离之前或之后执行从背侧有效的其它工艺处理步骤，例如用于产生背侧发射极或场停止区的注入以及用于提供背侧金属化的沉积工艺。
由空腔205形成直接邻接第二表面102a的背侧插入结构250。背侧插入结构250形成在台阶处，其中可获得高温预算，使得背侧插入结构250可以包括其形成/沉积与高温预算组合的材料，例如热生长的氧化物。
背侧插入结构250可以是实心介电结构或者具有在背侧处分隔了杂质区域的空隙的介电结构，例如RC-IGBT的p掺杂和n掺杂集电极区域。介电背侧插入结构可以局部地减小IGBT中的集电极效率，或者可以减小由施加至前侧的材料引起的晶片弯曲。
例如，沿两个正交方向形成足够数目的背侧插入结构250补偿了由沉积在前侧处的厚氧化物结构引起的机械应力以及由控制结构615的部件引起的机械应力，或者在半导体本体100与将半导体本体10与载板衬底(例如DCB(直接铜接合)衬底或PCB(印刷电路板))连接的焊料层之间或者在焊料层与载板衬底之间交汇处引起的热-机械应力。
根据其它一些实施例，背侧插入结构250可以是采用含有杂质的材料临时填充的辅助结构，杂质在制造期间扩散出去并且局部地以至第二表面102的距离形成了杂质区域。杂质区域例如可以用于场成形，电荷载流子寿命调整或雪崩限定。其它一些实施例可以提供有效地作为对准标记或切削停止物的背侧插入结构250。
根据其它一些实施例，空腔可以开口，例如通过选择性刻蚀工艺，例如通过移除辅助焊盘201以及如果适用的话则移除掩模衬垫203的一部分。将空腔205开口可以包括用于从空腔205的内部移除材料的其它工艺。可以采用或不采用与空腔205对准的横向图形通过重开口空腔的暴露底部和侧壁从背侧注入杂质。随后，可以例如采用介电材料例如使用低温CVD(化学气相沉积)或旋涂工艺再次填充重新开口的空腔205，以形成最终的背侧插入结构250。
图3A和图3B涉及半导体器件500，其边缘终止区域695包括环形背侧插入结构250。
半导体器件500包括在半导体本体100中的至少一个pn结，以及在第一负载电极310和第二负载电极320之间的负载电流路径。半导体器件500可以是横向器件，具有设置在由半导体本体100的第一表面101限定的前侧处的两个负载电极310、320。根据所示实施例，半导体器件500是具有设置在半导体本体100的相对侧上的负载电极310、320的垂直器件。
半导体器件500例如可以是或者可以包括例如可控半导体二极管的半导体二极管，IGFET、JFET、例如RC-IGBT(反向导电IGBT)的IGBT，或例如GTO(栅极关断闸流管)或GCT(栅极整流闸流管)的闸流管。半导体器件500可以包括超级结或者补偿结构。半导体本体100的材料是单晶半导体材料，例如硅Si、碳化硅SiC、锗Ge、锗硅晶体管SiGe、氮化镓GaN或砷化镓GaAs，或其它AIIIBV半导体。平行于第一表面101的方向是横向方向，以及第一表面101的法线限定了垂直方向。
半导体本体100包括第一导电类型的漂移区域120，以及第一导电类型或者与第一导电类型互补的第二导电类型的基架层130。基架层130平行于与第一表面101平行的半导体本体100的第二表面102延伸。在漂移区域120中，杂质浓度可以是均匀的，或者可以随着至第二表面102减小的距离而逐渐增大或减小。漂移区域120中杂质浓度例如可以在5E12与5E14cm-3之间。
场停止层128或缓冲层可以设置在漂移区域120与基架层130之间。在所示实施例中，场停止层128将基架层130与漂移区域120分离。场停止层128中最大杂质浓度是漂移区域12中最大杂质浓度的至少五倍，例如高达十倍。漂移区域120与场停止层128形成了单极半导体结，例如nn-结或pp-结，其大致平行于第二表面102。漂移区域120可以与基架层130形成pn结或单极半导体结，例如nn+结或pp+结。
在有源区域610中，半导体器件500包括在第一表面101与漂移区域120之间的器件专用控制结构615。环绕有源区域610并且将有源区域610与接触第一表面101和第二表面102的外表面103分离的边缘终止区域690可以包括边缘终止结构695，分别包括例如横向掺杂变化、场停止结构、沟槽终止结构和/或邻接第一表面101的保护环。
外表面103可以包括垂直于第一表面101的区段。例如，外表面103可以包括邻接第一表面101并且由沟槽刻蚀得到的第一区段，以及邻接第二表面102并且由诸如锯切的机械分割工艺得到的第二区段。
控制结构615可以包括元件结构，诸如半导体二极管的阳极区域、可控二极管的控制结构或者晶体管单元TC的源极区域110、本体区域115和栅极结构150。元件结构主要地比背侧上的第二表面102更靠近前侧上第一表面101。
在背侧处，插入结构250从第二表面102延伸进入半导体本体100中。在台阶状外表面103的情形中，插入结构250的横向突起可以与由沟槽刻蚀工艺获得的区段交叠。
插入结构250可以包括介电材料，半导体材料，和/或导电材料，相变材料，和/或空隙，其防止由例如在外表面103处的机械分割工艺导致的裂缝和裂沟穿透进入半导体本体100的有源区域610中。例如，插入结构250包括半导体氧化物层，例如沿着与半导体本体100的界面的氧化硅层或氮氧化硅层。插入结构250可以由介电材料完全填充或者可以包含由介电材料焊盘的空隙。
插入结构250的垂直尺寸可以在0.2微米与10微米之间，例如至少1微米。插入结构250的横向尺寸可以从0.1μm至数微米。
根据图3A和图3B中所示的实施例，插入结构250是环形结构并且以去往外表面103的一定距离围绕包括半导体本体100的有源区域610的一部分。插入结构250中的空隙255可以阻止在将半导体衬底分割为多个半导体裸片的分割工艺期间在外表面103处产生的裂缝的传播，其中裂缝稍后可以传播穿过边缘终止区域695进入有源区域610中。插入结构250也可以使得杂质原子(例如铜原子)穿过边缘终止区域690而进入有源区域610中。
图4A和图4B涉及其它一些实施例，具有在背侧处边缘终止区域690中的插入结构250。插入结构250至少采用包含杂质(例如施主杂质和/或受主杂质)的材料临时的填充。杂质扩散出插入结构250并且可以形成n型或p型杂质区域127，其中杂质浓度随着沿横向方向和沿垂直方向与各自插入结构250的距离增大而减小。
根据涉及IGBT的一个实施例，局部杂质区域127可以具有基架层130的导电类型，并且从相应插入结构250延伸进入漂移区域120中，使得在边缘终止区域690中漂移区域120与基架层130和局部杂质区域的背侧pn结偏离第二表面102。在背侧103处，pn结与第二表面102之间的距离增大。当第二负载电极320焊接至诸如DCB(直接铜接合)板、PCB(印刷电路板)或引线框架之类的载板上时，允许焊料材料沿着外表面103从背侧流动更远距离而不造成pn结的短路。
根据另一实施例，插入结构250局部地减小了集电极效率。少数电荷载流子充满处于IGBT的导通状态或RC-UGBT的反向导电模式下的边缘终止区域690，使得改进半导体器件500的整流换向(commutation)特性。
插入结构250可以与HDR(高动态强健性)方案组合。例如，边缘终止区域690可以包括发射极效率减小区域，从而减小电荷载流子从基架层130注入至边缘终止区域690中，导致结终止区域中减小的动态雪崩。
根据图4B中所示的实施例，沿着围绕边缘终止区域690中有源区域610的环形线设置多个插入结构250。
图5A至图5B涉及半导体器件500，其具有通过在半导体本体100中成形场停止层128的背侧插入结构250而引入的杂质。
根据一个实施例，n型杂质可以通过第二表面102a引入，例如通过注入，以形成沿着第二表面102a的注入层128x。
在半导体本体100中，可以使用上述方法之一形成从第二表面102a延伸进入半导体本体中并且包括处理材料254的插入结构250。
插入结构250可以形成作为包括处理材料254的实心结构，在半导体器件500具有例如多晶或单晶硅之类的n型漂移区域120的情形中含有n型杂质。根据另一实施例，插入结构250可以形成作为包括由掩模衬垫203加衬的空隙的沟槽状结构，其中处理材料254从背侧填充进入空隙中并且其中可以在提供处理材料254之前移除掩模衬垫203。根据又一实施例，插入结构250由可以采用处理材料254替代的牺牲材料形成。插入结构250可以进一步包括由介电材料形成的辅助焊盘201。其它一些实施例可以缺乏辅助焊盘201。
图5A示出了沿着第二表面102的注入层128x以及含有处理材料254的插入结构250。处理材料254可以仅提供在插入结构250的垂直区段中，或者可以在插入结构250的整个垂直延伸部之上延伸。在处理材料254在前侧处理之前提供的情形中，处理材料254可以包括诸如砷As或磷P之类的缓慢扩散的杂质。在处理材料254在前侧处理之后提供的情形中，处理材料254可以包括诸如硒Se之类的快速扩散杂质。
退火工艺包括n型杂质的扩散以在如图5B所示的半导体本体100中形成场停止层部分128a。根据提供了由处理材料254形成的原始插入结构250的实施例，n型杂质可以在前侧101处工艺处理期间从处理材料254扩散出，并且无需提供专用热退火以将n型杂质从处理材料254扩散出。通过背侧插入结构250引入的n型杂质形成了在半导体本体100中直接邻接漂移区域120的沟槽对准场停止区域128b。通过第一表面101引入的n型杂质形成了连续的场停止层部分128a。
可以在沟槽对准场停止区域128b与场停止层部分128a融合之前停止扩散工艺。根据另一实施例，在沟槽对准场停止区域128b与场停止层部分128a融合之后停止扩散工艺。沟槽对准场停止区域128b的杂质浓度具有横向梯度并且随着沿横向和垂直方向至插入结构250的距离增大而减小。沟槽对准场停止区域128b和场停止层部分128a形成了分级的或台阶状的场停止层。
从插入结构250的向外扩散可以由掩模衬垫203遮蔽，使得杂质主要从与第二表面102a相对的插入结构250的掩埋边缘而扩散出。根据一个实施例，基架层130可以与场停止层128一起形成或者在其之后形成。在扩散工艺之后，可以移除处理材料254或者采用另外材料替代处理材料254。对于其它细节参考图3A至图3B的描述说明。
图6示出了半导体器件500，例如IGBT、半导体二极管或功率IGFET，具有在漂移区域120的朝向第二表面102的部分中的反掺杂岛129，其中所示实施例涉及具有n型漂移区域120和p掺杂的反掺杂岛129的半导体器件500。可以使用参照图5A至图5B所述的方法形成反掺杂岛129，其中插入结构250中处理材料254包含p型杂质而非n型杂质。对于其它细节参照图3A和图3B的描述说明。
处理材料254可以是重掺杂多晶硅，其可以在杂质向外扩散之后重结晶以减小在反向操作模式下发生的泄漏电流。根据另一实施例，插入结构250初始地由含有合适的导电类型的杂质的单晶材料形成，其中单晶材料可以直接邻接半导体本体100的材料。
插入结构250可以具有近似相等的宽度和长度。例如插入结构250的平行于第一表面101的横截面可以是规则圆形、椭圆、卵形或具有或不具有圆化角部的矩形。根据另一实施例，至少一些插入结构250可以是具有大大超过宽度的长度的条带形状。条带可以是直的、弯曲的、急剧弯曲的和/或分支的。多个插入结构250可以分布在半导体本体100中。插入结构250可以均匀分布。根据其它一些实施例，插入结构的总体密度随着至半导体器件500中心距离增大而增大或减小。
图7涉及具有背侧插入结构250的一个实施例，包含增强了短路强健性的高导热材料255。根据一个实施例，高导热材料255是相变材料(PCM)。PCM可以在150℃与400℃之间的相变温度Tc下呈现固态-固态或固态-液态相变，例如在200℃和300℃之间。
根据一个实施例，PCM可以在相变温度Tc之下为晶体而在相变温度Tc之上为非晶体。在邻接插入结构250的半导体本体100的一部分中的短暂高电流脉冲可以加热PCM升温至相变温度Tc，使得PCM在短时间周期内(例如在50ns至200ns之间的周期内)执行从晶体至非晶体的相变。相变吸收了来自半导体本体100的潜热，而同时保持了相变温度Tc。PCM用作散热器，有效地散发热量并且抵消了否则可以损坏半导体器件500的局部加热效应。PCM的相变是可逆的，并且PCM的非晶部分可以通过合适的工艺(例如通过恢复退火)而再次转换为晶体相。恢复退火可以使用在延展的时间之上施加的适中的恢复电流。恢复电流将非晶材料加热升温至晶化温度，并且将非晶材料保持在该温度下，直至成核开始并且材料开始重结晶。可以在半导体器件100的正常工作期间执行恢复退火。
PCM可以包含盐或盐的水合物，例如MnH2O，有机PCM，例如CnH2n+2，或者可以是具有特性相变温度Tc和潜热的PCM的共熔化合物。根据一个实施例，PCM含有硫族化物，例如GeSbTe(锗-锑-碲或GST)。
根据另一实施例，高导热材料255包括CVD沉积的金刚石层或任何其它高导热材料。对于其它细节参照图3A和图3B以及图6的解释说明。
根据类似于参照图7所述的其它一些实施例，插入结构250包括可以补偿形变并且可以减小半导体器件500中机械应力的空隙。空隙可以进一步补偿在晶片合成中半导体器件500的处理期间发生的机械应力。结果，半导体器件500包括较少缺陷，例如裂缝，并且显示了更好的长期稳定性。
图8示出了半导体器件500，例如具有或不具有超级结结构的IGBT、半导体二极管、或IGFET，并且具有以至第一表面和第二表面101、120一定距离形成在半导体本体100中的掩埋的插入结构250。插入结构250可以是包括导电和/或介电子层的实心结构，或者可以包括空隙以及不包括、包括一个或多个加衬空隙的掩模衬垫。对于其它细节参照图3A和图3B以及图6的解释说明。
掩埋的插入结构250可以阻止滑动表面和线条缺陷的传播，和/或可以补偿半导体本体100中的机械应变。此外，掩埋的插入结构250可以吸附污染原子，例如氧或铜原子。可以如参照图1A至图1E或图2A至图2G所述地形成掩埋的插入结构250，其中除了图1A至图1E或图2A至图2G的背侧插入结构之外，可以完全省略减薄，或者减薄可以停止在距掩埋的插入结构250的一定距离处。
根据另一实施例，半导体器件包括半导体本体，包括在前侧处的第一表面和在背侧处平行于第一表面的第二表面，以及主要地形成为比第二表面更靠近第一表面的元件结构；以及插入结构，从第二表面延伸进入半导体本体中并且包括相变材料。
根据另一实施例，半导体器件包括半导体本体，具有在前侧的第一表面和在背侧的平行于第一表面的第二表面，以及主要地形成为比第二表面更靠近第一表面的元件结构，以及沿着第二表面的基底层，和在第一表面和基底层之间的半导体层；以及介电结构，包括在半导体层中的空隙，介电结构邻接在半导体层与基底层之间的界面。
根据另一实施例，一种制造半导体器件的方法包括在形成于半导体基底层上的第一半导体层中形成空腔，其中空腔从第一半导体层的处理表面延伸至基底层，并且通过外延在处理表面上生长第二半导体层，其中第二半导体层跨越空腔。
通过外延的生长可以在空腔的垂直突起中留下空隙，并且方法进一步包括在第二半导体层上沉积光致抗蚀剂层，通过估计空腔的光学响应而调整光刻设备至空腔的照射掩模，以及将光致抗蚀剂层曝光至穿过的或者由照射掩模反射的照射束。
尽管已经在此解释和描述了具体实施例，本领域技术人员应该知晓的是可以不脱离本发明的范围而对于所示和所述的具体实施例替代为大量备选和/或等价的实施方式。本申请意在覆盖在此所述的具体实施例的任何改变或变化。因此，其意在本发明仅由权利要求及其等价形式而限定。

Claims (20)

1.一种制造半导体器件的方法，所述方法包括：
在形成于半导体基底层上的第一半导体层中形成空腔，其中所述空腔从所述第一半导体层的处理表面至少向下延伸至所述基底层；
在所述空腔的侧壁的远离所述处理表面的部分上形成凹陷的掩模衬垫，或者在所述空腔的远离所述处理表面的部分中形成掩模插塞；以及
通过外延在所述处理表面上生长第二半导体层，其中所述第二半导体层跨越所述空腔。
2.根据权利要求1所述的方法，进一步包括：
在所述半导体基底层的表面的第一区段上形成辅助焊盘，所述辅助焊盘适用于抑制外延生长；以及
通过外延在所述表面的第二区段上选择性生长所述第一半导体层，其中所述空腔形成在所述辅助焊盘的垂直突起中。
3.根据权利要求1所述的方法，其中，刻蚀所述空腔进入所述第一半导体层中。
4.根据权利要求1所述的方法，进一步包括：
在生长所述第二半导体层之前，通过在含氢环境中对所述第一半导体层退火来封盖所述空腔，其中所述第一半导体层的材料闭塞所述空腔。
5.根据权利要求1所述的方法，进一步包括：
在生长所述第二半导体层之后，移除所述基底层的至少一部分，其中暴露了所述空腔或者所述空腔中的材料。
6.根据权利要求1所述的方法，进一步包括：
采用含杂质的处理材料至少部分地填充所述空腔；以及
退火所述处理材料以从所述处理材料将所述杂质扩散出，以在所述半导体本体中形成杂质区域，所述杂质区域直接邻接已填充的空腔，并且扩散进入所述杂质区域的杂质的杂质浓度随着距所述已填充的空腔的距离的增大而减小。
7.根据权利要求6所述的方法，其中，
所述处理材料填充进入多个空间分隔的空腔中，并且邻接所述已填充的空腔的杂质区域形成连续层。
8.根据权利要求7所述的方法，其中，
在所述已填充的空腔中所述处理材料中的杂质浓度沿垂直于在所述第一半导体层和所述第二半导体层之间的界面的垂直方向而变化。
9.根据权利要求6所述的方法，其中，
所述处理材料是多晶半导体材料，以及所述方法进一步包括：
将所述多晶半导体材料转换为单晶半导体材料。
10.根据权利要求6所述的方法，其中，
所述处理材料是单晶半导体材料。
11.根据权利要求1所述的方法，进一步包括：
在所述空腔中形成具有至少1E5cm/s的复合速率的复合结构或者相变材料。
12.根据权利要求1所述的方法，进一步包括：
在生长所述第二半导体层之后，移除所述基底层的至少一部分，其中暴露所述空腔或者所述空腔中的材料；
从所述空腔的内部选择性移除材料；
注入杂质通过已暴露的空腔的已暴露的侧壁和底部；以及
至少部分地重新填充所述空腔。
13.一种半导体器件，包括：
半导体本体，包括在前侧处的第一表面和在背侧处的平行于所述第一表面的第二表面，以及有源区域和将所述有源区域与所述半导体本体的外表面分隔的边缘终止区域，其中所述外表面连接所述第一表面和所述第二表面，并且所述有源区域中的元件结构主要地形成为比所述第二表面更靠近所述第一表面；以及
背侧插入结构，从所述第二表面延伸进入所述边缘终止区域中的所述半导体本体中。
14.根据权利要求13所述的半导体器件，其中，
所述插入结构围绕所述有源区域。
15.根据权利要求13所述的半导体器件，其中，
所述插入结构是连续的、环形的沟槽，并且包括半导体氧化物或者包括多个分隔的空腔。
16.根据权利要求13所述的半导体器件，其中，
所述插入结构包括多晶硅。
17.根据权利要求13所述的半导体器件，其中，
所述半导体器件是IGBT，并且所述插入结构包括与所述IGBT的漂移区域的导电类型互补的导电类型的杂质。
18.一种半导体器件，包括：
半导体本体，包括在前侧处的第一表面和在背侧处平行于所述第一表面的第二表面，以及主要地形成为比所述第二表面更靠近所述第一表面的元件结构；
插入结构，从所述第二表面延伸进入所述半导体本体中，所述插入结构包括相变材料、具有至少1E5cm/s的复合速度的复合结构、受主杂质或施主杂质。
19.根据权利要求18所述的半导体器件，进一步包括：
在所述半导体本体中的杂质区域，所述杂质区域直接邻接所述插入结构，并且对应于第一导电类型的杂质的杂质浓度随着距所述插入结构的距离的增大而减小。
20.根据权利要求18所述的半导体器件，其中，
所述插入结构包括多晶或单晶硅。
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