CN107039419A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN107039419A
CN107039419A CN201611060444.XA CN201611060444A CN107039419A CN 107039419 A CN107039419 A CN 107039419A CN 201611060444 A CN201611060444 A CN 201611060444A CN 107039419 A CN107039419 A CN 107039419A
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type
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impurity
conductivity type
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CN107039419B (zh
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白川彻
内藤达也
菅井勇
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明提供一种用于通过缓和SJ柱与漂移区之间的电场集中，而在一块半导体芯片内将MOSFET区、FWD区和IGBT区电连接且并联连接的最佳结构。本发明提供的半导体装置，具备：半导体基板；具有第一柱和第二柱的重复结构的超结型MOSFET部；在半导体基板与超结型MOSFET部分离而设置，并具有包括第二导电型的杂质的漂移区的并列器件部；在半导体基板并位于超结型MOSFET部与并列器件部之间的边界部，其中，边界部从一个主表面侧向另一主表面侧延伸，并且至少具有一个具有第一导电型的杂质的第三柱，第三柱比第一柱和第二柱都浅。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
以往，将IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)芯片和具有内部寄生二极管的MOSFET(Metal-Oxide-Semiconductor Field-EffectTransistor，金属氧化物半导体场效应晶体管)芯片电连接，从而将IGBT、MOSFET以及二极管并联连接(例如，参考专利文献1)。另外，已知具有IGBT和FWD(Free Wheeling Diode，续流二极管)的RC-IGBT(逆导型IGBT)(例如，参考专利文献2)。进一步地，已知在IGBT区和FWD区之间设有边界区(例如，参考专利文献3)。另外，已知在IGBT区和FWD区之间设有具有绝缘体的沟槽(例如，参考专利文献4)。进一步地，已知在元件区和终端部之间，设有随着从元件区朝向终端部，深度分阶段地变浅的p型和n型柱状区(例如，参考专利文献5)。
现有技术文献
专利文献
专利文献1：日本特开平04-354156号公报
专利文献2：日本特开2012-142537号公报
专利文献3：日本特开2014-056942号公报
专利文献4：日本特开2002-314082号公报
专利文献5：日本特开2007-335844号公报
发明内容
技术问题
目前，要求在一块半导体芯片内，将MOSFET区、FWD区以及IGBT区电连接且并联连接而设置。当MOSFET区为超结(Superjunction)(以下省略记载为SJ)型MOSFET时，与非SJ型MOSFET相比为高耐压。但由于SJ型MOSFET的SJ柱和与SJ型MOSFET邻接的FWD区或IGBT区的漂移区之间的杂质浓度差，而使电场在SJ柱和漂移区之间集中，产生雪崩电流。因此，当将MOSFET区、FWD区以及IGBT区设置于一块半导体芯片时，无法获得高耐压的半导体装置。
因此，本发明提供一种用于通过缓和SJ柱与漂移区之间的电场集中，而在一块半导体芯片内将MOSFET区、FWD区以及IGBT区电连接且并联连接的最佳结构。
技术方案
在本发明的第一形态中，具备半导体基板、超结型MOSFET部、并列器件部和边界部。超结型MOSFET部可以具有第一柱和第二柱的重复结构。第一柱和第二柱可以分别设置为从半导体基板的一个主表面侧向另一主表面侧延伸。第一柱可以具有第一导电型的杂质。第二柱可以具有第二导电型的杂质。并列器件部可以具有包括第二导电型的杂质的漂移区。并列器件部可以在半导体基板以与超结型MOSFET部分离而设置。边界部可以在半导体基板并位于超结型MOSFET部与并列器件部之间。边界部可以至少具有一个第三柱。第三柱可以从一个主表面侧向另一主表面侧延伸。第三柱可以具有第一导电型的杂质。第三柱的深度可以比第一柱和第二柱都浅。
边界部可以在半导体基板的从超结型MOSFET部朝向并列器件部的外侧方向的不同位置具有多个第三柱。多个第三柱的深度可以随着向外侧方向推进而逐渐变浅。
可以在多个第三柱的相邻的第三柱之间具有第四柱。第四柱可以具有第二导电型的杂质。第四柱的第二导电型的杂质浓度可以为漂移区中的第二导电型的杂质浓度以上。在多个第三柱中的第一导电型的杂质浓度可以为漂移区中的第二导电型的杂质浓度以上。
第四柱的深度可以比在外侧方向的反方向上邻接的第三柱的深度浅。第三柱可以具有突出区。突出区可以在第三柱的底部向外侧方向突出。
突出区可以不与在外侧方向上邻接的第四柱接触。
第四柱的深度可以与在外侧方向上邻接的第三柱的深度相等。
边界部可以在外侧方向的端部沿外侧方向连续具有两组相同深度的第三柱和第四柱。
超结型MOSFET部可以在另一主表面侧还具备缓冲区。缓冲区可以具有第二导电型的杂质。缓冲区的在边界部侧的端部位于与超结型MOSFET部的距离边界部最近的第一柱和第二柱分离的位置。
超结型MOSFET部还可以具备基区、源区、源电极、表面区和第一分离沟槽。基区可以位于第一柱与第二柱的重复结构上。基区可以具有第一导电型的杂质。源区可以包括基区的最外表面的一部分。源区可以具有第二导电型的杂质。源电极可以与源区电连接。源电极可以设置于基区上。表面区可以设于基区的最外表面且与源区不同的区域。表面区可以与设于基区上的源电极电连接。表面区可以具有比源区低的第二导电型的杂质浓度。第一分离沟槽可以从表面区的一部分向下延伸。第一分离沟槽可以延伸到达第二柱和与第二柱邻接的第一柱的边界。
边界部可以具备基区、表面区和第二分离沟槽。基区可以从超结型MOSFET部延伸而设置。表面区可以从超结型MOSFET部延伸而设置。第二分离沟槽可以从表面区的一部分向下延伸而设置。第二分离沟槽可以设为延伸到达第三柱、第四柱以及相互邻接的第三柱和第四柱的边界中的任意一个。
并列器件部可以为续流二极管部和IGBT部中的一个。
并列器件部可以为续流二极管部。半导体装置还具备IGBT部和耐压结构部。IGBT部可以在从超结型MOSFET部朝向续流二极管部的外侧方向上与续流二极管部邻接。耐压结构部可以在外侧方向上与IGBT部邻接。超结型MOSFET部、边界部、续流二极管部和IGBT部可以设置于一个半导体基板。
应予说明，上述的发明概要没有列举本发明的所有必要特征。另外，这些特征组的重新组合也可构成发明。
附图说明
图1为示出逆变器装置400的例子的图。
图2为示出第一实施方式的半导体基板10的上表面的示意图。
图3为示出第一实施方式的A1-A2截面的示意图。
图4A为示出形成漏区29的阶段的图。
图4B为示出形成漏区29和缓冲区28的阶段的图。
图4C为示出形成漂移区110的第一级的n型和p型杂质区的阶段的图。
图4D为示出形成漂移区110的第三级的n型和p型杂质区的阶段的图。
图4E为示出形成漂移区110的第五级的n型和p型杂质区，以及在最上面一级的漂移区110的整个面形成p型杂质区的阶段的图。
图4F为示出通过热扩散而形成基区22、重复结构30和重复结构60的阶段的图。
图4G为示出SJ型MOSFET部20、边界部50以及FWD部100的完成状态的图。
图5的(a)为示出没有边界部50的情况的图，图5的(b)为示出有边界部50的情况的图。
图6的(a)为示出没有边界部50的情况下的电位分布的图，图6的(b)为示出有边界部50的情况下的电位分布的图。
图7的(a)为示出没有边界部50的情况下的电场分布的图，图7的(b)为示出有边界部50的情况下的电场分布的图。
图8的(a)为示出有边界部50的情况下的电场分布的图，图8的(b)为示出B1-B2处的电场强度的图。
图9为示出第二实施方式的A1-A2截面的示意图。
图10为示出第三实施方式的A1-A2截面的示意图。
图11为示出第四实施方式的A1-A2截面的示意图。
图12为示出第五实施方式的A1-A2截面的示意图。
图13为示出第六实施方式的A1-A2截面的示意图。
图14为示出第七实施方式的A1-A2截面的示意图。
符号说明
10：半导体基板、12：一个主表面、14：另一主表面、16：外侧方向、18：内侧方向、20：SJ型MOSFET部、22：基区、24：源区、25：发射区、26：表面区、28：缓冲区、29：漏区、30：重复结构、32：p型柱、34：n型柱、36：第一分离沟槽、38：第二分离沟槽、40：栅沟槽、41：栅绝缘膜、42：栅电极、43：源电极、44：漏电极、46：层间绝缘膜、50：边界部、56：FS层、58：n型层、59：集电层、60：重复结构、62：p型柱、63：深度、64：n型柱、65：深度、66：突出区、81：绝缘膜、82：电极、90：支撑基板、91：外延层、92：区域、100：FWD部、110：漂移区、200：IGBT部、250：耐压结构部、300：半导体装置、400：逆变器装置
具体实施方式
以下通过发明的实施方式对本发明进行说明，但以下的实施方式并不对权利要求书所涉及的发明进行限定。另外，在实施方式中说明的特征组合未必全部是发明的技术方案所必须的。
图1为示出逆变器装置400的例子的图。本例的逆变器装置400具有直流电源Vcc、6个电路区块Cxy(x和y分别为1至3的自然数)和负载a～c。电路区块C11和C21串联连接而构成第一桥臂。同样地，电路区块C12和C22串联连接而构成第二桥臂，电路区块C13和C23串联连接而构成第三桥臂。第一桥臂、第二桥臂和第三桥臂相互并联连接。电路区块C11、C12以及C13的漏极端子(D)和集电极端子(C)与Vcc的正电位连接。电路区块C21、C22以及C23的源极端子(S)和发射极端子(E)与Vcc的负电位连接。
在本例中，在一个半导体基板10设有一个电路区块Cxy。各电路区块Cxy具备分别并联连接的IGBT部200、SJ型MOSFET部20和FWD部100。SJ型MOSFET部20的栅极(G)与IGBT部200的栅极(G)相互电连接。在一个电路区块Cxy的栅极(G)输入有来自外部的栅极信号Sgxy。由此，栅极(G)被导通或被截止。也就是说，各电路区块Cxy被导通或被截止。
为了进行说明，当在一个桥臂中Vcc的正电位侧的Cxy为导通，并且Vcc的负电位侧的Cxy为截止时，记载该一个桥臂为H(High的缩写)。与此相对，当在一个桥臂中Vcc的正电位侧的Cxy为截止，并且Vcc的负电位侧的Cxy为导通时，记载该一个桥臂为L(Low的缩写)。在本例中，(第一桥臂、第二桥臂、第三桥臂)以(H、L、L)、(H、H、L)、(L、H、L)、(L、H、H)、(L、L、H)和(H、L、H)的顺序变化，并且接下来返回至(H、L、L)。这样，通过适当地将各电路区块Cxy导通或截止，能够利用直流电源Vcc使三相交流的电流在负载a～c流通。
例如，在某个时刻，通过Sg11将电路区块C11导通，通过Sg22将电路区块C22导通，并通过Sg23将电路区块C23导通。这时，使电路区块C21、C12和C13截止。由此，(第一桥臂、第二桥臂、第三桥臂)实现(H、L、L)。
另外例如，在其他时刻，通过Sg11将电路区块C11导通，通过Sg12将电路区块C12导通，并通过Sg23将电路区块C23导通。这时，使电路区块C21、C22和C13截止。由此，(第一桥臂、第二桥臂、第三桥臂)实现(H、H、L)。
图2为示出第一实施方式的半导体基板10的上表面的示意图。本例的半导体基板10具有与X-Y平面平行的一个主表面。本例的半导体装置300形成于半导体基板。在本例中，半导体装置300具有SJ型MOSFET部20、边界部50、FWD部100、IGBT部200和耐压结构部250。
本例的SJ型MOSFET部20设置于半导体基板10的中央部。边界部50具有缓和SJ型MOSFET部20和并列器件部之间的电场集中的功能。另外，在SJ型MOSFET部20的±Y方向上与SJ型MOSFET部20邻接地设有边界部50。
与边界部50邻接地设有并列器件部。因此，以SJ型MOSFET部20、边界部50以及并列器件部的顺序进行配置。并列器件部可以为FWD部100和IGBT部200中的一个。在本例中，并列器件部是FWD部100。在本例中，将从SJ型MOSFET部20朝向FWD部100的方向设为外侧方向16。将与外侧方向16相反的方向设为内侧方向18。
在并列器件部的外侧方向16上与并列器件部邻接地还设有其他并列器件部。其他并列器件部可以为与邻接的并列器件部不同的元件。其他并列器件部可以为FWD部100和IGBT部200中的另一个。在本例中，其他并列器件部为IGBT部200。
应予说明，在其他的例子中，并列器件部可以为IGBT部200，其他并列器件部可以为FWD部100。也就是说，可以从中央部朝向外侧方向16以SJ型MOSFET部20、边界部50、IGBT部200和FWD部100的顺序设置各元件。
FWD部100和IGBT部200与SJ型MOSFET部20相比，在动作时容易发热。当没有进行适当放热时，由于热失控而存在元件被破坏的隐患。在本例中，将FWD部100和IGBT部200设置在比SJ型MOSFET部20靠向外侧方向16的位置。由此，与使SJ型MOSFET部20位于比FWD部100和IGBT部200靠向外侧方向16的位置的情况相比，能够更有效地将FWD部100和IGBT部200的热向芯片的外侧方向16放出。
在本例中，在IGBT部200的外侧方向16上与IGBT部200邻接地设有耐压结构部250。耐压结构部250还可以与包括SJ型MOSFET部20、边界部50、FWD部100和IGBT部200的元件区的±X方向的端部邻接。也就是说，耐压结构部250可以以包围元件区的方式设置。与没有耐压结构部250的情况相比，耐压结构部250具有使半导体基板10的耐压提高的功能。耐压结构部250具有在施加高电压时使耗尽层扩张而缓和电场集中的功能。具体来说，耐压结构部250可以具有以包围元件区的方式设置的保护环和场板中的至少一个。
图3为示出第一实施方式的A1-A2截面的示意图。如图3所示，半导体装置300具备SJ型MOSFET部20、FWD部100和边界部50。并列器件部具有在半导体基板10与SJ型MOSFET部20分离地设置，并包括n型杂质的漂移区11。
本例的半导体基板10具有一个主表面12和另一主表面14。在半导体基板10，SJ型MOSFET部20、边界部50和FWD部100可以共用源电极43、p型的基区22和漏电极44。源电极43可以与电路区块Cxy的源极端子(S)电连接。漏电极44可以与电路区块Cxy的漏极端子(D)电连接。
在本说明书中，“上”和“上方”是指+Z方向的位置。与之相对，“下”、“下方”和“底”是指-Z方向的位置。在本说明书中，X方向和Y方向是相互垂直的方向，Z方向是与X-Y平面垂直的方向。X方向、Y方向和Z方向构成所谓的右手坐标系。应予说明，Z方向并不一定表示与地面垂直的方向。本例的+Z方向是从漏电极44朝向源电极43的方向。另外，本例的X-Y平面是与一个主表面12和另一主表面14平行的方向。
另外，在本说明书中，n或p分别表示电子或空穴为多数载流子。另外，对于标记在n或p的右上的+或-，+是指载流子浓度比未标记+的物质的载流子浓度高，-是指载流子浓度比未标记-的物质的载流子浓度低。在本说明书中，设第一导电型为p型，设第二导电型为n型。但是，在其他例子中，也可以设第一导电型为n型，设第二导电型为p型。
(SJ型MOSFET部20)本例的SJ型MOSFET部20从下开始依次具有漏区29、缓冲区28、重复结构30和基区22。
漏区29具有作为第二导电型的n+型的杂质。漏区29可以具有1E+17[cm-3]以上且1E+21[cm-3]以下的n型的杂质浓度。缓冲区28具有作为第二导电型的n型的杂质。缓冲区28可以具有1E+14[cm-3]以上且1E+15[cm-3]以下的n型的杂质浓度。应予说明，在本说明书中，E表示10的指数，例如E+16表示1016，E-16表示10-16。
基区22具有作为第一导电型的p-型的杂质。基区22位于重复结构30上。基区22可以具有E+16[cm-3]以上且E+20[cm-3]以下的p型的杂质浓度，更优选地可以具有E+16[cm-3]以上且E+18[cm-3]以下的p型的杂质浓度。当在栅电极42施加有预定的正电位时，在栅绝缘膜41附近的基区22形成沟道区。
重复结构30具有p型柱32和n型柱34的重复结构，其中，p型柱32作为具有第一导电型的杂质的第一柱，n型柱34作为具有第二导电型的杂质的第二柱。p型柱32和n型柱34在外侧方向16上邻接地交替设置。p型柱32和n型柱34分别从一个主表面12侧向另一主表面14侧延伸而设置。p型柱32可以具有1E+14[cm-3]以上且1E+17[cm-3]以下的p型的杂质浓度。n型柱34可以具有1E+14[cm-3]以上且1E+17[cm-3]以下的n型的杂质浓度。
SJ型MOSFET部20具有栅沟槽40。栅沟槽40的底部到达n型柱34。栅沟槽40具有栅绝缘膜41和栅电极42。栅绝缘膜41是与栅沟槽40的侧壁和底部接触而形成的绝缘体的薄膜。栅电极42与栅绝缘膜41接触而形成。本例的栅电极42由多晶硅等导电性材料形成。栅电极42可以通过层间绝缘膜46而与源电极43电分离，且与电路区块Cxy的栅极端子(G)电连接。
源区24具有作为第二导电型的n+型的杂质。源区24包括基区22的最外表面的一部分。该最外表面为一个主表面12。本例的源区24被设置为夹着栅沟槽40。源区24的Y方向长度可以为大约5[μm]。源区24与设置于基区22上的源电极43电连接。
当在源电极43和漏电极44之间施加了预定的电位差，并在栅电极42施加了预定的正电位时，在SJ型MOSFET部20流通电流Ic。在该情况下，电流Ic从漏电极44开始，按顺序经过漏区29、缓冲区28、n型柱34、基区22中的沟道区和源区24，而流向源电极43。将电流Ic流通的状态称为导通状态。
(边界部50)边界部50位于SJ型MOSFET部20和FWD部100之间。边界部50具有从SJ型MOSFET部20延伸而设置的基区22。边界部50在基区22的下方至少具有一个作为具有第一导电型的杂质的第三柱的p型柱62。本例的边界部50具有多个p型柱62。本例的边界部50具有五个p型柱62，但p型柱62的数量可以不限于五个。
p型柱62从一个主表面12侧向另一主表面14侧延伸。距离SJ型MOSFET部20最近的p型柱62可以具有与SJ型MOSFET部20的p型柱32和n型柱34相同的深度。但是，其他的p型柱62的深度比SJ型MOSFET部20的p型柱32和n型柱34浅。在本例中，多个p型柱62的深度随着向外侧方向16推移而逐渐设置得浅。
应予说明，在本例中深度是指以基区22的下端为起点，从该起点向下到达层、膜、区域或柱的终点为止的长度。深度浅是指从该起点到下方的终点为止的长度短。作为深度浅的其他表现，可以在对多个柱进行比较时，将柱的另一主表面14侧的端部(即，底部)更靠近一个主表面12侧的一方作为深度浅。
n型柱64的n型的杂质浓度可以为漂移区110中的n型的杂质浓度以上。另外，多个p型柱62中的p型的杂质浓度可以为漂移区110中的n型的杂质浓度以上。p型柱62可以具有1E+15[cm-3]以上且1E+17[cm-3]以下的p型的杂质浓度。n型柱64可以具有1E+15[cm-3]以上且1E+17[cm-3]以下的n型的杂质浓度。漂移区110可以具有1E+13[cm-3]以上且1E+15[cm-3]以下的n型的杂质浓度。
在没有边界部50的情况下，如果SJ型MOSFET部20为导通状态，则耗尽层从基区22向下方扩展。除此之外，在该情况下，耗尽层从FWD部100朝向SJ型MOSFET部20沿向下的方向扩展。FWD部100的漂移区110的杂质浓度比SJ型MOSFET部20的重复结构30中的杂质浓度低。因此，与重复结构30相比，耗尽层容易在漂移区110扩展。其结果，由于电场仅集中在位于最外侧方向16的p型柱32的底部附近，而产生雪崩电流，耐压容易下降，因此难以将SJ型MOSFET部20和FWD部100并列配置在一块芯片内。
与此相对，本例的边界部50在外侧方向16上具有逐渐变浅的p型柱62。由此，能够在逐渐变浅的p型柱62底部分别分担电场，因此能够使从FWD部100扩展的耗尽层逐渐向内侧方向18和下方扩展，能够提高耐压。因此，由于能够防止电场仅集中在位于最外侧方向16的p型柱32的底部附近，所以耐压下降消失。FWD部100仅是并列器件部的一个例子，在将IGBT部200设置于FWD部100的位置的情况下也能够获得相同的效果。
边界部50在多个p型柱62中的相邻的p型柱62之间，还具有作为具有第二导电型的杂质的第四柱的n型柱64。本例的n型柱64的深度与在外侧方向16上邻接的p型柱62的深度相等。应予说明，在本例中，深度相等并不意味着深度严格一致。深度相等也可以具有±5[nm]程度的偏差。
n型柱64的深度65比在外侧方向16的反方向上邻接的p型柱的深度63浅。因此，在n型柱64的外侧方向16上邻接的p型柱62的底部的杂质，由于不存在n型柱64的扩散，所以容易向外侧方向16扩散。由此，p型柱62在底部具有向外侧方向16突出的突出区66。应予说明，突出区66不与在外侧方向16上邻接的n型柱64接触。
另一方面，当p型柱62与在外侧方向16上邻接的n型柱64的深度相同时，突出区66消失。因此来自FWD部100的耗尽层的扩展在n型柱64的底部被抑制，所以耗尽层的扩展变慢，耐压下降。通过各p型柱62具有突出区66，而使在边界部50中邻接的p型柱62的底部之间的距离缩短。因此，在重复结构60的底部，耗尽层变得容易扩展。因此在本例中，与p型柱62与在外侧方向16上邻接的n型柱64为相同深度的情况相比较，通过形成突出区66，能够提高耐压。
n型的电场终止层(以下称为FS层56)与n+型的n型层58在边界部50以及并列器件部以共用的方式设置。FS层56具有防止在并列器件部的漂移区110向下方延伸的耗尽层到达n型层58的功能。应予说明，在FWD部100，通过p-型的基区22和漂移区110，形成有pn结二极管。
图4A为示出形成漏区29的阶段的图。首先，在支撑基板90上形成一级外延层91。支撑基板90可以为FZ基板或外延基板。另外，支撑基板90的杂质浓度可以为任意的值。外延层91可以为与漂移区110具有相同杂质浓度的n型的外延层。之后，在区域92注入形成漏区29的n型的杂质。区域92也配置在比SJ型MOSFET部20靠外侧方向16配置的边界部50内。
图4B为示出形成漏区29和缓冲区28的阶段的图。在外延层91上重复进行外延层的形成和向区域92注入n型杂质。该重复可以在五次以下。之后，在最上面一级形成外延层91，在区域92注入形成缓冲区28的n型的杂质。区域92的形成缓冲区28的n型的杂质浓度可以比形成漏区29的n型的杂质浓度低。
图4C为示出形成漂移区110的第一级的n型和p型杂质区的阶段的图。首先，形成在SJ型MOSFET部20、边界部50和FWD部100共用的层。在本例中，该共用的层可以是与漂移区110相同的n型的外延层。接下来，在n型的外延层选择性地注入n型和p型杂质。在SJ型MOSFET部20中，为了形成重复结构30，整体上选择性地注入n型和p型杂质。与此相对，在边界部50中，为了形成重复结构60，仅在距离SJ型MOSFET部20最近的区域选择性地注入n型和p型杂质。
图4D为示出形成漂移区110的第三级的n型和p型杂质区的阶段的图。与第一级相同，重复进行n型的外延层的形成以及n型和p型杂质的选择性注入。但是，在边界部50中，随着级数增加，将选择性注入n型和p型杂质的区域向外侧方向16增大。在第一级中，仅在距离SJ型MOSFET部20最近的区域形成一组n型和p型杂质区。与此相对，在第二级中形成两组n型和p型杂质区，在第三级中形成三组n型和p型杂质区。
图4E为示出形成漂移区110的第五级的n型和p型杂质区，以及在最上面一级的漂移区110的整个面形成p型杂质区的阶段的图。在本例中，重复五次n型外延层的形成和杂质的选择性注入。但是，重复次数只要不脱离发明的主旨，可以比五次少也可以比五次多。接下来，在最上部形成与漂移区110相同的n型外延层。接下来，在该n型外延层的上部整体注入p型杂质。由此，在后续的热处理工序中，形成p型的基区22。
n型外延层的形成和杂质的选择性注入可以重复一次以上且二十次以下。在该情况下，从基区22上至p型柱32的底为止的长度可以在10μm以上且200μm以下。
图4F为示出通过热扩散而形成基区22、重复结构30和重复结构60的阶段的图。在该阶段中，对半导体基板10进行热处理。在最上部的漂移区110中，p型杂质均匀地向下扩散，从而形成p型的基区22。在漂移区110的下部，区域92的n型杂质均匀地扩散，形成n型的缓冲区28、n+型的漏区29。另外，在漂移区110中，n型和p型杂质大致呈放射状地热扩散。由此，形成多个球体沿Z方向层叠那样的形状的杂质扩散区域。应予说明，多个球体沿Z方向层叠那样的形状只是示意性地示出杂质浓度特别高的区域。应予说明，在p型柱62的底部形成有突出区66。
图4G为示出SJ型MOSFET部20、边界部50以及FWD部100的完成状态的图。SJ型MOSFET部20可以不与FWD部100邻接而与IGBT部200邻接。首先，就表面结构而言，通过图案化以及蚀刻形成栅沟槽40，并依次形成栅绝缘膜41和栅电极42。接下来，通过图案化以及注入n型杂质，形成n型的源区24，之后，通过接触图案(Contact pattern)形成层间绝缘膜46。接下来，通过金属溅射形成源电极43。对于背面结构，通过蚀刻去除支撑基板90，从背面(另一主表面14侧)注入形成FS层56和n型层58的n型的杂质以及形成集电层59的p型的杂质。之后，通过热处理进行活化，从而形成FS层56、n型层58和集电层59。再之后，通过金属溅射形成漏电极44。应予说明，对于集电层59，参考图14的例子。
在FWD部100和SJ型MOSFET部20，从背面注入形成FS层56和n型层58的n型的杂质。对于IGBT部200，可以通过背面图案化方法而注入形成集电层59的p型的杂质，之后，将Se(硒)、H+(质子)、或P(磷)作为形成FS层的n型的杂质进行注入而形成FS层56。
另外，作为其他的制造方法，可以通过蚀刻来去除支撑基板90，并从背面整个面注入形成FS层56的n型的杂质和形成IGBT部200的集电层59的p型的杂质，之后，通过背面图案化方法在除了形成IGBT部200的集电层59的区域以外的区域，注入形成n型层58的n型的杂质。
进一步地，作为其他的制造方法，可以通过蚀刻来去除支撑基板90，并从背面整个面注入形成FS层56的n型的杂质和形成n型层58的n型的杂质，之后，通过背面图案化方法仅在形成IGBT部200的集电层59的区域注入形成IGBT部200的集电层59的p型的杂质。应予说明，虽然在本例中没有详细记载，但也可以不使用支撑基板90而使用n型的半导体基板，通过对半导体基板的背面进行研磨并进行薄化而作为n型层58。
图5的(a)为示出没有边界部50的情况的图，图5的(b)为示出有边界部50的情况的图。在图5的(a)所示的结构下，进行了后述的图6的(a)以及图7的(a)中的模拟。在图5的(a)、图6的(a)和图7的(a)中，SJ型MOSFET部20和FWD部100直接邻接。
与此相对，在图5的(b)所示的结构下，进行了后述的图6的(b)以及图7的(b)中的模拟。在图5的(b)、图6的(b)和图7的(b)中，如图3、图4A～图4F中所述，在SJ型MOSFET部20和FWD部100之间设置了边界部50。应予说明，虽然在图5的(a)和图5的(b)中显示比例不同，但SJ型MOSFET部20中的各结构的大小在图5的(a)和图5的(b)中设为相同。应予说明，在p型柱32上方的栅沟槽40的相邻两侧设有后述的第一分离沟槽。
图6的(a)为示出没有边界部50的情况下的电位分布的图，图6的(b)为示出有边界部50的情况下的电位分布的图。在图6的(a)中，从距离FWD部100最近的p型柱32至FWD部100，等电位线的变化急剧。因此，在距离FWD部100最近的p型柱32的底部，特别是在底部的左侧，等电位线的间隔狭窄。与此相对，在图6的(b)中，通过将边界部50的p型柱32的深度配置为向FWD部100侧逐渐变浅，等电位线的变化与图6的(a)相比比较平缓。另外，在图6的(b)中，在SJ型MOSFET部20的最外侧方向16的p型柱32的底部，没有等电位线的急剧变化。
图7的(a)为示出没有边界部50的情况下的电场分布的图，图7的(b)为示出有边界部50的情况下的电场分布的图。在图7的(a)中，在距离FWD部100最近的p型柱32的底部(特别是底部的左侧)，由于图6的(a)的等电位线的变化变得急剧，因此电场非常地集中。以EH表示该电场集中部位。应予说明，在其他的p型柱32中，没有与距离FWD部100最近的p型柱32的底部相同程度地集中电场的部位。
与此相对，在图7的(b)中，在边界部50的各p型柱62的底部具有电场集中部位EH。但是图7的(b)的EH的强度与图7的(a)的EH的强度相同或者比其弱。另外，由于在内侧方向18上，p型柱62逐渐变深，因此能够在各p型柱62上分担电场，耗尽层容易从FWD部100扩展到SJ型MOSFET部20。因此，能够抑制雪崩电流，与图7的(a)相比，图7的(b)能够提高耐压。应予说明，在图6的(a)和图7的(a)中，将150℃的上限耐压设为450V，与此相对，在图6的(b)和图7的(b)中，能够将上限耐压设为850V。
图8的(a)为示出有边界部50的情况下的电场分布的图，图8的(b)为示出B1-B2处的电场强度的图。如图8的(a)所示，在穿过在边界部50中逐渐变深的p型柱62的底部的B1-B2线上的电场强度[V/cm]如图8的(b)所示，能够在各p型柱62的底部将电场强度以大致恒定的比例分担给各p型柱62。
图9为示出第二实施方式的A1-A2截面的示意图。本例的重复结构60具有p型柱62’，该p型柱62’具有与在外侧方向16上邻接的n型柱64相同的深度，并且没有底部的突出区66。这一点与第一实施方式不同。另外，没有突出区66的p型柱62’的底部与在p型柱62’的外侧方向16上与p型柱62’接近的p型柱62和n型柱64的底部之间的高度差b设为高度差a的两倍以上的高度，其中，高度差a是没有突出区66的p型柱62’的底部与在p型柱62’的内侧方向18上与p型柱62’接近的p型柱62和n型柱64的底部之间的高度差。由此，电场集中在产生高度差b的边界部50的配置有突出区66的p型柱62，因此能够防止电场集中在SJ型MOSFET部20。应予说明，设仅有一处没有突出区66的p型柱62’。
图10为示出第三实施方式的A1-A2截面的示意图。本例的边界部50在外侧方向16的端部沿外侧方向16连续具有两组相同深度的p型柱62和n型柱64。这一点与第一实施方式不同。在本例中，与第一实施方式相比较，在重复结构60的底部耗尽层变得容易扩展。因此在本例中，与第一实施方式相比较，能够使耐压提高。应予说明，可以将本例的结构与第二实施方式组合。
应予说明，若各p型柱62和n型柱64的在外侧方向16上的宽度与第一实施方式相同，则在一个主表面12上边界部50所占面积变得比第一实施方式大。应予说明，也可以使各p型柱62和n型柱64的宽度变窄，使边界部50所占面积与第一实施方式相同。
图11为示出第四实施方式的A1-A2截面的示意图。在本例中，使缓冲区28和漏区29向内侧方向18后退。也就是说，本例的缓冲区28和漏区29的边界部50侧的端部位于与SJ型MOSFET部20中的距离边界部50最近的p型柱62和n型柱64分离的位置。这一点与第一实施方式不同。
在本例中，直到边界部50侧的SJ型MOSFET部20的底部为止成为漂移区110。由于漂移区110与重复结构30的p型柱32和n型柱34相比杂质浓度低，因此耗尽层容易扩展。因此，在本例中，与第一实施方式相比，能够使耗尽层更向内侧方向18扩展。结果，耐压比第一实施方式提高。应予说明，也可以将本例的结构与第二实施方式和第三实施方式组合。
图12为示出第五实施方式的A1-A2截面的示意图。本例的SJ型MOSFET部20还具备表面区26和第一分离沟槽36。这一点与第一实施方式不同。
表面区26设于基区22的最外表面且与源区24不同的区域。本例的表面区26设在源区24与第一分离沟槽36之间，以及两个第一分离沟槽36之间。表面区26具有比源区24低的n型的杂质浓度。表面区26与设置在基区22上的源电极43电连接。
基区22和表面区26构成表面区二极管。基区22和n型柱34构成第一体二极管。另外，p型柱32与缓冲区28构成第二体二极管。表面区二极管与第一体二极管相互反向串联连接。同样地，表面区二极管和第二体二极管也相互反向串联连接。以下，将表面区二极管、第一体二极管以及第二体二极管统称为合成体二极管。
在反向偏压时(电路区块Cxy的截止时)，源电极43与漏电极44相比，变为高电位。在本例中，在反向偏压时(截止时)，电流不从SJ型MOSFET部20的源电极43流向漏电极44。在本例中，反向偏压时的电流在FWD部100中流通，但在SJ型MOSFET部20中，电流的流通变得极少。这是由于在基区22和表面区26之间产生电位差，Vf(正向电压)变高。只要不向合成体二极管施加超过相当于SJ型MOSFET部20的Vf的电位差的电压，电流的流通就变得极少。
假设在表面区26具有与源区24相同的n型杂质浓度，并具有与源区24相同的深度的情况下，难以取得基区22和p型柱32的电位，耗尽层难以扩展。那么，将表面区26的n型杂质的浓度设为基区22的p型杂质的浓度以上，并使表面区26的深度比源区24的深度浅。由此，在基区22和p型柱32中，耗尽层变得容易扩展。由此，合成体二极管能够维持反向偏压时的耐压。
本例的表面区26具有比源区24低的n型的杂质浓度。源区24的n型杂质浓度可以在E+17[cm-3]以上且E+21[cm-3]以下。与此相对，表面区26的杂质浓度可以根据耐压而确定。表面区26的杂质浓度也可以是基区22的一倍以上，例如在耐压为600V的情况下优选为一倍至两倍的程度。
在本例中，通过设置表面区26，能够将SJ型MOSFET部20的合成体二极管的Vf设置为比并联连接的FWD部100的Vf高。因此，与没有表面区26的情况相比，能够使截止时的电流更多地在FWD部100而不是SJ型MOSFET部20流通。
第一分离沟槽36从表面区26的一部分向下延伸到达p型柱32和n型柱34的边界。第一分离沟槽36与栅沟槽40相同地，具有绝缘膜81和电极82。绝缘膜81是与第一分离沟槽36的侧壁和底部接触而形成的绝缘体的薄膜。电极82与绝缘膜81接触而形成。本例的电极82由多晶硅等导电性材料形成。本例的电极82通过层间绝缘膜46而与源电极43电分离，但与栅电极42电连接。
应予说明，可以不在第一分离沟槽36上设置层间绝缘膜46，使电极82与源电极43电连接，从而取代将电极82和栅电极42电连接。由此，因为能够降低浮置区的电容，因此具有提高源极-栅极间电压(VGS)以及源极-漏极间电压(VDS)的开关特性的效果。应予说明，浮置区是指左右被栅沟槽40和第一分离沟槽36夹住，上下被源区24、表面区26和n型柱34夹住的区域。应予说明，也可以将本例的结构与第二实施方式至第四实施方式进行组合。
图13为示出第六实施方式的A1-A2截面的示意图。本例的边界部50具备表面区26和第二分离沟槽38。这一点与第五实施方式不同。表面区26为从SJ型MOSFET部20延伸而设置。也就是说，表面区26在SJ型MOSFET部20和边界部50具有相同结构。
第二分离沟槽38为从表面区26的一部分向下延伸到达p型柱62、n型柱64以及相互邻接的p型柱62和n型柱64的边界中的任意一个而设置。本例的第二分离沟槽38以到达边界部50的最外侧方向16上的p型柱62的外侧方向16的侧部的方式设置。
在本例中，边界部50的基区22与表面区26构成表面区二极管。边界部50的基区22和表面区26与SJ型MOSFET部20构成为一体。通过在边界部50也设置表面区二极管，使将SJ型MOSFET部20和边界部50合在一起的表面区二极管的面积变得比仅在SJ型MOSFET部20的表面区二极管的面积大。因此，边界部50的表面区二极管使SJ型MOSFET部20的合成体二极管的Vf增大。因此，能够使SJ型MOSFET部20和边界部50的Vf比SJ型MOSFET部20单独的Vf高。
第二分离沟槽38与第一分离沟槽36相同地，具有绝缘膜81和电极82。本例的电极82通过层间绝缘膜46而与源电极43电分离，并与栅电极42电连接。然而，与第一分离沟槽36相同地，也可以将第二分离沟槽38的电极82与源电极43电连接。应予说明，也可以将本例的结构与第二实施方式至第四实施方式进行组合。
图14为示出第七实施方式的A1-A2截面的示意图。本例的并列器件部为IGBT部200。这一点与第一实施方式不同。IGBT部200在FS层56下具有p+型的集电层59。另外，IGBT部200在基区22具有与SJ型MOSFET部20相同的栅沟槽40，并取代源区24而具有n+型的发射区25。
但是，本例的IGBT部200不具有与SJ型MOSFET部20相同的重复结构30。取而代之，本例的IGBT部200具有n型的漂移区110。如果向漏电极44(也可以称为集电极)施加比源电极43(也可以称为发射电极)高的预定电位，向栅电极42施加正脉冲，则在基区22形成沟道。这时，空穴被从集电层59向漂移区110注入，电子被从发射区25注入。由此，在漂移区110产生电导率调制，漂移区110成为低电阻状态。因此，从漏电极44向源电极43流通大电流。应予说明，也可以将本例的结构与第二实施方式至第六实施方式进行组合。
以上，利用实施方式对本发明进行了说明，但本发明的技术范围不限于上述实施方式所记载的范围。可以对上述实施方式进行各种变更和改进对本领域技术人员来说是显而易见的。从权利要求书的记载可知，进行了那样的变更或改进的方式也可包括于本发明的技术范围内。
权利要求书、说明书以及附图中所示的装置、系统、程序和方法中的动作、顺序、步骤和阶段等各个处理的执行顺序并未特别明示“之前”、“预先”等，另外，应注意，只要不是后续处理中需要使用之前处理的结果，就可以按任意顺序实现。关于权利要求书、说明书和附图中的动作流程，即使为了方便而使用“首先”、“接下来”等进行了说明，也并不意味着必须以该顺序实施。

Claims (12)

1.一种半导体装置，其特征在于，具备：
半导体基板；
超结型MOSFET部，具有第一柱和第二柱的重复结构，其中，第一柱和第二柱分别设置为从所述半导体基板的一个主表面侧向另一主表面侧延伸，第一柱具有第一导电型的杂质，第二柱具有第二导电型的杂质；
并列器件部，在所述半导体基板与所述超结型MOSFET部分离而设置，并具有包括第二导电型的杂质的漂移区；以及
边界部，在所述半导体基板并位于所述超结型MOSFET部与所述并列器件部之间，
其中，所述边界部至少具有一个从所述一个主表面侧向所述另一主表面侧延伸，并且具有第一导电型的杂质的第三柱，
所述第三柱的深度比所述第一柱和所述第二柱都浅。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述半导体基板的从所述超结型MOSFET部朝向所述并列器件部的外侧方向的不同位置，所述边界部具有多个所述第三柱，
多个所述第三柱的深度随着向所述外侧方向推进而逐渐变浅。
3.根据权利要求2所述的半导体装置，其特征在于，
在多个所述第三柱中的相邻的所述第三柱之间还具有第四柱，所述第四柱具有第二导电型的杂质，
所述第四柱的第二导电型的杂质浓度为所述漂移区中的所述第二导电型的杂质浓度以上，
在多个所述第三柱中的第一导电型的杂质浓度为所述漂移区中的所述第二导电型的杂质浓度以上。
4.根据权利要求3所述的半导体装置，其特征在于，
所述第四柱的深度比在所述外侧方向的反方向上邻接的所述第三柱的深度浅，
所述第三柱具有在所述第三柱的底部向所述外侧方向突出的突出区。
5.根据权利要求4所述的半导体装置，其特征在于，
所述突出区不与在所述外侧方向上邻接的第四柱接触。
6.根据权利要求3至5中任一项所述的半导体装置，其特征在于，
所述第四柱的深度与在所述外侧方向上邻接的所述第三柱的深度相等。
7.根据权利要求3所述的半导体装置，其特征在于，
所述边界部在所述外侧方向的端部沿所述外侧方向连续具有两组相同深度的所述第三柱和所述第四柱。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，
所述超结型MOSFET部在所述另一主表面侧还具备具有第二导电型的杂质的缓冲区，
所述缓冲区的边界部侧的端部位于与所述超结型MOSFET部中的距离所述边界部最近的所述第一柱和所述第二柱分离的位置。
9.根据权利要求1至8中任一项所述的半导体装置，其特征在于，
所述超结型MOSFET部还具备：
基区，位于所述第一柱与所述第二柱的重复结构上，并具有第一导电型的杂质；
源区，包括所述基区的最外表面的一部分，并具有第二导电型的杂质；
源电极，与所述源区电连接，并设置于所述基区上；
表面区，设于所述基区的所述最外表面且与所述源区不同的区域，与设于所述基区上的所述源电极电连接，并具有比所述源区低的第二导电型的杂质浓度；以及
第一分离沟槽，从所述表面区的一部分向下延伸到达所述第二柱和与所述第二柱邻接的所述第一柱的边界。
10.根据权利要求9所述的半导体装置，其特征在于，
所述边界部具备：
所述基区，从所述超结型MOSFET部延伸而设置；
所述表面区，从所述超结型MOSFET部延伸而设置；以及
第二分离沟槽，从所述表面区的一部分向下延伸到达所述第三柱、所述第四柱以及相互邻接的所述第三柱和所述第四柱的边界中的任意一个而设置。
11.根据权利要求1至10中任一项所述的半导体装置，其特征在于，
所述并列器件部为续流二极管部和IGBT部中的一个。
12.根据权利要求11所述的半导体装置，其特征在于，
所述并列器件部为所述续流二极管部，
所述半导体装置还具备：
所述IGBT部，在从所述超结型MOSFET部朝向所述续流二极管部的外侧方向上与所述续流二极管部邻接；和
耐压结构部，在所述外侧方向上与所述IGBT部邻接，
所述超结型MOSFET部、所述边界部、所述续流二极管部和所述IGBT部设置于一个所述半导体基板。
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CN114883380B (zh) * 2021-06-10 2023-12-22 上海林众电子科技有限公司 一种绝缘栅半导体器件及其制备方法

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