CN104752401A - 柔性微电子组件和方法 - Google Patents
柔性微电子组件和方法 Download PDFInfo
- Publication number
- CN104752401A CN104752401A CN201410858222.7A CN201410858222A CN104752401A CN 104752401 A CN104752401 A CN 104752401A CN 201410858222 A CN201410858222 A CN 201410858222A CN 104752401 A CN104752401 A CN 104752401A
- Authority
- CN
- China
- Prior art keywords
- cross tie
- tie part
- circuit board
- micromodule
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
- H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16111—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75253—Means for applying energy, e.g. heating means adapted for localised heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
- H01L2224/8123—Polychromatic or infrared lamp heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
- H01L2224/83204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structure Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
本公开内容总体上涉及包括衬底和电子部件的系统和方法。所述衬底包括包含孔的电路板、布线层和至少部分地设置在所述孔内的第一互连件部分。所述电子部件包括耦合到所述第一互连件部分的第二互连件部分,以在所述电子部件与所述布线层之间形成互连件。
Description
技术领域
本文中的公开内容总体上涉及柔性微电子组件以及相关的方法。
背景技术
诸如电子芯片封装、可能或已经电气和/或机械地固定到印刷电路版(PCB)或其它电路版的芯片封装、分立的电子部件等的微电子组件早已利用互连件来将组件的电子部件耦合到组件内部或外部的其它部件。互连件可以例如通过将焊球耦合到相对的焊盘的方式而被形成为永久或半永久的瓦连件,或者可以通过使用插接件(socket)等形成暂时的互连件或使互连件容易解耦。PCB内或微电子组件内的迹线可以耦合到焊盘或凸块和/或插接件,并且布线到发送到或接收自微电子组件的各种部件的电信号的中间点或最初起点和/或终点,以及布线到微电子组件所耦合到的位置。
附图说明
图1是示例性实施例中的微电子组件的简要截面图。
图2A-2C示出了示例性实施例中的通过施加热量的微电子组件的形成和分离。
图3是示例性实施例中的微电子组件的窄视图。
图4是示例性实施例中的微电子组件的简要截面图。
图5是示例性实施例中的处于弯曲状况下的微电子组件的简要截面图。
图6是示例性实施例中的用于制作微电子组件的流程图。
图7是示例性实施例中的包含至少一个微电子组件的电子设备的框图。
具体实施方式
下面的描述和附图充分示出了特定实施例,以使本领域技术人员能够实践该特定实施例。其它实施例可以包含结构上、逻辑上、电气、工艺以及其它改变。一些实施例的部分和特征可以被包括在其它实施例的部分和特征中,或可以被替换为其它实施例的部分和特征。权利要求中阐述的实施例包括那些权利要求的所有可用的等同形式。
微电子组件通常实质上是刚性的,至少部分是由于组成该组件的部件。尽管一些微电子组件可以是局部柔性的,其中板是柔性的或包括柔性衬底,但是通常这种组件在组件的部件周围实质上并非柔性的。例如,电子芯片可以包括包装在实质上非柔性的电介质材料中的实质上非柔性的硅管芯。无论微电子组件有多少部分是柔性的,微电子组件的包括电子芯片的部分通常或本质上与电子芯片一样实质上为非柔性的。在电子芯片所附接的PCB或衬底为柔性的程度上,弯曲PCB或衬底可能导致电子芯片与PCB或衬底之间的互连件的破损。
已经发展了微电子组件和相关的制造工艺,可以增大微电子组件的柔性,即使在相对非柔性的单个部件附近。PCB或衬底(此后被统称为衬底,但不限于此)可以被构建成柔性的(尽管本文中公开的组件和方法完全适用于刚性或实质上刚性的衬底),并且其中形成有孔。互连件的衬底部分可以位于孔内。通过使互连件的部件部分与互连件的衬底部分相接触并且将二者结合形成互连件来使部件与板配对。如本文中所公开的,互连件可以因此留在原位而不会过度延伸衬底。
图1是示例性实施例中的微电子组件100的简要截面图。如所示出的,微电子组件包括包含互连件焊盘104的芯片封装102和包含PCB 108、布线层110、以及形成在PCB 108中的孔114内的互连件焊料凸块112的衬底106。焊盘104和焊料凸块112形成互连件116,互连件116至少部分地提供芯片封装102与布线层110之间的导电性。
芯片封装102可以包括封装电介质118内的硅管芯(被遮盖)。焊盘104可以由铜或其它适合的导电材料形成。焊盘104通过电介质118电耦合到管芯。焊盘104和焊料凸块112、以及互连件116通常可以是非导电连接,或可以整体上或部分地被非导电连接器替代。因此,微电子组件100可以至少部分地通过各种适合的紧固件来机械固定,其中紧固件可以以与本文中所公开的互连件116相同或相似的方式进行配置。
如所示出的,焊料凸块112或第一互连件部分电耦合到布线层110,并且位于PCB 108中的孔114内。布线层110可以由铜迹线形成或包括铜迹线,所述铜迹线单独耦合到相关联的焊料凸块112。布线层110实质上可以是柔性的。PCB 108则不同,其实质上可以是刚性的。然而,由于焊料凸块112位于PCB 108的孔114内,布线层110的弯曲可以允许焊料凸块112的一个或多个自由度至少部分地独立于PCB 108。因此,焊料凸块112可以在孔114内移动并且半独立于PCB 108,由此提供了相对较大的弹力,防止可能在焊料凸块112相对于PCB 108固定的情况下发生的对互连件116的损坏。
布线层110可以包括足够柔软的聚酰亚胺薄膜,以使互连件116可以在各种弯曲度下保持固定。应当理解,柔性受微电子组件中使用的材料和它们的相对尺寸的限制。在各种示例中,PCB 108可以是柔性的,这是由于所使用的材料及其厚薄。本文中要注意,在各种示例中,PCB 108实质上是刚性的。
尽管关于芯片封装102论述了微电子组件100,但是可以利用替代的部件来实施微电子组件100。例如,根据应用到芯片封装102的原则,可以包含硅管芯来替代芯片封装102、一个或多个单个电子部件等。此外,原则是可扩展的,以使多芯片封装102或芯片封装102的组合和混合、管芯、以及分立的部件可以被实施为微电子组件100的一部分。
尽管衬底106被描绘为包括PCB 108和单独的布线层110,但是可以设想附加的构造。例如,布线层110可以嵌入在PCB 108中。作为其它示例,PCB 108可以被替换为例如柔性电路或衬底。然而,在这种示例中,在无论何种构造中,衬底106包括通常形成在衬底106中而不是特别形成在PCB108中的孔114内的焊料凸块112。
尽管互连件116被描绘为由焊盘104和焊料凸块112形成,但是应当理解,互连件116可以由通常用于形成互连件和/或电互连件的各种材料和构造中的任何材料和构造来形成。例如,焊盘104和焊料凸块112可以调换,并且焊料凸块112作为芯片封装102的部分被包括而焊盘104作为衬底106的部分被包括。可以实施插接件技术,例如通过将焊料凸块112耦合到被插入芯片封装102的插接件。
通过将焊盘104和焊料凸块112结合来形成互连件116,从而在芯片封装102与衬底106之间创建电路径。如本文中将详细公开的,可以通过使焊盘104与焊料凸块112彼此接触并且然后使焊盘104和焊料凸块112相对于彼此电气和机械耦合来形成互连件116。可以通过施加热量、施加电导聚合物粘合剂、施加压力、它们的组合、或其它适合的方式来形成互连件116。
图2A-2C示出了通过施加热量来形成和分离微电子组件100。图2A和2B总体上涉及微电子组件100的形成。如图2C中所示出的,已经形成的微电子组件100被分成单独的芯片封装102和衬底106。
在图2A中,芯片封装102与衬底106对齐并且与衬底106接触。箭头200示出了芯片封装102与衬底106的相对移动。芯片封装102和衬底106的适当定位使相对的焊盘104与凸块112对齐。
在图2B中,向焊盘104和凸块112施加局部热量,例如将凸块112点焊到焊盘104。在所示出的示例中,通过使用热冲压焊盘和/或柱202来施加局部热量。热冲压202位于与凸块112相对于布线层110的相对的位置,并且热能从布线层110传导到凸块112,在达到相关联的材料的熔点时,凸块112可以熔化、流动并且最终建立与焊盘104的电气和机械连接。在替代的示例中,可以从各种适合的方向和方位中的任何方向和方位向微电子组件100施加局部热量,例如从微电子组件的一侧施加局部热量。
应当理解,热量的施加并非必须是局部的。在示例中,通常通过例如在烤箱中、施加红外能量、以及其它适合的技术来加热微电子组件100或微电子组件100的一部分。
如所示出的,在将芯片封装102与衬底106结合期间,支撑板204可以任选地提供附加的刚性。如果微电子组件实质上是柔性的,则支撑板204可以具有特殊用途。可以在芯片封装102与衬底106相对于彼此黏附在一起时移除支撑板204。
在替代的示例中,通过施加机械压力来形成微电子组件100,以形成互连件116。在各种示例中,可以利用本文中所公开的焊球和焊盘来形成互连件116,或可以利用可以通过例如沿着箭头200施加机械压力来形成弹性结的替代的材料来形成互连件116。
在图2C中,可以任选地将微电子组件100分成芯片封装102和衬底106。来自热冲压202的局部热量可以用于使凸块112回流,因此可以根据箭头206所指示的相对移动来分开芯片封装102与衬底106。可以任选地与局部热量一起施加吸力,以在凸块112回流时去除焊料凸块112。
图3是微电子组件100的与图1所呈现的视图相比更窄的视图。具体而言,图3示出了局部热量对PCB 108的影响。如所示出的,已经将局部热量施加到微电子组件100并且将焊盘104与凸块112结合以形成互连件116。因此布线层110电耦合到嵌入在电介质118中的管芯。
PCB 108被示出为包括由于加热的影响而被化学和/或机械改型(modified)的区域300和未被加热的影响改型的未改型区域302。尽管图3示出了区域300与302之间的清晰轮廓,但是要认识并理解,在实际实施方式中,在区域300与302之间可能存在梯度,并且可以通过加热到比其它部分更高或更低的温度来使PCB 108的那部分改型。
改型区域300和未改型区域302可能源于施加到微电子组件的局部热量。具体而言,由于实质上向焊盘104和凸块112施加局部热量,PCB 108的部分可以接收足以使PCB 108熔化或另外改变其化学或机械状态(即,改型区域300)的热量。PCB 108的其它部分(即,未改型区域302)不会接收足以使PCB材料的化学或机械性质发生易于检测的变化的热量。这可以与整体加热相对照,在整体加热中,通过整体施加热量,可以均匀地或实质上均匀地使PCB 108化学或机械改型。通过局部施加热量,相对于整体加热的影响,可以减小PCB的化学和/或机械性质的改变。
应当理解,加热越局部化,越倾向于产生更小的改型区域300。因此,在施加特别窄的局部热量的各种示例中,PCB 108可以根本不包括改型区域300,即PCB 108不具有由热量的施加而产生的可辨别的化学或机械改变。在各种示例中,取决于施加的局部热量的性质,例如单位时间内传输的热量和热量聚集的程度,改型区域300可以更大或更小。
图4是示例性实施例中的微电子组件400的简要截面图。微电子组件400包含微电子组件100的许多部件。然而,取代通过施加热量或压力来形成,微电子组件在互连件408的第一部分404与第二部分406之间包括导电粘合剂402。在各种示例中,导电粘合剂402是导电聚合物。通过利用互连件408的部分404、406之间的粘合剂402挤压部分404、406直到在互连件408中形成弹性结来形成微电子组件。
如所示出的,硅管芯410未被封装在所示出的电介质中。然而,可以任选地添加电介质,其封装管芯410、以及任选地互连件408和衬底412中的一些或全部。衬底412可以包括与衬底106相同或实质上相同的部件,包括PCB 108和布线层110。
图5是处于弯曲状况下的微电子组件100的简要截面图。应当理解,处于弯曲状况下的微电子组件100的说明同样适用于微电子组件400以及其它微电子组件。
微电子组件100处于如图1中所示的松弛状况下的情况被描绘为通常具有九十度角,处于弯曲状况下的微电子组件100示出互连件116相对于PCB 108处于非90度角。如所示出的,互连件116通常可以在PCB 108中的孔114内弯曲而保持电子部件102与布线层110之间的电气和机械连接。
图6是用于制作微电子组件的流程图。流程图可以用于制作微电子组件100或任何其它适合的微电子组件。
在步骤600处,相对于衬底设置电子部件,衬底包括形成孔的电路板、布线层、和至少部分地位于孔内的第一互连件部分。在示例中,设置电子部件在第一互连件部分与电路板之间产生了间隙。在示例中,相对于衬底设置电子部件包括相对于第一互连件部分和第二互连件部分设置粘合剂。在示例中,粘合剂是导电性粘合剂。在示例中,电子部件是电子芯片、硅管芯、和分立的电子部件的至少其中之一。在示例中,第一互连件部分是焊料凸块并且第二互连件部分是焊盘。
在步骤602处,电子部件的第一互连件部分相对于第二互连件部分进行耦合,以在电子部件与衬底之间形成互连件。在示例中,耦合第一互连件部分包括创建电路板的改型区域和电路板的未改型区域。在示例中,将第一互连件部分耦合到第二互连件部分包括向第一互连件部分和第二互连件部分施加热量并向电路板的部分施加热量,其中改型区域指示向电路板施加热量的区域并且未改型区域指示缺少向电路板施加热量的区域。在示例中,将第一互连件部分耦合到第二互连件部分包括利用粘合剂将第一互连件部分至少部分地相对于第二互连件部分固定。在示例中,相对于第二互连件部分耦合第一互连件部分包括在第一互连件部分与第二互连件部分之间施加压力。
在步骤604处,相对于电路板使互连件弯曲。
在步骤606处,使布线层弯曲。
包括了使用如本公开中所描述的电子组件的电子设备的示例以示出所公开的主题内容的较高水平的设备应用的示例。图7是包含诸如微电子组件100、400或本文中的示例所描述的其它微电子组件之类的至少一个微电子组件的电子设备700的框图。电子设备700仅是本发明的实施例可以使用的电子系统的一个示例。电子设备700的示例包括但不限于个人电脑、平板电脑、移动电话、个人数字助理、MP3或其它数字音乐播放器、可穿戴设备、物联网(IOTS)设备等。在该示例中,电子设备700包括数据处理系统,数据处理系统包括耦合系统的各种部件的系统总线702。系统总线702提供电子设备700的各种部件中间的通信链接并且系统总线702可以被实施为单个总线、总线的组合或以其它任何适合的方式来实施。
将电子组件710耦合到系统总线702。电子组件710可以包括任何电路或电路的组合。在一个实施例中,电子组件710包括可以是任何形式的处理器712。如本文中所使用的,“处理器”表示任何形式的计算电路,例如但不限于微处理器、微控制器、复杂指令集计算(CISC)微处理器、精简指令集计算(RISC)微处理器、超长指令字(VLIW)微处理器、图形处理器、数字信号处理器(DSP)、多核处理器、或任何其它形式的处理器或处理电路。
电子组件710中可以包括的其它形式的电路是定制电路、特殊应用集成电路(ASIC)等,例如在诸如移动电话、寻呼机、个人数字助理、便携式电脑、双向无线电设备、以及类似的电子系统之类的无线设备中使用的一个或多个电路(例如通信电路714)。IC可以实现任何其它形式的功能。
电子设备700还可以包括外部存储器720,其可以包括适合于特殊应用的一个或多个存储器元件,例如随机存取存储器(RAM)形式的主存储器722、一个或多个硬盘驱动器724、和/或处理诸如光盘(CD)、数字化视频光盘(DVD)等的可移动介质726的一个或多个驱动器。
电子设备700还包括显示设备716、一个或多个扬声器718、以及键盘和/或控制器730,键盘和/或控制器730可以包括鼠标、轨迹球、触摸屏、语音识别设备、或允许系统用户将信息输入到电子设备700中并且接收来自电子设备700的信息的任何其它设备。
附加示例
示例1可以包括主题内容(例如装置、方法、用于实现动作的模块),其可以包括衬底和电子部件,其中衬底包括包含孔的电路板、布线层、和至少部分地设置在孔内的第一互连件部分,电子部件包括第二互连件部分,第二互连件部分耦合到第一互连件部分,以在电子部件与布线层之间形成互连件。
示例2可以包括示例1的主题内容,还包括:第一互连件部分与电路板之间具有间隙。
示例3可以包括示例1和2中的任何一个或多个的主题内容,还包括:互连件被配置为相对于电路板弯曲。
示例4可以包括示例1-3中的任何一个或多个的主题内容,还包括:布线层实质上为柔性。
示例5可以包括示例1-4中的任何一个或多个的主题内容,还包括:电路板包括改型区域和未改型区域。
示例6可以包括示例1-5中的任何一个或多个的主题内容,还包括:改型区域指示在形成电路板时向互连件施加热量的区域并且未改型区域指示缺少向电路板施加热量的区域。
示例7可以包括示例1-6中的任何一个或多个的主题内容,还包括相对于第一和第二互连件部分设置的粘合剂,粘合剂至少部分地将第一互连件部分相对于第二互连件部分固定。
示例8可以包括示例1-7中的任何一个或多个的主题内容,还包括:粘合剂是导电性粘合剂。
示例9可以包括示例1-8中的任何一个或多个的主题内容,还包括:第一与第二互连件部分之间的结是压力结。
示例10可以包括示例1-9中的任何一个或多个的题内容,还包括:电子部件是电子芯片、硅管芯、和分立的电子部件的至少其中之一。
示例11可以包括示例1-10中的任何一个或多个的主题内容,还包括:第一互连件部分是焊料凸块并且第二互连件部分是焊盘。
示例12可以包括主题内容(例如装置、方法、用于实现动作的模块),其可以包括:相对于衬底设置电子部件,衬底包括形成孔的电路板、布线层、和至少部分地设置在孔内的第一互连件部分;以及相对于电子部件的第二互连件部分而电气和机械地耦合第一互连件部分,以在电子部件与衬底之间形成互连件。
示例13可以包括示例12的主题内容,还包括:电子部件在第一互连件部分与电路板之间产生间隙。
示例14可以包括示例12和13中的任何一个或多个的主题内容,还包括:相对于电路板来弯曲互连件。
示例15可以包括示例12-14中的任何一个或多个的主题内容,还包括:弯曲布线层。
示例16可以包括示例12-15中的任何一个或多个的主题内容,还包括:耦合第一互连件部分包括创建电路板的改型区域和电路板的未改型区域。
示例17可以包括示例12-16中的任何一个或多个的主题内容,还包括:将第一互连件部分耦合到第二互连件部分包括向第一互连件部分和第二互连件部分施加热量并且向电路板的一部分施加热量,其中改型区域指示向电路板施加热量的区域并且未改型区域指示缺少向电路板施加热量的区域。
示例18可以包括示例12-17中的任何一个或多个的主题内容,还包括:相对于衬底设置电子部件包括相对于第一互连件部分和第二互连件部分设置粘合剂,并且其中将第一互连件部分耦合到第二互连件部分包括利用粘合剂将第一互连件部分至少部分地相对于第二互连件部分固定。
示例19可以包括示例12-18中的任何一个或多个的主题内容,还包括:粘合剂是导电性粘合剂。
示例20可以包括示例12-19中的任何一个或多个的主题内容,还包括:将第一互连件部分相对于第二互连件部分固定包括在第一互连件部分与第二互连件部分之间施加压力。
示例21可以包括示例12-20中的任何一个或多个的主题内容,还包括:电子部件是电子芯片、硅管芯、以及分立的电子部件的至少其中之一。
示例22可以包括示例12-21中的任何一个或多个的主题内容,还包括:第一互连件部分是焊料凸块并且第二互连件部分是焊盘。
这些非限制性示例中的每一个都可以独立实践,或可以与其它示例中的一个或多个以任何互换或组合的形式进行组合。
上述具体实施方式包括对附图的参考,附图形成了具体实施方式的一部分。附图通过说明的方式示出可以实践本发明的具体实施例。这些实施例也被称为“示例”。这种示例可以包括除所示出或描述的元件之外的元件。然而,本发明人还考虑了仅提供所示出或描述的那些元件的示例。此外,本发明人还考虑了使用所示出或描述的那些部件(或它们的一个或多个方面)相对于特定示例(或它们的一个或多个方面)或相对于本文中所示出或描述的其它示例(或它们的一个或多个方面)的任何组合或互换的示例。
在本文件中,使用了专利文件中通用的术语“一”来包括一个或多于一个,而不受“至少一个”或“一个或多个”的任何其它实例或使用的影响。在本文件中,术语“或”用于指非排他性的或,以使“A或B”包括“A但没有B”、“B但没有A”以及“A和B”,除非另外指示。在本文件中,术语“包括”和“其中”用作相应的术语“包含”和“其中”的通俗英语等同物。同样,在下面的权利要求中,术语“包括”和“包含”是开放式的,即,在权利要求中包括除了在这些术语之后所列出的元件之外的元件的系统、设备、物品、成分、配方或工艺仍被视为落在权利要求的范围内。此外,在下面的权利要求中,术语“第一”、“第二”和“第三”等仅用作标记,并且不是要对它们的对象强加数值要求。
上述描述旨在进行说明,而不是限制。例如,上述示例(或它们的一个或多个方面)可以与彼此组合使用。例如本领域普通技术人员在回顾了上述描述之后可以使用其它实施例。依照37 C.F.R.§1.72(b)提供了摘要,以使读者能够快速明确本技术公开的实质。在理解摘要并非用来解释或限制权利要求的范围或含义的基础上提交摘要。同样,在上述具体实施方式中,各种特征可以组合在一起以简化本公开内容。这应当被解释为意指未要求保护的公开的特征对于任何权利要求都是必要的。此外,发明性主题内容存在于特定公开实施例的部分特征。因此,下面的权利要求由此并入到具体实施方式中,并且每个权利要求依靠自身作为单独的实施例,并且考虑到这种实施例可以以各种组合或互换的形式而彼此进行组合。应当参考所附权利要求、以及为这些权利要求赋予权利的等同物的全部范围来确定本发明的范围。
Claims (22)
1.一种微电子组件,包括:
衬底,所述衬底包括:
包括孔的电路板;
布线层;以及
至少部分地设置在所述孔内的第一互连件部分;以及
电子部件,其包括耦合到所述第一互连件部分的第二互连件部分,以在所述电子部件与所述布线层之间形成互连件。
2.根据权利要求1所述的微电子组件,所述第一互连件部分与所述电路板之间具有间隙。
3.根据权利要求1和2中的任一项所述的微电子组件,其中,所述互连件被配置为相对于所述电路板弯曲。
4.根据权利要求1和2中的任一项所述的微电子组件,其中,所述布线层实质上是柔性的。
5.根据权利要求1和2中的任一项所述的微电子组件,其中,所述电路板包括改型区域和未改型区域。
6.根据权利要求5所述的微电子组件,其中,所述改型区域指示在形成所述互连件时向所述电路板施加热量的区域,并且所述未改型区域指示缺少向所述电路板施加的热量的区域。
7.根据权利要求1和2中的任一项所述的微电子组件,还包括相对于所述第一互连件部分和所述第二互连件部分设置的粘合剂,所述粘合剂将所述第一互连件部分相对于所述第二互连件部分至少部分地固定。
8.根据权利要求7所述的微电子组件,其中,所述粘合剂是导电性粘合剂。
9.根据权利要求1和2中的任一项所述的微电子组件,其中,所述第一互连件部分与所述第二互连件部分之间的结是压力结。
10.根据权利要求1和2中的任一项所述的微电子组件,其中,所述电子部件是电子芯片、硅管芯、以及分立的电子部件的至少其中之一。
11.根据权利要求1和2中的任一项所述的微电子组件,其中,所述第一互连件部分是焊料凸块,并且所述第二互连件部分是焊盘。
12.一种用于制作微电子组件的方法,包括:
相对于衬底设置电子部件,所述衬底包括形成孔的电路板、布线层、和至少部分地设置在所述孔内的第一互连件部分;以及
相对于所述电子部件的第二互连件部分来电气和机械地耦合所述第一互连件部分,以在所述电子部件与所述衬底之间形成互连件。
13.根据权利要求12所述的方法,其中,设置所述电子部件在所述第一互连件部分与所述电路板之间产生了间隙。
14.根据权利要求12和13中的任一项所述的方法,还包括:相对于所述电路板来弯曲所述互连件。
15.根据权利要求12和13中的任一项所述的方法,还包括:弯曲所述布线层。
16.根据权利要求12和13中的任一项所述的方法,其中,耦合所述第一互连件部分包括创建所述电路板的改型区域和所述电路板的未改型区域。
17.根据权利要求16所述的方法,其中,将所述第一互连件部分耦合到所述第二互连件部分包括:向所述第一互连件部分和所述第二互连件部分施加热量并且向所述电路板的一部分施加热量,其中,所述改型区域指示向所述电路板施加热量的区域并且所述未改型区域指示缺少向所述电路板施加的热量的区域。
18.根据权利要求12和13中的任一项所述的方法,其中,相对于所述衬底设置所述电子部件包括:相对于所述第一互连件部分和所述第二互连件部分设置粘合剂,并且其中,将所述第一互连件部分耦合到所述第二互连件部分包括:利用所述粘合剂将所述第一互连件部分至少部分地相对于所述第二互连件部分固定。
19.根据权利要求18所述的方法,其中,所述粘合剂是导电性粘合剂。
20.根据权利要求12和13中的任一项所述的方法,其中,相对于所述第二互连件部分来耦合所述第一互连件部分包括:在所述第一互连件部分与所述第二互连件部分之间施加压力。
21.根据权利要求12和13中的任一项所述的方法,其中,所述电子部件是电子芯片、硅管芯、和分立的电子部件的至少其中之一。
22.根据权利要求12和13中的任一项所述的方法,其中,所述第一互连件部分是焊料凸块并且所述第二互连件部分是焊盘。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/141,123 | 2013-12-26 | ||
US14/141,123 US20150187681A1 (en) | 2013-12-26 | 2013-12-26 | Flexible microelectronic assembly and method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104752401A true CN104752401A (zh) | 2015-07-01 |
CN104752401B CN104752401B (zh) | 2019-07-16 |
Family
ID=53372161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410858222.7A Expired - Fee Related CN104752401B (zh) | 2013-12-26 | 2014-11-26 | 柔性微电子组件和方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20150187681A1 (zh) |
JP (2) | JP2015126229A (zh) |
CN (1) | CN104752401B (zh) |
DE (1) | DE102014117374A1 (zh) |
TW (1) | TWI559483B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200095253A (ko) * | 2019-01-31 | 2020-08-10 | 에스케이하이닉스 주식회사 | 앵커(anchor) 구조물을 포함하는 반도체 패키지 |
JP2022046358A (ja) * | 2020-09-10 | 2022-03-23 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像装置及びその製造方法、並びに電子機器 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03177034A (ja) * | 1989-12-05 | 1991-08-01 | Casio Comput Co Ltd | 電子部品の接続方法 |
US5361491A (en) * | 1989-11-06 | 1994-11-08 | Nippon Mektron, Ltd. | Process for producing an IC-mounting flexible circuit board |
JP2000124345A (ja) * | 1998-10-12 | 2000-04-28 | Hitachi Cable Ltd | 高密度配線板 |
US20030102156A1 (en) * | 2001-11-30 | 2003-06-05 | Spielberger Richard K. | Ball grid array package |
US20080006949A1 (en) * | 2006-06-19 | 2008-01-10 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
CN101814465A (zh) * | 2009-02-24 | 2010-08-25 | 富士通株式会社 | 电子元件安装结构以及电子元件安装方法 |
CN101496168B (zh) * | 2006-07-31 | 2011-06-01 | 智识投资基金27有限责任公司 | 用于半导体倒装芯片封装的衬底和过程 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02251160A (ja) * | 1989-03-24 | 1990-10-08 | Toppan Printing Co Ltd | Icチップ用キャリアフィルム |
JPH0982752A (ja) * | 1995-09-14 | 1997-03-28 | Sony Corp | 半導体装置 |
TW460927B (en) * | 1999-01-18 | 2001-10-21 | Toshiba Corp | Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device |
US6744122B1 (en) * | 1999-10-04 | 2004-06-01 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
JP3865989B2 (ja) * | 2000-01-13 | 2007-01-10 | 新光電気工業株式会社 | 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置 |
JP2001257453A (ja) * | 2000-03-09 | 2001-09-21 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及びそれらの製造方法 |
JP2002064265A (ja) * | 2000-08-18 | 2002-02-28 | Toshiba It & Control Systems Corp | Bga実装方法 |
JP2002313843A (ja) * | 2001-04-18 | 2002-10-25 | Sharp Corp | 接続装置 |
SG104293A1 (en) * | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
US20050119381A1 (en) * | 2002-03-08 | 2005-06-02 | Shigeru Tanaka | Thermosetting resin composition and laminates and circuit board substrates made by using the same |
US7557433B2 (en) * | 2004-10-25 | 2009-07-07 | Mccain Joseph H | Microelectronic device with integrated energy source |
JP4379583B2 (ja) * | 2003-12-04 | 2009-12-09 | ブラザー工業株式会社 | インクジェット記録ヘッド |
US20060202001A1 (en) * | 2005-03-08 | 2006-09-14 | International Business Machines Corporation | Enhanced heat system for bga/cga rework |
KR100712517B1 (ko) * | 2005-07-14 | 2007-04-30 | 삼성전자주식회사 | 에어 갭 구조를 갖는 반도체 소자의 인터포저 |
KR100753528B1 (ko) * | 2006-01-04 | 2007-08-30 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 이의 제조 방법 |
JP2008311584A (ja) * | 2007-06-18 | 2008-12-25 | Elpida Memory Inc | 半導体パッケージの実装構造 |
KR20120054371A (ko) * | 2010-11-19 | 2012-05-30 | 에스케이하이닉스 주식회사 | 원통형 패키지, 이를 이용한 전자장치 및 그 제조방법 |
US8674503B2 (en) * | 2011-10-05 | 2014-03-18 | Himax Technologies Limited | Circuit board, fabricating method thereof and package structure |
US9287245B2 (en) * | 2012-11-07 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contoured package-on-package joint |
-
2013
- 2013-12-26 US US14/141,123 patent/US20150187681A1/en not_active Abandoned
-
2014
- 2014-11-25 TW TW103140786A patent/TWI559483B/zh not_active IP Right Cessation
- 2014-11-26 JP JP2014238429A patent/JP2015126229A/ja active Pending
- 2014-11-26 DE DE102014117374.0A patent/DE102014117374A1/de not_active Ceased
- 2014-11-26 CN CN201410858222.7A patent/CN104752401B/zh not_active Expired - Fee Related
-
2016
- 2016-09-12 JP JP2016177889A patent/JP6342460B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5361491A (en) * | 1989-11-06 | 1994-11-08 | Nippon Mektron, Ltd. | Process for producing an IC-mounting flexible circuit board |
JPH03177034A (ja) * | 1989-12-05 | 1991-08-01 | Casio Comput Co Ltd | 電子部品の接続方法 |
JP2000124345A (ja) * | 1998-10-12 | 2000-04-28 | Hitachi Cable Ltd | 高密度配線板 |
US20030102156A1 (en) * | 2001-11-30 | 2003-06-05 | Spielberger Richard K. | Ball grid array package |
US20080006949A1 (en) * | 2006-06-19 | 2008-01-10 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
CN101496168B (zh) * | 2006-07-31 | 2011-06-01 | 智识投资基金27有限责任公司 | 用于半导体倒装芯片封装的衬底和过程 |
CN101814465A (zh) * | 2009-02-24 | 2010-08-25 | 富士通株式会社 | 电子元件安装结构以及电子元件安装方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2016219846A (ja) | 2016-12-22 |
JP6342460B2 (ja) | 2018-06-13 |
US20150187681A1 (en) | 2015-07-02 |
JP2015126229A (ja) | 2015-07-06 |
DE102014117374A1 (de) | 2015-07-02 |
CN104752401B (zh) | 2019-07-16 |
TWI559483B (zh) | 2016-11-21 |
TW201537714A (zh) | 2015-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105745752A (zh) | 基板中的嵌入式桥接结构 | |
TWI231080B (en) | Power delivery apparatus, systems, and methods | |
CN104103531A (zh) | 封装结构及其制作方法 | |
CN100428274C (zh) | 生产具有双界面的卡的方法以及这样获得的微电路卡 | |
CN102148173A (zh) | 无源组件到半导体封装体的附接 | |
TW201237441A (en) | Methods and apparatuses for testing circuit boards | |
JP2009230897A (ja) | 電子部品接合装置、電子ユニット、および電子装置 | |
CN104752401A (zh) | 柔性微电子组件和方法 | |
KR101532618B1 (ko) | 전자 부품의 제조 방법 | |
KR102190390B1 (ko) | 반도체 패키지 및 이의 제조 방법 | |
WO2010070779A1 (ja) | 異方性導電樹脂、基板接続構造及び電子機器 | |
TW595290B (en) | Electronic device having connection structure and connection method thereof | |
CN105280603B (zh) | 电子封装组件 | |
CN103855128A (zh) | 半导体装置 | |
JP2012059246A (ja) | Usb装置機構 | |
KR101320973B1 (ko) | 집적회로 소자 패키지 및 이의 제조 방법 | |
JP2009231597A (ja) | 電子装置 | |
KR101451888B1 (ko) | 메모리 카드 시스템 | |
JP2010171407A5 (zh) | ||
JP4977828B2 (ja) | 携帯型物体接続可能パッケージ | |
CN104425421A (zh) | 芯片封装及其形成方法 | |
JP3744334B2 (ja) | 表示装置およびその製造方法ならびに電子機器 | |
KR101486201B1 (ko) | 유연 집적회로 소자 및 이의 제조 방법 | |
CN101247697B (zh) | 可再使用的软性印刷电路板 | |
JP5024190B2 (ja) | Icモジュール製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190716 Termination date: 20211126 |