CN104603920B - 沟槽限定的外延生长器件层 - Google Patents

沟槽限定的外延生长器件层 Download PDF

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CN104603920B
CN104603920B CN201380045269.5A CN201380045269A CN104603920B CN 104603920 B CN104603920 B CN 104603920B CN 201380045269 A CN201380045269 A CN 201380045269A CN 104603920 B CN104603920 B CN 104603920B
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semiconductor
layer
seed
groove
hard mask
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CN104603920A (zh
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R·皮拉里塞泰
S·H·宋
N·戈埃尔
J·T·卡瓦列罗斯
S·达斯古普塔
V·H·勒
W·拉赫马迪
M·拉多萨夫列维奇
G·杜威
H·W·田
N·慕克吉
M·V·梅茨
R·S·周
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Intel Corp
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Priority to CN201710540962.XA priority Critical patent/CN107275331B/zh
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    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Abstract

提供了一种沟槽限定的选择性外延生长工艺,其中,在沟槽的限定内进行半导体器件层的外延生长。在实施例中,制作沟槽,使其包括设置在所述沟槽的底部的原来的平面半导体种子表面。可以使包围种子表面的半导体区域相对于种子表面凹陷,其中,将隔离电介质设置到所述半导体区域上,以包围所述半导体种层并形成沟槽。在形成沟槽的实施例中,可以将牺牲硬掩模鳍状物覆盖到电介质内,之后对所述电介质平面化,以暴露出所述硬掩模鳍状物,之后去除所述硬掩模鳍状物,以暴露出所述种子表面。通过选择性异质外延从所述种子表面形成半导体器件层。在实施例中,通过使隔离电介质的顶表面凹陷来从所述半导体器件层形成非平面器件。在实施例中,可以由所述半导体器件层来制作具有高载流子迁移率的非平面CMOS器件。

Description

沟槽限定的外延生长器件层
技术领域
本发明的实施例涉及半导体器件领域,更具体而言,涉及外延生长的器件层。
背景技术
可以通过多种减成工艺和加成工艺来制作晶体管和其他半导体器件。可以通过硅以外的半导体材料,例如,锗和III-V族材料形成器件层,由此得到某些益处,例如,晶体管的沟道迁移率。在晶体硅衬底充当起始材料的情况下,可以采用外延生长技术以加法方式形成晶体管沟道区,从而将这样的非硅材料集成到硅衬底上,其通常被称为异质外延。这样的外延工艺是很复杂的,其至少部分原因在于硅种子表面与外延生长半导体之间的晶格失配以及热膨胀系数(CTE)失配。
基于硅的FET器件的先驱现在已经成为了采用非平面晶体管的商业化器件,所述非平面晶体管利用从衬底表面突出的硅材料体,并采用包覆所述硅体的两个、三个乃至所有侧面的栅极电极(即,双栅晶体管、三栅晶体管、纳米线晶体管)。在栅极电极的两侧将源极区和漏极区形成到所述体内,或者将其形成为耦合至所述体的再生长部分。这样的非平面设计相对于平面硅器件设计极大地改善了沟道控制和相关电性能(例如,短信道效应、降低的源极到漏极电阻等)。
将非硅材料集成到硅衬底上将是有利的,尤其是对于非平面晶体管设计而言,通过服从于这样的拓扑结构的器件层外延生长实施这样的集成将是有利的。但是,能够担当在硅衬底之上制造异质外延器件层的任务的技术和结构是未知的。例如,高度减法的工艺可能要求在硅衬底之上进行非硅薄膜的毯式生长,随后进行蚀刻,由此勾勒处形成晶体管的非硅非平面体。对于这样的技术而言,硅种衬底具有质朴的优点,但是从晶体缺陷的角度来看这样的大面积生长是很困难的,尤其是当在外延膜存在由热膨胀或晶格失配引发的显著应力的情况下。一种替代工艺可能要求仅在要设置非硅非平面体的具有有限衬底面积的区域内进行非硅膜的外延生长。尽管这样的技术可能不受大面积生长所特有的问题,但是出现了其他问题。例如,硅种子表面可能因衬底初步处理而受到损伤和/或发生变形,所述初步处理的目的在于划定发生外延生长的区域。在执行生长衬底(硅)表面的凹陷蚀刻的位置处,可能在种子表面中产生碗状或坑状,并接下来会损害外延生长。
附图说明
将通过举例方式而非限定方式对本发明的实施例予以说明,通过在联系附图考虑的同时参考下述具体实施方式将得到对本发明的实施例的更加充分的理解,其中:
图1示出了在根据本发明的实施例的外延生长器件层的方法中的选定操作的图解的流程图;
图2A-2G示出了根据本发明的实施例的随着图1所示的方法的操作的执行而在形成沟槽限定的外延器件叠置体的衬底之上的区域的截面;
图2H是说明根据CMOS实施例的互补沟槽限定的外延器件结构的等轴视图;
图3A示出了根据本发明的实施例的沿非平面晶体管的第一维度的截面,所述晶体管采用了通过图1所示的方法生长的器件层;
图3B示出了根据本发明的实施例的沿图3A所示的非平面晶体管的第二维度的截面;
图3C示出了根据本发明的实施例的沿采用通过图1所示的方法生长的器件层的平面晶体管的第一维度的截面;
图4示出了根据本发明的实施例的移动计算装置平台的等轴视图以及移动平台所采用的微电子器件的示意图;以及
图5示出了根据本发明的一种实施方式的计算装置的功能框图。
具体实施方式
将描述采用外延生长器件层的非平面晶体管及其形成方法。在下述说明中,将阐述很多细节,但是对于本领域技术人员而言显然可以在没有这些具体细节的情况下实践本发明。在一些情况下,以方框图的形式而非详细地示出了公知的方法和器件,以避免对本发明造成混淆。在整个本说明书中对“实施例”或者“在一个实施例中”的提及是指在本发明的至少一个实施例中包含联系所述实施例描述的具体特征、结构、功能或特性。因而,在本说明书从头到尾的各处出现的短语“在实施例中”未必全都是指本发明的同一实施例。此外,可以在一个或更多实施例中通过任何适当的方式结合所述特定特征、结构、功能或特点。例如,只要是在未指出第一和第二实施例相互排斥的地方,就可以使这两个实施例相结合。
可以在文中采用词语“耦合”和“连接”连同其派生词描述部件之间的结构关系。应当理解,这些术语并非意在彼此同义。更确切地说,在具体的实施例中,可以采用“连接”表示两个或更多元件相互直接物理接触或电接触。可以采用“耦合”表示两个或更多元件存在相互的直接或者间接(其间存在其他居间元件)物理或电接触,并且/或者两个或更多元件相互协作或交互(例如,就像在因果关系当中那样)。
文中采用的词语“在……之上”、“在……之下”、“在……之间”和“在……上”是指一个材料层或部件相对于其他层或部件的相对位置。因而,例如,设置在另一层之上(上方)或者之下(下方)的一个层可以与所述的另一层直接接触,或者可以具有一个或多个居间层。此外,设置在两个层之间的一个层可以与所述的两个层直接接触,或者可以具有一个或多个居间层。相形之下,位于第二层上的第一层则与所述第二层直接接触。类似地,除非另行明确指出,否则设置在两个相邻特征之间的一个特征可以与所述相邻特征直接接触,或者可以具有一个或多个居间特征。
图1示出了在根据本发明的实施例的器件层外延生长方法101中的选定操作的图解的流程图。图2A-2G示出了根据本发明的实施例的随着图1所示的方法的操作的执行而得到的衬底之上的区域的截面。交替参考图1和图2A-2G,以提供对制造技术以及显著的生成结构特征这两者的简洁扼要的说明。
方法101大体上是一种沟槽限定的选择性外延生长工艺,其中,半导体器件层的外延生长是在沟槽的局限之内进行的。这样的沟槽限定的生长能够提供高宽比陷获(ATR)的优点,由此能够通过在沟槽的侧壁上陷获穿入位错、堆垛层错、孪晶等而增强外延层的晶体质量,在沟槽侧壁上缺陷终止,从而使得上覆的各层可以更多地免于出现缺陷,而且在隔开的沟槽内生长的相邻器件层可以按照更加独立的或隔离的方式同时生长。划定若干这样的具有至少一个相对较小的尺寸(例如,2nm-100nm)以实现最佳ATR的沟槽可以使得异质外延工艺能够在种晶体与器件层中的外延生长晶体之间具有既定量的热失配和晶格失配的情况下具有较低的缺陷密度。
本发明人还发现,沟槽限定的外延膜的质量高度依赖于生长外延层的限定沟槽的特征(例如,沟槽侧壁角度、沟槽的拐角圆化和沟槽的底部凹坑)。与对生长衬底进行凹陷蚀刻之后在受到凹陷蚀刻的半导体种子表面上执行选择性外延的沟槽形成技术形成对照的是,已经发现方法101有利地提供了良好的沟槽高宽比和侧壁角度控制,同时还保持了原来的平面未受凹陷蚀刻的外延生长种子表面,从而获得更高质量的受到更好控制的外延器件层。
参考图1,方法101开始于在操作103中接收生长衬底。一般而言,生长衬底可以由任何适于半导体器件制造的材料构成,因为文中描述的技术广泛适用于任何已知生长衬底,例如,所述生长衬底可以是但不限于硅、锗、硅锗、碳化硅、蓝宝石或III-V族化合物半导体等。图2A对示范性生长衬底给出了进一步图示。在这一实施例中,所述生长衬底包括由(单晶)晶体硅(例如,(100)硅)构成的体衬底201。将一个或多个半导体的基底层205设置到体衬底201之上,例如,所述基底层可以是但不限于假同晶的、变质的或基本晶格匹配的缓冲层和/或过渡层,这是本领域已知的。本发明的实施例在基底层205的结构和/或构成方面不受限制。如图2A所示,无论生长衬底的确切结构怎样,都有存在于操作103(图1)中接收到的生长衬底上的外延种子表面225。例如,所述种子表面225可以是具有(100)晶体取向的晶体SiGe表面,等等。
继续方法101,在操作105中,在生长基板之上毯式沉积硬掩模膜。一般而言,硬掩模膜应当由这样的材料构成,即,能够从生长衬底上将其容易地去除而不会对生长衬底造成损坏(即,可通过相对于下层生长衬底材料具有高度选择性的工艺去除),并且能够对其进行各向异性蚀刻,从而获得良好控制的侧壁角度、平滑度和CD控制。如文中别处进一步描述的,硬掩模膜的功能之一在于对下层半导体表面的将由其开始外延层生长的种子表面加以保护。硬掩模膜的另一功能在于最终界定将在其内进行外延生长的沟槽的侧壁角度。
在生长衬底表面包括除了硅以外的晶格构成(例如,SiGe合金)的一个实施例中,所述硬掩模膜包括多晶硅(p-Si)或非晶硅(a-Si)层。在另一实施例中,所述硬掩模膜包括氮化硅层。所述硬掩模膜的厚度(z高度)可以随着用以取得接下来要在硬掩模膜内形成的特征的预期高宽比(即厚度:横向临界尺寸)的技术而发生变化。用于形成硬掩模膜的沉积工艺可以是本领域已知的任何适于这些示范性材料或者任何其他适当的备选材料的工艺。图2B对示范性生长衬底给出了进一步图示。在这一实施例中,将硬掩模膜230直接沉积到基底层205上(与种子表面225直接接触)。在图示的实施例中,硬掩模膜230是单匀质层,并且这样的实施例适于下层半导体包括硅以外的元素的情况(例如,作为硅合金或者无硅半导体),以确保相对于下层半导体种子表面225的良好的选择性蚀刻。在某些这样的示范性实施例中,硬掩模膜230的厚度超过50nm,并且可以进一步超过500nm,具体取决于获得具有适当深宽比的沟槽所需的裕量。
在其他实施例中,硬掩模膜可以包括一个或多个层,以形成多层的材料叠置体。一般而言,可以将从CD控制、侧壁角度控制、边缘粗糙度等角度来看提供良好蚀刻特性的材料块体层设置在下层基底层上,即,与生长衬底的种子表面直接接触。所述硬掩模基底层可以比所述块体层薄,并且可以具有任何适于作为蚀刻停止部分的材料,从而允许所述块体层材料和/或蚀刻工艺具有更低的相对于半导体衬底的蚀刻选择性。作为一个例子,可以将薄氧化物层(例如,SiO2、GeO2、SixGe1-xOy)或者氮氧化物层(例如,SiON、GeON、SixGe1-xOyNz)设置到体硬掩模层和下方的生长衬底表面之间。例如,参考图2B,硬掩模膜230可以包括直接位于种子表面225上的氧化物层以及直接设置在所述氧化物层上的p-Si、a-Si或氮化硅层。对于这样的实施例而言,氧化物层的厚度可以从1nm左右的自然氧化物厚度到2-3nm的热生长氧化物或化学沉积氧化物(例如,通过CVD/PECVD)厚度不等,或者可以更厚。
继续方法101,在操作107中,将硬掩模膜图案化为硬掩模鳍状物。所述硬掩模鳍状物是牺牲鳍状物,其起着接下来的处理的芯柱的作用。所述鳍状物一般具有有利于限定接下来的生长的沟槽的反转图案,因此所述鳍状物的覆盖区和所述鳍状物的侧壁角度两者都是有研究价值的。可以使标准光刻图案化技术与硬掩模膜的已知各向异性干法等离子体蚀刻结合,从而将硬掩模膜图案化为牺牲硬掩模鳍状物。
图2C示出了一个示范性实施例,其中,将硬掩模膜230各向异性蚀刻为具有侧壁250的硬掩模鳍状物235,从而在硬掩模膜230的各向异性蚀刻过程中或者对于硬掩模膜230为多层的叠置体的实施例而言通过对蚀刻停止层(例如,薄CVD氧化物)的单独蚀刻暴露周围种子表面225。或者,可以将蚀刻停止层留在周围半导体表面上。当前认为,在将初始种子表面设置到具有至少2:1,优选大于4:1的高宽比的沟槽内时,ART是最成功的。在硬掩模膜230具有50-500nm的厚度的示范性实施例中,对于处于大约5和10之间的高宽比而言硬掩模鳍状物235可以具有处于2nm-100nm的范围内的横向临界尺寸(例如,沿图2C的x轴)。
在优选实施例中,硬掩模鳍状物的侧壁大致垂直于下层生长衬底的顶表面。例如,在图2C中,侧壁250具有相对于种子表面225大约90°(例如88-92°)的侧壁角θ。已经发现垂直鳍状物侧壁对于接下来界定沟槽的侧壁是有利的,如文中别处进一步所述。在替代实施例中,侧壁角θ略微正倾斜,此时硬掩模鳍状物的基底具有大于顶部部分的尺寸(即,非凹入的)。例如,在图2C中,可以使侧壁250倾斜至100-120°的侧壁角θ。
返回到图1,方法101进行至操作109,其中,按照与硬掩模鳍状物自对准的方式形成隔离。在示范性实施例中,操作109要求在硬掩模鳍状物之上沉积隔离电介质膜,之后使所述隔离电介质平面化,以暴露所述硬掩模鳍状物。在共形沉积隔离电介质的实施例中,所述电介质形成了与硬掩模鳍状物的侧壁互补的侧壁(例如,图2D中所示的侧壁250),从而将针对硬掩模鳍状物取得的蚀刻轮廓的取反转化为所述隔离电介质膜。因此,在对硬掩模鳍状物的蚀刻进行很好地控制以提供非凹入(即,正交或正倾斜的)侧壁的情况下,包围硬掩模鳍状物的共形隔离电介质能够类似地形成具有逆反图案的受到很好控制的侧壁角(即,正交的或者凹入的)。
在其他实施例中,使隔离电介质凹陷到生长衬底种子表面下方。对于这样的实施例而言,操作109中的隔离电介质的形成还包括对不受硬掩模鳍状物保护的半导体衬底进行蚀刻。如图2D所示,这一浅沟槽隔离蚀刻按照与硬掩模鳍状物235自对准的方式去除了一些生长衬底,更具体而言,去除了一些基底半导体层205(例如,缓冲)。所述的生长衬底的蚀刻可以通过任何本领域已知的适用于生长衬底材料系的技术进行。在示范性实施例中,执行对生长衬底的各向异性蚀刻,例如,等离子体蚀刻,以保持半导体种子表面侧壁245和硬掩模侧壁250之间的保真度。例如,在基底层205是SiGe合金(例如,Si0.7Ge0.3)的情况下,执行干法蚀刻,从而使蚀刻前沿的推进超越了种子表面225。在图示的示范性实施例中,使拐角圆化246凹陷到种子表面225以下,所述拐角圆化发生在将膜清除(例如,将基底层205清除)以前的定时蚀刻当中。例如,这样的生长衬底的凹陷有利地减少了通过生长衬底的顶层(例如,通过基底层205)内的通路发生的相邻器件之间的漏电流。这样的生长衬底的凹陷可以进一步实现对出现在种子表面225处的膜应力的工程设计,例如,其方式是减少种子表面225和周围基底层205之间的物理耦合(实际上是将种子表面225放置到半导体基座或台地的顶上)和/或能够将受到很好的控制的经应力工程设计的隔离电介质240(被设计为发生伸张或压缩,具体取决于实施例)设置为与种子表面侧壁245相邻。根据硬掩模鳍状物235的x-y尺寸,这样的应力可以或多或少是单轴的或双轴的。
在实施例中,操作109需要共形沉积一个或多个电介质材料层,例如,其可以是但不限于化学气相沉积(例如,CVD、PECVD)氧化物(SiO2)。在沉积一个以上的层的情况下,可以在体电介质(例如,SiO2)内沉积薄蚀刻停止电介质(例如,氮化硅)。在常规平面化技术(例如,CMP)之后,沉积电介质具有与硬掩模鳍状物的顶表面在一个平面内的顶表面,如图2D所示。
继续方法101,在操作111中,相对于隔离电介质和生长衬底有选择地去除硬掩模鳍状物,以暴露出半导体种子表面。硬掩模鳍状物、隔离电介质和生长衬底之间的材料差别促进了对于硬掩模鳍状物而言具有高度选择性的硬掩模鳍状物蚀刻,从而确保外延种子表面不受蚀刻(不凹陷)、不受损伤并因此而具有起始衬底通常具有的高平面度(例如,基本上就像在操作103中接收到的那样)。如图2E进一步所示,在沟槽260的底部暴露出原来的种子表面225,由于与硬掩模鳍状物蚀刻相关的高蚀刻选择性的原因所述沟槽的侧壁250受到了很好的控制。这一处理和所得到的结构特征与其他替代处理形成了鲜明对比,在其他处理当中将相对于周围隔离电介质或者生长衬底的其他区域对生长衬底的顶表面进行凹陷蚀刻,以形成可以在其内进行接下来的外延生长的沟槽。已经发现,这样的半导体凹陷蚀刻可能以某种对接下来对外延生长不利的方式对半导体表面造成损伤。例如,微开槽(局部化加速蚀刻)可能导致底部半导体表面产生凹坑和/或沟槽拐角圆化。但是,借助于本发明的实施例,将无需执行任何对种子表面(例如,图2E中的225)的凹陷处理,因而种子表面是未经蚀刻的半导体表面。
在基底层205为SiGe合金,隔离电介质240为SiO2的示范性实施例中,能够借助于各向同性低能蚀刻(例如,基于下游等离子体的、基于湿法化学反应的等等)以20-30:1的选择性容易地去除p-Si硬掩模材料以及氮化硅硬掩模材料。在硬掩模膜是叠置体(例如,在薄氧化物之上设置p-Si或氮化硅的体层)的其他实施例中,在操作111中去除硬掩模鳍状物可能需要第一和第二蚀刻,其中,采用高选择性(相对于生长衬底为20-30:1或更高)蚀刻去除硬掩模鳍状物的薄基底层。在实施例中,在操作111之后,其内设置着种子表面的沟槽260具有至少5:1的高宽比(z高度:x横向临界尺寸),并且所述高宽比可以是10:1或更大,其中,侧壁250基本上与种子表面225正交或者略微凹入。在沟槽260的x尺寸处于2nm和100nm之间的实施例中,沟槽260的z高度处于50nm与500nm之间。
方法101(图1)继续进行操作113,其中,在所制成的沟槽内对晶体半导体器件层或多个层进行外延生长。一般而言,在操作113中生长的器件层可以是任何本领域已知的器件层,其可以采用任何已知的用于所选材料的外延技术(例如,通过金属化学气相沉积-MOCVD、分子束外延(MBE)等)。在示范性实施例中,外延半导体层因与晶体种子表面的晶格和/或CTE失配而发生应变。对于外延生长一个以上的器件层的实施例而言,晶格和/或CTE失配还可能存在于外延器件层之间。文中采用的“外延”层是与种子表面配准的(例如,由于种子表面的结晶性的原因而具有优选晶体取向)。在种子表面具有(100)取向的某些实施例中,外延器件层还具有(100)取向。由于外延生长被局限在沟槽260内,因而半导体器件层将具有与电介质240中的侧壁250的那些侧壁互补的侧壁。即使存在成分变化的层理,所述器件层都具有基本上相对于种子表面225正交的侧壁或者略微正倾斜(例如,偏离正交10-20)的侧壁,在后一情况下侧壁250是凹入的。借助于操作113中的沟槽限定的外延生长,缺陷可能朝向与侧壁250的界面逃出(run out)。假设未对外延生长进行沟槽限定(例如,就不存在任何沟槽界面的毯式生长而言),将不存在这样的定向外逃。此外,借助于沟槽限定的外延生长,形成于种子表面之上的外延层内的晶体缺陷密度可能随着器件层内的各点与种子表面相距越远而逐步地越低。
在一个示范性实施例中,在操作113中生长的器件层包括至少一个在种子表面之上(或者直接在其上)外延生长的高迁移率沟道层。所述高迁移率层可以是在操作113中直接在生长衬底的种子表面上生长的量子阱结构(例如,两个或三个具有相异能带隙的外延层)的部分,例如,以作为适于高载流子迁移率晶体管实施例的器件层的部分。或者,如图2F所示,所述器件层可以包括若干沟道层,它们全部在沟槽260的局限之内生长,从而(例如)形成堆叠式纳米线晶体管器件。或者,图2F所示的实施例可以是不太复杂的情况,其中,就像本领域公知的更加典型的平面晶体管沟道结构那样仅形成单个沟道层。因而,图2F意在既表示平面实施例又表示堆叠式纳米线实施例,因为可以将平面实施例看作是图示的纳米线实施例的第一层。
对于基底层205是SiGe合金的一个实施例而言,在种子表面225之上有选择地生长由Ge构成的高空穴迁移率沟道层280A。尽管在一些实施例中,沟道层280A是在种子表面225上直接生长的(例如,对于平面晶体管实施例而言),但是对于图2F中所示的堆叠式纳米线实施例而言,将居间半导体层275设置(生长)到沟道层280A和种子表面225之间。居间半导体层275可以具有某种成分,其使得所述半导体层能够被相对于沟道层280A有选择地去除(或反之)。尽管所述外延器件层可以包括在沟槽260的局限内生长的任何数量的沟道层,但是对于图示的实施例而言,在沟道层280A之上生长第二沟道层280B,二者具有居间晶体层290A。在沟道层280A和280B具有相同成分的实施例中,居间层290A具有相异成分,并且可以具有与居间层275相同的成分。最后,在第二沟道层280A之上是另一外延半导体层290B,在一个实施例中,外延半导体层290B与层290A具有相同成分,更具体而言,其可以由具有高电子迁移率的材料构成,例如,与沟道层280A、280B合理地晶格匹配的已知III-V族合金(例如,任何二元、三元或四元化合物,例如但不限于InAs、InAsSb、InSb、AlGaAs、GaAs等)。这样的器件叠置体可以允许进行CMOS实现,其中,层290A和290B充当nMOS器件沟道,层280A和280B充当pMOS器件沟道。对于平面晶体管实施例而言,单个沟道层280A(或290A)将是唯一的半导体器件层,其直接设置在种子表面225上,并且相对于周围电介质240生长至与图示的纳米线叠置体相当的厚度。作为例子,图3C中示出了平面晶体管的实施方式。
在实施例中,操作113还包括平面化,以去除延伸到相邻隔离电介质以上或者超出相邻隔离电介质的任何过生长半导体。例如,图2F示出了示范性纳米线半导体器件叠置体,其顶表面基本上与周围隔离电介质240在一平面内。在这样的平面化之后,所述外延生长半导体的顶表面(图2G中的顶表面291)可以被设置为距种子表面一定距离,该距离是沟槽260(图2E)的深度的重要部分。例如,在实施例中,平面化外延器件层的顶表面可以与种子表面相距40nm-400nm,或者种子表面最小横向尺寸(例如,图2G中的x维)的三倍以上。
方法101(图1)在操作115中结束,从而完成了外延半导体内或外延半导体上的器件制作。这样的制作可以随着器件和/或器件层而变化。在某些实施例中,例如在图2F所示的非平面实施例中,操作115要求使隔离电介质顶表面241有选择地凹陷至器件层,以暴露器件层内的一个或多个半导体层的一个或多个侧壁,从而使得每一沟槽限定的外延器件叠置体成为伸到周围隔离电介质之上的非平面半导体基体。相对于隔离电介质起着限定沟槽作用时的厚度对凹陷隔离电介质减薄,但是所保留的厚度可以足够用于未被用作种子表面的生长衬底部分凹陷至种子表面以下(例如,在图1的操作109当中)的地方的电器件隔离。可以采用任何本领域已知的适于使隔离电介质材料凹陷的蚀刻技术。例如,可以采用定时湿法或干法SiO2蚀刻,或者在将蚀刻停止层结合到多层隔离电介质内的实施例中,可以使隔离凹陷蚀刻在蚀刻停止层上停止,所述停止层要么接下来被去除,要么作为矫作部分(artifact)留在隔离区内。在图2G所示的实施例中,在隔离电介质凹陷过程完成时,沟道层280A和280B两者均在隔离顶表面241以上暴露出。
图2H是说明根据CMOS实施例的沟槽限定的外延器件叠置体的等轴视图。图2H表示一种可以用于由沟槽限定的外延器件层形成具有互补载流子类型的高迁移率晶体管的技术。图2H中的CMOS实现包括pMOS纳米线结构301和nMOS纳米线结构302。而且,可以类似地形成包括平面pMOS晶体管结构和平面nMOS晶体管结构的类似CMOS结构(例如,仅采用相应的种子表面之上的单沟道层生长)。
在一个纳米线实施例中,pMOS纳米线结构251是由图2G中所示的器件叠置体演化而来的。如图所示,可以包围器件叠置体的中央区域形成牺牲沟道掩模芯轴结构215(例如,在y维度的中央),之后在通过掩模芯柱结构215保护所述中央区域的同时蚀刻掉对于所述晶体管载流子类型而言要牺牲掉的所述器件层的交替的各层(例如,对于pMOS结构251而言的层275、290A、290B或者对于nMOS结构252而言的层280A、290B)。之后,可以将掺杂半导体沉积(或生长)到沟道层280A和280B的暴露端213、223之上,可以在所述过程中的某一点上对所述暴露端重掺杂。或者,可以将末端213、223一起替换(重新生长)。之后,可以去除沟道掩模芯柱结构215(未对此给出图示),并且借助于非牺牲间隔体电介质216A、216B、226A、226B和/或源极/漏极半导体和/或锚固器件层的接触金属,执行第二次半导体蚀刻(例如,蚀刻掉pMOS结构251内的层275、290A、290B以及nMOS结构252中的层280A、280B),以暴露所述互补结构的沟道层。之后,采用可以是但不限于原子层沉积(ALD)的常规技术在暴露的沟道层之上形成包括共形栅极电介质层和栅极电极层的非牺牲栅极叠置体。在示范性实施例中,共形沉积第一栅极电介质和第二栅极电介质,从而对器件层之间的任何孔隙进行回填,继而完全包覆在源极和漏极之间延伸的半导体沟道的各个表面。
值得注意的是,尽管图2H中的图示示出了处于同一状态的pMOS器件301和nMOS器件302,但是在一个结构的顺序处理先于另一结构的顺序处理的情况下(例如,可能多次执行上文所述的处理,所述处理将在衬底的各单独区域内择一地保留半导体层290A、290B与层280A、280B以作为互补沟道层)这样的状态可以不是同时出现的。通过这种方式,基于同一外延器件叠置体的跨越衬底界定的多个沟槽既可以充当pMOS高迁移率器件的基础,又可以充当nMOS高迁移率器件的基础。在一个这样的实施例中,至少在沟道区内,所述pMOS纳米线层280A、280B中的每者具有相同的IV族半导体材料(例如,Ge)。类似地,在沟道区内,nMOS纳米线层290A、290B中的每者具有相同的III族-V半导体材料(例如,GaAs)。在备选实施例中,pMOS纳米线层280A、280B中的每者具有相同的IV族半导体材料(例如,Ge),与此同时nMOS纳米线层290A、290B中的每者也具有相同的IV族半导体材料(例如,Si)。
在单沟槽限定的异质外延叠置体中,一个晶体管类型的沟道层充当与另一晶体管类型的沟道层相邻的牺牲层,就所述的单沟槽限定的异质外延叠置体而言,第一半导体沟道将具有被设置为与种子表面相距第一距离的顶表面,具有互补导电类型的第二半导体沟道将具有被设置为与种子表面相距第二距离(比第一距离大或小)的顶表面。
图3A示出了根据本发明的实施例的沿非平面pMOS晶体管301的第一(x)维度的截面,所述晶体管采用了通过图1所示的实施例生长的沟槽限定的器件层。图3B示出了根据本发明的实施例的沿非平面pMOS晶体管301的第二(y)维度的截面。在示范性实施例中,PMOS晶体管301是在操作115(图1)当中由pMOS结构251演化而来的(图2H)。图3C示出了根据本发明的实施例的沿采用通过图1所示的方法生长的器件层的平面晶体管的第一维度的截面。
如图3A所示,由于沟槽限定的外延生长的原因,沟道层280A、280B的中央(通过中心线CL表示)贯穿设置在隔离电介质240之间的种子表面225的中央延伸。除了重合的中央之外,种子表面225的平面性也体现了方法101。进一步如图3A所示,使种子表面225相对于隔离电介质顶表面241凹陷,同时使底部隔离表面242在种子表面225的高度以下的高度上与下层半导体相接。如图3B所示,种子表面225沿y维度具有长度L1,其由相邻隔离电介质240界定。还是沿该轴,使种子表面225与在半导体源极和漏极112A、112B之间延伸的界定沟道层280A、280B的器件层的中央对准。由于在非凹陷的未经蚀刻的生长衬底表面上执行的沟槽限定生长的原因,种子表面225也沿其整个长度L1呈平面。假设执行了无阻停半导体凹陷蚀刻在基底层205中将不存在这样的平面性(例如,相反将接近隔离电介质240的界面出现拐角圆化)。如图3A和3B两图所示,采用栅极电介质310A、310B、310C(例如,310A包围沟道层280A,310B包围沟道层280B)和栅极电极材料315对器件叠置体内因对牺牲半导体层进行蚀刻而形成的凹陷进行回填。进一步地,沉积与源极和漏极112A、112B接触的接触金属化335A、345A。
如图3C所示,对于平面晶体管实施例而言,单个沟道层280A(或290A)将是唯一的半导体器件层,其直接设置在种子表面225上,并且相对于周围电介质240生长至跨越隔离电介质240和沟道层28A获得平面表面的厚度。
图4示出了根据本发明的实施例的移动计算装置平台700的等轴视图以及所述移动平台采用的微电子器件710的示意图721。移动计算平台700可以是任何被配置为实现电子数据显示、电子数据处理和无线电子数据传输中的每者的便携式装置。例如,移动计算平台700可以是平板电脑、智能电话、膝上型计算机等当中的任何一种,其包括显示屏705、芯片级(SoC)或者封装级集成微电子器件710和电池713,所述显示屏在示范性实施例中是触摸屏(例如,电容式的、电感式的、电阻式的等等)。
通过放大图721对集成器件710给出了进一步图示。在示范性实施例中,器件710包括至少一个存储器和至少一个处理器芯片(例如,多芯微处理器和/或图形处理器芯730、731)。“处理器”一词可以指任何对来自寄存器和/或存储器的电子数据进行处理从而将该电子数据变换为其他可以存储在寄存器和/或存储器内的其他电子数据的装置或装置的部分在实施例中,处理器芯片或存储器内的一个或多个晶体管包括在采用隔离电介质形成了包围平面种层的周界的情况下设置在所述种层之上的异质外延沟道层,文中别处对此给出了更加详细的描述(例如,图3A、3B),其中,所述种层集成在器件710内。器件710还连同功率管理集成电路(PMIC)715、包括宽带RF(无线)发射器和/或接收器(例如,包括数字基带,并且模拟前端模块还包括处于发射通路上的功率放大器和处于接收通路上的低噪声放大器)的RF(无线)集成电路(RFIC)725以及其控制器711耦合至板、衬底或插入机构500。在功能上,PMIC 715执行电池功率调节、DC到DC转换等,因而具有耦合至电池713的输入,并且具有向所有其他功能模块提供电流源的输出。如图进一步所示,在示范性实施例中,RFIC 725具有耦合至天线的输出,从而有条件实施很多无线标准或协议中的任何标准或协议,其包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、它们的衍生产物以及任何被命名为3G、4G、5G或更高代的其他无线协议。在实现当中,这些模块中的每者可以集成到作为SoC的单个芯片上,集成到耦合至封装器件710的封装衬底的单独IC上或者处于板层级上。
图5是根据本发明的一个实施例的计算装置1000的功能框图。可以在(例如)移动计算平台700内发现计算装置1000,所述计算装置1000还包括具有若干部件的板1002,例如所述部件可以是但不限于处理器1004(例如,应用处理器)和至少一个通信芯片1006。在实施例中,至少所述处理器1004与处理器芯片或存储器中的一个或多个晶体管集成(例如,在芯片上),所述处理器1004包括根据文中别处描述的实施例在采用隔离电介质形成包围平面种层的周界的情况下设置在所述平面种层之上的异质外延沟道层。将处理器1004物理和电耦合至板1002。处理器1004包括封装在处理器1004内的集成电路裸片。
在一些实施方式中,还将至少一个通信芯片1006物理和电耦合至板1002。在其他实施方式中,通信芯片1006是处理器1004的部分。根据其应用,计算装置1000可以包括其他部件,这些部件可以物理和电耦合至母板1002,也可以不存在这样的耦合。这些其他部件包括但不限于易失性存储器(例如,DRAM)、具有闪速存储器等形式的非易失性存储器(例如,RAM或ROM)、图形处理器、数字信号处理器、密码处理器、芯片组、天线、触摸屏显示器、触摸屏控制器、电池、音频编码译码器、视频编译码器、功率放大器、全球定位系统(GPS)装置、罗盘、加速度计、陀螺仪、扬声器、照相机和大容量存储装置(例如,硬盘驱动器、固态驱动器(SSD)、紧致磁盘(CD)、数字通用盘(DVD)等)。
通信芯片1006的至少其中之一能够实现无线通信,从而进行往返于计算装置1000的数据传输。“无线”一词及其派生词可以用来描述利用调制电磁辐射通过非固态介质进行数据通信的电路、装置、系统、方法、技术、通信信道等。该词并非暗示相关装置不含有任何布线,但是在一些实施例中它们可能不含有。通信芯片1006可以实现很多无线标准或协议中的任何标准或协议,其包括但不限于文中别处描述的那些标准或协议。计算装置1000可以包括多个通信芯片1006。例如,第一通信芯片1006可以专用于较短范围的无线通信,例如,Wi-Fi和蓝牙,第二通信芯片1006可以专用于较长范围的无线通信,例如,GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
因而,描述了沟槽限定的异质外延器件叠置体及其制造的实施例。在实施例中,提供了一种在衬底上形成异质外延器件层的方法,所述方法包括:接收具有半导体种子表面的衬底;在所述种子表面之上形成硬掩模鳍状物;形成与所述硬掩模鳍状物相邻的隔离区;通过相对于所述隔离区有选择地去除硬掩模鳍状物而形成以所述种子表面作为其底部的沟槽;以及在所述沟槽内外延生长半导体层,所述半导体层具有所述半导体种子表面的晶格失配或CTE失配的至少其中之一。在实施例中,形成硬掩模鳍状物还包括在所述种子表面之上沉积多晶硅层或氮化硅层;以及采用各向异性蚀刻对所述多晶硅层或氮化硅层构图。在实施例中,形成硬掩模鳍状物还包括直接在种子表面上沉积蚀刻停止层,并在氧化物层之上沉积多晶硅层或氮化硅层。在实施例中,所述各向异性蚀刻形成了垂直侧壁或者略微正倾斜的侧壁,并且其中,所述硬掩模鳍状物具有至少5:1的高宽比。在实施例中,形成所述隔离区还包括:在硬掩模鳍状物之上沉积隔离电介质层,以及使所述隔离电介质层平面化以暴露所述硬掩模鳍状物的顶表面。在实施例中,形成所述隔离区还包括:蚀刻与硬掩模鳍状物相邻的衬底部分,从而使不受硬掩模鳍状物保护的衬底部分相对于所述种子表面凹陷;以及在所述凹陷衬底表面之上沉积隔离电介质层。在实施例中,所述方法还包括使外延器件层的顶表面与所述隔离区平面化;以及使所述隔离区相对于所述外延器件层的顶表面凹陷,以形成包括所述外延器件层的非平面半导体基体,其中,所述隔离区与所述非平面半导体基体相邻。在实施例中,所述方法还包括至少在所述外延器件层的相对的两侧之上形成栅极电介质和栅极电极,以控制耦合至器件层的源极区和漏极区之间的载流子传导。在实施例中,所述外延器件层包括Ge或III-V族二元、三元或四元半导体合金,并且所述栅极电介质和栅极电极的形成还包括蚀刻设置在种子表面和外延器件层之间的牺牲半导体层,以暴露出外延器件层的底表面;以及在所述底表面之上回填栅极电介质和栅极电极。
在实施例中,提供了一种设置在硅衬底之上的非平面场效应晶体管(FET),所述非平面FET包括:源极区和漏极区,其间设置有处于平面半导体种层之上的非硅半导体沟道,所述半导体种子表面具有非硅半导体沟道的成分以外的成分,所述平面半导体种子表面是受到隔离电介质包围的半导体平台的顶表面;设置在所述非硅半导体沟道之上的栅极电介质层和栅极电极层。在实施例中,所述非硅半导体沟道为Ge或III-V族二元、三元或四元化合物半导体合金,并且其中,所述沟道的中央与所述平面半导体种子表面的中央对准。在实施例中,隔离电介质的底表面与凹陷到所述种子表面下方的半导体表面接触。在实施例中,使种子表面凹陷到隔离电介质的顶表面下方。在实施例中,所述非硅半导体沟道是半导体叠置体的一个层,其顶表面被设置为与所述种子表面相距至少是所述种子表面的最小横向尺寸的三倍的距离。
在实施例中,提供了一种设置在硅衬底之上的CMOS器件,所述CMOS器件包括:pMOS器件,其具有:第一源极区和第一逻辑区,它们之间设置有位于第一平面半导体顶表面之上的Ge半导体沟道,所述第一平面半导体种子表面具有所述沟道的成分以外的成分,所述第一平面半导体种子表面是受到隔离电介质包围的第一半导体平台的顶表面;以及设置在所述Ge半导体沟道之上的第一栅极电介质层和第一栅极电极层;以及nMOS器件,其具有:第二源极区和第二漏极区,它们之间设置有位于第二平面半导体种子表面之上的III-V族半导体沟道,所述第二平面半导体种子表面具有除了所述沟道的成分以外的成分,所述第二平面半导体种子表面是受到隔离电介质包围的第二半导体平台的顶表面;以及设置在所述III-V族半导体沟道之上的第二栅极电介质层和第二栅极电极层。在实施例中,所述Ge半导体沟道具有被设置为与所述种子表面相距第一距离的顶表面,所述III-V族半导体沟道具有被设置为与所述种子表面相距不同于所述第一距离的第二距离的顶表面。在实施例中,使Ge半导体沟道的中央与第一平面半导体种子表面的中央对准,并且其中,使III-V族半导体沟道的中央与第二平面半导体种子表面的中央对准。在实施例中,使所述第一种子和第二种子表面凹陷到隔离电介质的顶表面下方。在实施例中,使第一栅极电介质和第二栅极电介质完全包覆在源极和漏极之间延伸的半导体沟道的表面。
在实施例中,一种移动计算平台包括含有文中描述的非平面FET或者文中描述的CMOS器件的集成电路、显示屏以及无线收发器。
因此,本发明的一个或多个实施例总体上涉及沟槽限定的异质外延器件叠置体。应当理解,上述说明意在进行举例说明而非构成限制。例如,尽管附图中的流程图示出了通过本发明的某些实施例执行的操作的具体顺序,但是应当理解不需要这样的顺序(例如,替代实施例可以按照不同的顺序执行操作,结合某些操作,叠加某些操作等)。此外,对于本领域技术人员而言在阅读并理解了上述说明的情况下很多其他实施例将显而易见。尽管已经参考具体示范性实施例描述了本发明,但是应当认识到本发明不限于文中描述的实施例,而是可以在所附权利要求的精神和范围内以修改和变更来实践本发明。因此,应当参考所附权利要求以及该权利要求的等同方案的全范围来确定本发明的范围。

Claims (13)

1.一种在衬底上形成异质外延器件层的方法,所述方法包括:
接收具有半导体种子表面的衬底;
在所述种子表面之上形成硬掩模鳍状物;
形成与所述硬掩模鳍状物相邻的隔离区;
形成沟槽,其中,通过去除所述硬掩模鳍状物而使所述种子表面位于所述沟槽的底部;以及
在所述沟槽内外延生长半导体器件层,所述器件层具有与所述半导体种子表面的晶格常数失配或CTE失配的至少其中之一。
2.根据权利要求1所述的方法,其中,形成所述硬掩模鳍状物还包括:在所述种子表面之上沉积多晶硅层或氮化硅层;以及采用各向异性蚀刻来对所述多晶硅层或氮化硅层进行构图。
3.根据权利要求2所述的方法,其中,形成所述硬掩模鳍状物还包括直接在所述种子表面上沉积蚀刻停止层,以及在氧化物层之上沉积所述多晶硅层或所述氮化硅层。
4.根据权利要求1所述的方法,其中,形成所述隔离区还包括:
蚀刻所述衬底的与所述硬掩模鳍状物相邻的部分,从而使不受所述硬掩模鳍状物保护的所述衬底部分相对于所述种子表面凹陷;以及
在凹陷的衬底表面之上沉积隔离电介质层。
5.根据权利要求1所述的方法,还包括:
使所述器件层的顶表面与所述隔离区平面化;以及
使所述隔离区相对于所述器件层的顶表面凹陷,以形成包括所述外延器件层的非平面半导体基体,其中,所述隔离区与所述非平面半导体基体相邻。
6.根据权利要求5所述的方法,还包括:
在所述器件层的至少两个相对侧之上形成栅极电介质和栅极电极,以控制耦合至所述器件层的源极区和漏极区之间的载流子传导。
7.根据权利要求6所述的方法,其中,所述器件层包括Ge或III-V族二元、三元或四元半导体合金,并且其中,形成所述栅极电介质和所述栅极电极还包括:蚀刻设置在所述种子表面与所述器件层之间的牺牲半导体层,以暴露出所述器件层的底表面;以及在所述底表面之上回填所述栅极电介质和所述栅极电极。
8.一种设置在硅衬底(205)之上的非平面场效应晶体管(FET),所述非平面场效应晶体管包括:
第一源极区和第一漏极区,其中,若干非硅半导体沟道(280A、280B)被设置在所述第一源极区与所述第一漏极区之间并且位于第一平面半导体种子表面(225)之上,所述第一平面半导体种子表面(225)具有除了构成所述若干非硅半导体沟道的成分以外的成分,所述第一平面半导体种子表面(225)是被隔离电介质包围的半导体平台的顶表面;
设置在所述若干非硅半导体沟道之上的第一栅极电介质层和第一栅极电极层。
9.根据权利要求8所述的非平面场效应晶体管,其中,所述若干非硅半导体沟道(280A、280B)是Ge或III-V族二元、三元或四元化合物半导体合金,并且其中,使所述若干非硅半导体沟道的中央与所述第一平面半导体种子表面(225)的中央对准。
10.根据权利要求9所述的非平面场效应晶体管,其中,所述隔离电介质的底表面与凹陷到所述第一平面半导体种子表面(225)下方的半导体表面接触。
11.根据权利要求10所述的非平面场效应晶体管,其中,使所述第一平面半导体种子表面(225)凹陷到所述隔离电介质的顶表面下方。
12.一种设置在硅衬底之上的CMOS器件,所述CMOS器件包括:
根据权利要求9到11中的一项所述的非平面场效应晶体管,其中所述非平面场效应晶体管是PMOS器件(301),并且其中所述PMOS器件(301)的若干非硅半导体沟道(280A、280B)是Ge半导体沟道;以及
NMOS器件(302),所述NMOS器件具有:
第二源极区和第二漏极区,其中,III-V族半导体沟道被设置在所述第二源极区与所述第二漏极区之间并且被设置在第二平面半导体种子表面之上,所述第二平面半导体种子表面具有除了构成所述III-V族半导体沟道的成分以外的成分,所述第二平面半导体种子表面是被所述隔离电介质包围的第二半导体平台的顶表面;以及
设置在所述III-V族半导体沟道之上的第二栅极电介质层和第二栅极电极层。
13.根据权利要求12所述的CMOS器件,其中,使所述Ge半导体沟道的中央与所述第一平面半导体种子表面的中央对准,并且其中,使所述III-V族半导体沟道的中央与所述第二平面半导体种子表面的中央对准。
CN201380045269.5A 2012-09-28 2013-06-20 沟槽限定的外延生长器件层 Active CN104603920B (zh)

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