TWI525665B - 溝渠侷限的磊晶成長裝置層 - Google Patents

溝渠侷限的磊晶成長裝置層 Download PDF

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TWI525665B
TWI525665B TW102133674A TW102133674A TWI525665B TW I525665 B TWI525665 B TW I525665B TW 102133674 A TW102133674 A TW 102133674A TW 102133674 A TW102133674 A TW 102133674A TW I525665 B TWI525665 B TW I525665B
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semiconductor
layer
planar
seed crystal
hard mask
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TW102133674A
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TW201426817A (zh
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拉維 皮拉瑞斯提
宋承宏
尼堤 高爾
傑克 卡瓦萊羅斯
山薩塔克 達斯古塔
凡 雷
威利 瑞奇曼第
馬可 拉多撒福傑維克
吉伯特 狄威
陳漢威
尼洛依 穆可吉
馬修 梅茲
羅伯特 喬
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英特爾股份有限公司
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Description

溝渠侷限的磊晶成長裝置層
本發明的實施例係在半導體裝置的領域，且更特別是關於磊晶成長裝置層。
電晶體及其它半導體裝置可經由一些消去與相加過程予以製造。某些利益，諸如電晶體的通道遷移率，可藉由以除了矽外的半導體材料形成裝置層而獲得，諸如鍺及第III-V族材料。如果結晶矽基板供作起始材料，磊晶成長技術可被利用而附加地形成電晶體通道區以整合此種非矽材料至矽基板上，典型地稱為異質磊晶。至少部分地由於晶格失配及晶種矽表面與磊晶成長半導體之間之熱膨脹係數(CTE)的失配，使得此種磊晶過程備受挑戰。
基於矽的場效電晶體(FET)裝置的先驅現已將使用非平面電晶體之裝置商業化，其利用自基板表面突出之矽材料的本體且使用環繞矽本體的二、三、或甚至所有側之閘極電極(亦即，雙閘極、三閘極、奈米線電晶 體)。源極及汲極區係形成於本體中，或作為連接至本體的再成長部分，在閘極電極的任一側上。此種非平面設計已極大地改善通道控制及相對於平面矽裝置設計之關聯的電性能(例如，短通道效應、減小的源極對汲極阻抗等)。
將有利的是，經由順從此種布局之裝置層的磊晶成長而整合非矽材料至矽基板上，特別地用於非平面電晶體設計。然而，適合製造異質磊晶裝置層在矽基板上之技術及結構係未知。例如，高度消去過程可能需要矽基板上的敷層磊晶非矽膜成長，接著在刻劃非矽、非平面本體的蝕刻後，電晶體自該本體形成。至於此種技術，晶種矽基板具有原始的優點，然而從結晶缺陷觀點而言，此種大面積成長會是一種挑戰，特別是如果磊晶膜中有經由熱膨脹或晶格失配引起之明顯應力。替代過程可能僅需要非矽膜的磊晶成長於將配置非矽、非平面本體之受限基板面積的區域中。雖然此種技術可能不受制於特別對於大面積成長的相同問題，其它問題發生。例如，自針對刻劃磊晶成長將發生的區之基板的初始處理，晶種矽表面可能遭受破壞及/或變形。如果成長基板(矽)表面的凹槽蝕刻被實施，晶種表面中的碗狀或凹陷形狀可能產生且接著損害磊晶成長。
201‧‧‧大塊基板
205‧‧‧半導體底層
213‧‧‧暴露端
215‧‧‧犧牲通道掩罩心軸結構
216A‧‧‧非犧牲間隔介電質
216B‧‧‧非犧牲間隔介電質
223‧‧‧暴露端
225‧‧‧磊晶晶種表面
226A‧‧‧非犧牲間隔介電質
226B‧‧‧非犧牲間隔介電質
230‧‧‧硬掩罩膜
235‧‧‧硬掩罩鰭片
240‧‧‧隔離介電質
241‧‧‧隔離介電質頂表面
242‧‧‧底隔離表面
245‧‧‧晶種表面側壁
246‧‧‧角圓化
250‧‧‧側壁
251‧‧‧pMOS奈米線結構
260‧‧‧溝渠
275‧‧‧中介半導體層
280A‧‧‧通道層
280B‧‧‧通道層
290A‧‧‧中介結晶層
290B‧‧‧磊晶半導體層
291‧‧‧頂表面
301‧‧‧pMOS奈米線結構
302‧‧‧nMOS奈米線結構
310A‧‧‧閘極介電質
310B‧‧‧閘極介電質
310C‧‧‧閘極介電質
315‧‧‧閘極電極材料
335A‧‧‧接點金屬化
345A‧‧‧接點金屬化
500‧‧‧插入物
700‧‧‧行動計算裝置平台
705‧‧‧顯示螢幕
710‧‧‧微電子裝置
711‧‧‧控制器
713‧‧‧電池
715‧‧‧電源管理積體電路
721‧‧‧示意圖
725‧‧‧RF(無線)積體電路(RFIC)
730‧‧‧圖形顯示器核心
731‧‧‧圖形顯示器核心
1000‧‧‧計算裝置
1002‧‧‧電路板
1004‧‧‧處理器
1006‧‧‧通訊晶片
CL‧‧‧中心線
L1‧‧‧長度
本發明的實施例係經由實例而闡明，而不是 經由限制，且當聯接圖式考慮時，參照以下詳述可更加充份瞭解。其中：圖1解說依據本發明的實施例以磊晶地成長裝置層的方法繪製所選操作之流程圖；圖2A-2G解說依據本發明的實施例在實施從圖1所示的方法之操作時，形成溝渠侷限的磊晶裝置堆疊的基板之區域的剖面圖；圖2H係依據CMOS實施例解說互補性溝渠侷限的磊晶裝置結構之等角視圖；圖3A解說依據本發明的實施例沿著使用藉由圖1所示的方法所成長的裝置層之非平面電晶體的第一維之剖面圖；圖3B解說依據本發明的實施例沿著圖3A所示之非平面電晶體的第二維之剖面圖；圖3C解說依據本發明的實施例沿著使用藉由圖1所示的方法所成長的裝置層之平面電晶體的第一維之剖面圖；圖4解說依據本發明的實施例之移動計算裝置平台的等角視圖及行動平台所使用的微電子裝置的示意圖；及圖5解說依據本發明的一實施之計算裝置的功能方塊圖。
【發明內容及實施方式】
使用磊晶成長裝置層的非平面電晶體及形成該電晶體的方法被說明。於以下說明中，許多細節被提出，然而，對於熟悉此項技術者顯而易知的是，本發明可被實施而無需這些特定細節。於一些實例中，熟知的方法及裝置係以方塊圖形式而顯示，而不是細節，以避免混淆本發明。遍及此說明書中對於“實施例”或“於一實施例中”的參照意指，聯接實施例中所述之特殊特徵、結構、功能或特性係包括於本發明的至少一實施例中。因此，此說明書中的不同位置之片語“於實施例中”的出現不一定指本發明的相同實施例。再者，特殊的特徵、結構、功能或特性可以任何適合方式組合於一或更多實施例中。例如，第一實施例可與第二實施例組合，在任何地方該二實施例未指定互斥。
用詞“耦接”及“連接”以及其衍生詞可被使用於文中以說明組件間的結構關係。應瞭解到，這些用詞並非擬作為相互的同義字。更確切的說，於特殊實施例中，“連接”可被使用來表示二或更多個元件係相互直接物理或電氣接觸。“耦接”可被使用來表示二或更多元件係相互直接或間接(具有其它中介元件於其間)物理或電氣接觸，及/或該二或更多元件相互合作或作用(例如，如於因果關係中)。
如文中所使用的用詞“之上”、“之下”、“之間”及“上”指的是一材料層或組件相對於其它層或組件的相對位置。例如，配置在另一層之上(上方)或之 下(下方)之一層可直接地與其它層接觸，或可具有一或更多中介層。再者，配置於二層之間的一層可與該二層直接地接觸或可具有一或更多中介層。對比之下，第二層“上”的第一層係與該第二層直接接觸。同樣地，除非明確說明，配置在二鄰接特徵之間的一特徵可與該等鄰接特徵直接接觸，或可具有一或更多中介特徵。
圖1解說依據本發明的實施例之用於磊晶地成長裝置層的方法101中所選操作之流程圖。圖2A-2G解說依據本發明的實施例在實施從圖1所示的方法之操作時，基板上之區域的剖面圖。圖1及2A-2G係交替地提到以提供製造技術及突出的合成結構特徵二者的精確說明。
方法101廣泛地為溝渠侷限的選擇性磊晶成長過程，其中半導體裝置層的磊晶成長進行在溝渠的侷限內。此種溝渠侷限的成長可提供深寬比捕捉(ART)的優點，因此磊晶層的結晶品質係經由在缺陷終止之溝渠的側壁捕捉穿過差排、堆疊缺陷、雙晶等而加強，使得疊加層可以是漸增地無缺陷，以及成長於分開溝渠中的鄰接裝置層可以更獨立或孤立方式同時成長。最佳ART的具有至少一相對小的尺寸(例如，2nm-100nm)之一些此種溝渠的刻劃可能夠使異質磊晶過程具有較低缺陷密度，用於裝置層中晶種結晶及磊晶成長結晶之間的指定溫度失配及晶格失配的量。
本發明人已更進一步發現，溝渠侷限的磊晶 膜品質係高度依賴侷限溝渠的特性(例如，溝渠的側壁角、溝渠的角圓化及溝渠的底滾動)，其中磊晶膜層被成長。與成長基板的某些量係凹陷蝕刻以及選擇性磊晶然後實施在凹陷蝕刻的半導體晶種表面上之溝渠形成技術相比，方法101已被發現有利地提供優質的溝渠深寬比及側壁角控制，同時亦保持原始、平面、非凹陷蝕刻的磊晶成長晶種表面為了更高品質、更佳控制的磊晶裝置層。
參照圖1A，方法101首先在操作103接收成長基板。通常，成長基板可以適合半導體裝置製造的任何材料所組成，因為文中所述的技術可廣泛地應用於任何已知成長基板，諸如，但不限於，矽、鍺、矽鍺、碳化矽、藍寶石、第III-V族化合物半導體或類似物。示範性成長基板係進一步解說於圖2A中。於此實施例中，成長基板包括以(單)結晶矽(例如，(100)矽)組成的大塊基板201。配置在大塊基板201上的是一或多個半導體底層205，諸如但未限制於假象、變質或實質晶格匹配的緩衝層及/或過渡層，如本技術領域所熟知。本發明的實施例不限於有關於底層205的結構及/或組成。如圖2A所示，無論成長基板的精確結構，有磊晶晶種表面225存在於操作103所接收的成長基板上(圖1)。晶種表面225可以是例如，具有(100)晶向等之結晶SiGe表面。
繼續方法101，硬掩罩膜係在操作105沉積在成長基板上的敷層。通常，硬掩罩膜將是可隨時移除自成長基板而不會損壞成長基板(亦即，可經由對下層成長基 板材料具高度選擇性之過程而移除)之材料，且為了適當控制的側壁角、平滑性及臨界尺寸(CD)控制可非等向性蝕刻。如文中別的地方進一步所述，硬掩罩膜的數個功能的一者將保護磊晶層成長將起始之下層半導體表面的晶種表面。硬掩罩膜的另一功能最後將界定磊晶將發生之溝渠的側壁角。
於成長基板表面包括除了矽的晶格成份(例如，SiGe合金)之一實施例中，硬掩罩膜包括一層多晶矽(p-Si)或非晶矽(a-Si)。於另一實施例中，硬掩罩膜包括一層氮化矽。作為技術的一功能，硬掩罩膜的厚度(z-高度)可改變以達到想要深寬比(亦即，厚度：側向臨界尺寸)於接著形成於硬掩罩膜中之特徵。使用來形成硬掩罩膜之沉積過程可以是任何本技術領域中可應用於這些示範性材料或任何其它適合替代材料之習知製程。示範性成長基板係進一步解說於圖2B中。於此實施例中，硬掩罩膜230係直接沉積在底層205上(亦即，與晶種表面225直接接觸)。於所述實施例中，硬掩罩膜230係單同質層，並且此種實施例係適合的，如果下層半導體包括除了矽的元件外(例如，如矽的合金、或無矽半導體)以確定對下層半導體晶種表面225的良好蝕刻選擇性。於某些此種示範性實施例中，硬掩罩膜230的厚度係超過50nm，且可進一步超過500nm，依照達到具有適當深寬比的溝渠所需之界限。
於其它實施例中，硬掩罩膜可包括一或多個 層以形成多層材料疊。通常，從臨界尺寸(CD)控制、側壁角控制、邊緣粗度等的觀點來看，提供良好蝕刻特性的材料之大塊層可被配置在與成長基板的晶種表面直接接觸之下層底層上。硬掩罩底層可以是薄於大塊層，且為適合作蝕刻終止的任何材料，允許大塊層材料及/或蝕刻過程具有對半導體基板低蝕刻選擇性。作為一實例，薄氧化層(例如，SiO2,GeO2,SixGe1-xOy)、或氮氧化層(例如，SiON,GeON,SixGe1-xOyNz)可被配置於大硬掩罩層及下層成長基板表面之間。例如，參照圖2B，硬掩罩膜230可包括直接在晶種表面225上的氧化層及直接配置在氧化層上的p-Si、a-Si或矽氮化層。至於此種實施例，氧化層的厚度可自按1nm的順序之天然氧化厚度變化至2-3nm或更大的熱成長氧化物或化學沉積氧化物(例如，藉CVD/PECVD)。
繼續方法101，在操作107，硬掩罩膜係圖案化成硬掩罩鰭片。硬掩罩鰭片係犧牲用且用作後續處理的心軸。鰭片通常具有有利於後續磊晶成長的侷限之溝渠的逆圖案，且因此鰭片的覆蓋區及鰭片的側壁角二者係有關聯的。標準微影圖案化技術可與硬掩罩膜的已知各向異性乾式電漿蝕刻組合以將硬掩罩膜圖案化成犧牲硬掩罩鰭片。
圖2C解說一示範性實施例，其中硬掩罩膜230係各向異性地蝕刻成具有側壁250的硬掩罩鰭片235，暴露周圍晶種表面225在硬掩罩膜230的各向異性 蝕刻期間或藉由蝕刻終止層的分開蝕刻(例如，薄CVD氧化物)，用於硬掩罩膜230係多層疊的實施例。替代地，蝕刻終止層可被留在周圍半導體表面上。現在認為，當初始晶種表面係配置在具有至少2：1且較佳為超過4：1的深寬比之溝渠時，ART係最成功。於硬掩罩膜230具有50-500nm的厚度之示範性實施例中，硬掩罩鰭片235可具有2nm-100nm的範圍內(例如，於圖2C的x軸上)之側向臨界尺寸用於在約5與10之間的深寬比。
於有利的實施例中，硬掩罩鰭片的側壁係大約正交下層成長基板的頂表面。例如，於圖2C中，側壁250具有相對於晶種表面225約90°(例如，88-92°)之側壁角θ。垂直鰭片側壁已被發現有利於後續界定溝渠的側壁，如在文中其它處進一步所述。於替代實施例中，側壁角θ係與硬掩罩鰭片的底部些微正向傾斜，其為比頂部更大的尺寸(亦即，非凹角)。例如，於圖2C中，側壁250可傾斜100-120°的側壁角θ。
回到圖1A，方法101進行至操作109，其中隔離係以對硬掩罩鰭片自動對準的方式而形成。於示範性實施例中，操作109需要沉積隔離介電質膜在硬掩罩鰭片上，之後平面化隔離介電質以暴露硬掩罩鰭片。於隔離介電質係保角地沉積之實施例中，介電質形成與硬掩罩鰭片的側壁互補的側壁(例如，圖2D所示的側壁250)，使得完成硬掩罩鰭片之蝕刻輪廓的反面轉換成隔離介電質膜。因此，如果硬掩罩鰭片的蝕刻係適當控制以提供非凹 角側壁(例如，正交或正向傾斜)，圍繞硬掩罩鰭片的保角隔離介電質係同樣地能夠形成具有反面圖案的適當控制側壁角(例如，正交或凹角)。
於進一步實施例中，隔離介電質係凹陷在成長基板晶種表面下方。至於此種實施例，在操作109之隔離介電質的形成進一步包含未受硬掩罩鰭片保護之半導體基板的蝕刻。如圖2D所示，此淺的溝渠隔離蝕刻以對硬掩罩鰭片235自動校準之方式移除成長基板的一部分，且更特別是移除基極半導體層205的一部分(例如，緩衝層)。成長基板的蝕刻可藉由可應用於成長基板材料系統之任何本領域習知技術所進行。於示範性實施例中，成長基板的各向異性蝕刻，諸如電漿蝕刻，被實施以保持半導體晶種表面側壁245與硬掩罩側壁250之間的保真度。例如，如果底層205係SiGe合金(例如，Si0.7Ge0.3)，乾式蝕刻被實施以推進超過晶種表面225的蝕刻前端。於所述示範性實施例中，在清除膜之前(例如，在清除底層205之前)所終止之安排的蝕刻典型的角圓化246係凹陷在晶種表面225下方。成長基板的此種凹陷可以是例如，有利地降低經由成長基板的頂層中的通路(例如，經由底層205)而發生之鄰近裝置間的漏電流。成長基板的此種凹陷可進一步能夠致使存在於晶種表面225之膜應力的工程，例如，藉由降低晶種表面225與周圓底層205之間的物理耦接(實際上放置晶種表面225在半導體基座或台面頂上)，及/或藉由能夠致使適當控制應力設計的隔離介 電質240(設計為拉伸或壓縮取決於該實施例)配置鄰接晶種表面側壁245。取決於硬掩罩膜鰭片235的x-y維度，此種應力可能多少是單軸或雙軸。
於實施例中，操作109需要一或多層介電質材料的保角沉積，諸如但不限於化學氣相沉積(例如，CVD,PECVD)氧化物(例如，SiO2)。如果超過一層被沉積，薄蝕刻終止介電質(例如，氮化矽)可被沉積在大塊介電質內(例如，SiO2)。在習用平面化技術後(例如，CMP)，所沉積介電質具有與硬掩罩鰭片的頂表面成平面之頂表面，如圖2D所示。
繼續方法101，在操作111，係選擇性地對隔離介電質及成長基板而移除硬掩罩鰭片以暴露半導體晶種表面。硬掩罩鰭片、隔離介電質及成長基板之間的材料差異有助於對硬掩罩鰭片高度選擇之硬掩罩鰭片的蝕刻，確保磊晶晶種表面未蝕刻(非凹陷)、未受損且因此具有典型起始基板的高平面性(例如，實質如在操作103所接收)。如圖2E進一步所示，原始晶種表面225係暴露在溝渠260的底部，且適當控制側壁250，造成與硬掩罩鰭片蝕刻關聯之高蝕刻選擇性。此處理及結果的結構特性係與替代處理明顯對比，因此成長基板的頂表面係相對於周圍隔離介電質或成長基板的其它區而凹陷蝕刻，以形成後續磊晶成長可被實施之溝渠。已發現到，此種半導體凹陷蝕刻可以不利於後續磊晶成長之方式而損害半導體表面。例如，微開溝(局部加速蝕刻)可能導致底半導體表面的 碗形化及/或溝角圓化。以本發明的實施例，然而，晶種表面無凹陷(例如，圖2E中的225)被實施，使得晶種表面為未蝕刻半導體表面。
於底層205為SiGe合金以及隔離介電質240為SiO2的示範性實施例中，p-Si硬掩罩材料以及氮化矽硬掩罩材料可以20-30：1或更大的選擇性、以各向異性低能蝕刻(例如，基於下游電漿、基於濕式化學等)隨時移除。於其它實施例中，如果硬掩罩膜係疊加(例如，大塊層p-Si或配置在薄氧化物上的氮化矽)，在操作111之硬掩罩鰭片的移除可能需要第一及第二蝕刻，其中硬掩罩鰭片的薄底層以高選擇性蝕刻(20-30：1或更大，在成長基板上)所移除。於實施例中，在操作111後，配置晶種表面的溝渠260具有至少5：1的深寬比(z-高度：x臨界側向尺寸)，且可以是10：1或更大，其中側壁250實質正交晶種表面225或些微凹角。於溝渠260的x尺寸係在2nm與100nm之間的實施例中，溝渠260的z-高度係在50nm及500nm之間。
方法101(圖1)在操作113繼續以結晶半導體裝置層或複數層在所製造溝渠內的磊晶成長。通常，在操作113成長的裝置層可以是任何本領域習知裝置層，其使用習知用於所選材料之任何磊晶技術(例如，藉由有機金屬化學氣相沉積MOCVD、分子束磊晶(MBE)等)。於示範性實施例中，磊晶半導體層係由於與晶種結晶表面之晶格及/或CTE失配而變形。至於一個以上裝置層磊晶 成長之實施例，晶格及/或CTE失配可另存在於磊晶裝置層間。如文中所用，“磊晶”層配準有晶種表面(例如，具有由於晶種表面的晶性之較佳結晶方位)。於晶種表面具有(100)方位之某些實施例中，磊晶裝置層亦具有(100)方位。因為磊晶成長係侷限在溝渠260內，半導體裝置層將具有與介電質240的側壁250互補之側壁。不管複合層的存在，裝置層可具有相對於晶種表面225的實質正交側壁，或些微正向傾斜(例如，偏離正交10-20)，其中側壁250係凹角。以在操作113之溝渠侷限的磊晶成長，缺陷可能朝與側壁250的介面而伸出。如果磊晶未受溝渠限制，則此種定向的伸出將不會存在(例如，其中無溝渠介面的敷層成長將存在)。再者，在溝渠侷限磊晶成長的情況下，在離晶種表面的裝置層中更遠之點，形成在晶種表面上之磊晶層內的結晶缺陷密度可能逐漸更低。
於一示範性實施例中，在操作113成長的裝置層包括至少一高遷移率通道層磊晶成長在晶種表面的上方(或直接在其上面)。高遷移率層可以是在操作113直接成長在成長基板的晶種表面上面之量子井適當結構的一部分(例如，二或三不同帶隙的磊晶層)，例如，作為適合高載子遷移率電晶體實施例之裝置層的一部分。或，如圖2F所示，裝置層可包括一些通道層，全部磊晶成長在溝渠260的侷限內，例如，以形成堆疊的奈米線電晶體裝置。替代地，圖2F所示的實施例可以是較不複雜的例 子，其中僅單一通道層係形成作為習知技術中更典型的平面電晶體通道結構。因此，圖2F意謂表示平面實施例以及堆疊的奈米線實施例二者，因為平面實施例可被視為所述之奈米線實施例的第一層。
至於底層205為SiGe合金的一實施例，由Ge組成的高電洞遷移通道層280A係選擇性地成長在晶種表面225上方。雖然某些實施例中的通道層280A係直接成長在晶種表面225上(例如，用於平面電晶體實施例)，用於圖2F所示之堆疊奈米線實施例，中介半導體層275係配置(成長)在通道層280A與晶種表面225之間。中介半導體層275可以是使其能夠相對於通道層280A被選擇性移除之合成物(反之亦然)。雖然磊晶裝置層可包括任何數量的通道層成長在溝渠260的侷限內，用於所述實施例，第二通道層280B係與中介結晶層290A成長在通道層280A上方。於通道層280A及280B係相同合成物的實施例中，然而，中介結晶層290A係不同合成物，且不能是和中介層275相同的合成物。最後，在第二通道280A上方係另一磊晶半導體層290B，其在一實施例中係如層290A的相同合成物，且更特殊地可以是具有高電子遷移率的材料，諸如合理晶格符合通道層280A、280B之已知第III-V族合金(例如，任何二元、三元或四元化合物，諸如但不限於，InAs、InAsSb、InSb、AlGaAs、GaAs等)。此種裝置堆疊可能夠致使CMOS實施，其中層290A及290B用作nMOS裝置通道而層280A 及280B用作pMOS裝置通道。至於平面電晶體實施例，單一通道層280A(或290A)將是唯一半導體裝置層，直接配置在晶種表面225上，且成長至可與所述奈米線堆疊比較之相對於周圍隔離介電質240的厚度。作為實例，平面電晶體實施係於圖3C中的圖解。
於實施例中，操作113進一步包括平面化以移除延伸高過/越過鄰接隔離介電質之任何半導體過成長。例如，圖2F解說示範性奈米線半導體裝置堆疊，具有與周圍隔離介電質240實質成平面之頂表面。在此種平面化後，磊晶成長半導體的頂表面(例如，圖2G中的頂表面291)可被配置離晶種表面為溝渠260的深度的顯著部分之距離(圖2E)。例如，於實施例中，平面化磊晶裝置層的頂表面可以是離晶種表面40nm-400nm，或超過晶種表面的最小側向尺寸三倍(例如，圖2G的x維)。
方法101(圖1)之後在操作115完成以磊晶半導體中或上之裝置的製造。此種製造可隨著裝置及/或裝置層的功能而變化。於某些實例中，諸如圖2F所示之非平面化實施例，操作115需要隔離介電質頂表面241選擇性地對裝置層的凹陷以暴露裝置層中之一或多個半導體層的一或多個側壁，給予每一溝渠侷限的磊晶成長裝置堆疊延伸在周圍隔離介電質上方之非平面半導體本體。凹陷的隔離介電質係相對於其作為侷限溝渠的角色所具有之厚度而薄化，但是所保持的厚度可適於電子裝置隔離，其中未使用作為晶種表面(亦即，未被硬掩罩鰭片保護)之成 長基板部分已被凹陷在晶種表面下方(例如，於圖1中的操作109期間)。本領域習知之可應用使隔離介電質材料凹陷之任何蝕刻技術可被利用。例如，所安排的濕式或乾式SiO2蝕刻可被使用，或於蝕刻停止層併入多層隔離介電質之實施例中，隔離凹陷蝕刻可被停止在蝕刻停止層上，其中停止層接續被移除或留下作為隔離區內的人為生成物。於圖2G所示的實施例中，在隔離介電質凹陷過程的完成之後，通道層280A及280B二者暴露在隔離頂表面241上方。
圖2H係依據CMOS實施例解說溝渠侷限的磊晶裝置堆疊之等角視圖。圖2H表示可被應用以自溝渠侷限的磊晶裝置層形成互補載子型的高遷移率電晶體的一技術。圖2H中的CMOS實施包括pMOS奈米線結構301及nMOS奈米線結構302。再者，包括平面pMOS電晶體結構及平面nMOS電晶體結構之類似CMOS結構可同樣地被形成(例如，僅使用單通道層成長在各別晶種表面上)。
於一奈米線實施例中，pMOS奈米線結構251係發展自圖2G所示的裝置堆疊。如所示，犧牲通道掩罩心軸結構215可被形成在裝置堆疊的中央區域周圍(例如，在y維的中心內)，以及犧牲用於電晶體載子類型之裝置層的交替層(例如，用於pMOS結構251的層275、290A、290B或nMOS結構252的層280A、280B)然後被蝕刻，而中央部係由掩罩心軸結構215所保護。摻雜半導體則可被沉積(或成長)在通道層280A及280B的暴露 端213、223上，其可重摻雜於過程中的某點。替代地，端213、223可一起全部更換(再成長)。通道掩罩心軸結構215然後可被移除(未繪出)，以及以非犧牲間隔介電質216A、216B、226A、226B及/或源極/汲極半導體及/或固定裝置層的接觸金屬，半導體蝕刻被實施第二次(例如，蝕刻光pMOS結構251中的層275、290A、290B及nMOS結構252中的層280A及280B)以暴露互補結構的通道層。包含保角閘極介電質層及閘極電極層的非犧牲閘極堆疊然後使用習知技術，諸如但不限於，原子層沉積(ALD)，形成在暴露的通道層之上。於示範性實施例中，第一及第二閘極介電質係保角地沉積，回填裝置層之間的任何孔洞，以完全包覆延伸在源極及汲極之間之半導體通道的表面。
尤其，雖然圖2H中的圖示描述pMOS及nMOS裝置301、302於相同狀態中，此種狀態可能不會同時發生，其中串列處理該等結構的一者進行其它的處理(例如，上述的處理可被實施多次，其中半導體層290A、290B及層280A、280B的保留之間的交替作為互補通道層於基板的分開區中)。以此方式，依據相同磊晶裝置堆疊橫越基板所界定之複數溝渠可用作pMOS及nMOS高遷移率裝置二者的依據。於一個此種實施例中，在至少一通道區內，pMOS奈米線層280A、280B的每一者為相同IV族半導體材料(例如，Ge)。同樣地，在通道區內，nMOS奈米線層290A、290B的每一者為相同 III-V族半導體材料(例如，GaAs)。於替代實施例中，pMOS奈米線層280A、280B的每一者為相同IV族半導體材料(例如，Ge)，而nMOS奈米線層290A、290B的每一者為相同IV族半導體材料(例如，Si)。
以一電晶體類型的通道層用作鄰接另一電晶體類型的通道層之犧牲層的單溝渠侷限的異質磊晶堆疊，第一半導體通道將具有沉積離晶種表面的第一距離之頂表面，以及互補傳導性型的第二半導體通道將具有沉積自晶種表面的第二距離(多於或少於第一)之頂表面。
圖3A解說依據本發明的實施例沿著使用藉由圖1所示的實施例所成長的溝渠侷限的裝置層之非平面pMOS電晶體301的第一(x)維之剖面圖。圖3B解說依據本發明的實施例沿著非平面pMOS電晶體301的第二(y)維之剖面圖。於示範性實施例中，pMOS電晶體301係在操作115(圖1)期間自pMOS結構251發展出(圖2H)。圖3C解說依據本發明的實施例沿著使用藉由圖1所示的方法所成長的裝置層之平面電晶體的第一維之剖面圖。
如圖3A所示，因為溝渠侷限的磊晶成長，通道層280A、280B的中心(由中心線CL所示)延伸穿過配置在隔離介電質240間之晶種表面225的中心。於除了重合中心外，晶種表面225的平面性還指示方法101。如圖3A進一步所示，晶種表面225相對於隔離介電質頂表面241係凹陷，而底隔離表面242係與在晶種表面225的 下方位準之下層半導體的介面。如圖3B所述，晶種表面225具有由鄰接隔離介電質240所界定的y維之長度L1。亦沿著此軸線，晶種表面225係與界定延伸在半導體源極及汲極112A、112B之間的通道層280A、280B之裝置層的中心對準。晶種表面225亦為平面沿著其整個長度L1，由於實施在未凹陷、未蝕刻的成長基板表面上之溝渠侷限的成長。底層205中的此種平面性將不存在，若未終止的半導體凹陷蝕刻被實施(例如，圓化接近隔離介電質240的介面之代替角將存在)。如圖3A及3B所述，藉由蝕刻裝置堆疊內的犧牲半導體層所形成的凹陷係回填以閘極介電質310A、310B、310C(例如，圍繞通道層280A的310A及圍繞通道層280B的310B)及閘極電極材料315。接點金屬化335A、345A係進一步沉積與源極及汲極112A、112B接觸。
如圖3C所述，用於平面電晶體實施例中，單通道層280A、(或290A)將是唯一半導體裝置層，直接配置在晶種表面225上，且成長至相對於周圍隔離介電質240之厚度以達到橫越隔離介電質240及通道層280A之平坦表面。
圖4解說依據本發明的實施例之行動計算裝置平台700的等角視圖及由行動平台所使用的微電子裝置710的示意圖721。行動計算平台700可以是組構用於電子資料顯示、電子資料處理及無線電子資料傳輸的每一者之任何可攜式裝置。例如，行動計算平台700可以是平 板、智慧型手機、膝上型電腦等的任一者，且包括示範性實施例中為觸控螢幕(電容、電感、電阻等)的顯示螢幕705、晶片層級(SoC)或封裝層級積體微電子裝置710及電池713。
積體裝置710係進一步解說於展開圖721中。於示範性實施例中，裝置710包括至少一記憶體、至少一處理晶片(例如，多核心微處理器及/或圖形處理器核心730、731)。用詞“處理器”可意指任何裝置或處理來自暫存器及/或記憶體的電子資料之裝置的一部分，以將該電子資料轉換成可被儲存於暫存器及/或記憶體中的其它電子資料。於實施例中，處理器晶片或記憶體中的一或多個電晶體包括配置在平面晶種層上的異質磊晶通道層，其中隔離介電質形成圍繞晶種層的周圍，如文中其它地方更加詳述(例如，圖3A及3B)，併入裝置710中。裝置710係與電源管理積體電路(PMIC)715、包括寬頻RF(無線)發射器及/或接收器的RF(無線)積體電路(RFIC)725(例如，包括數位基頻及類比前端模組進一步包含功率放大器在發射路徑上及低雜訊放大器在接收路徑上)、及其控制器711之一或多者一起進一步耦接至控制板、基板或插入物500。功能性地，PMIC715實施電池電源調節、DC對DC轉換等，且因此具有耦接至電池713的輸入並具有提供電流供應給所有其它功能性模組之輸出。如進一步所述，於示範性實施例中，RFIC725具有耦接至天線之輸出以提供實施一些無線標準或協定的任一 者，包括但不限於，Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生者，以及指定為3G、4G、5G及超越的任何其它無線協定。於實施中，這些模組的每一者可被整合至單晶片上作為SoC，至耦接至封裝裝置710的封裝基板之分開IC上，或在板層次。
圖5係依據本發明的一實施例之計算裝置1000的功能方塊圖。計算裝置1000可被發現在平台700內，例如，且進一步包括主控一些組件的電路板1002，諸如但不限於，處理器1004(例如，應用處理器)及至少一通訊晶片1006。於實施例中，至少處理器1004係與一或多個電晶體整合(例如，晶片上)於處理器晶片或記憶體中，依據文中其它所述的實施例，包括配置在平面晶種層上之異質磊晶通道層以及隔離介電質形成圍繞晶種層的周圍。處理器1004係物理且電氣地耦接至電路板1002。處理器1004包括封裝在處理器1004內的積體電路晶片。
於某些實例中，至少一通訊晶片1006亦物理且電氣地耦接至電路板1002。於其它實施中，通訊晶片1006係處理器1004的一部分。取決於其應用，計算裝置1000可包括可或不可物理且電氣地耦接至電路板1002的其它組件。這些其它組件包括但不限於，依電性記憶體 (例如，DRAM)、以快閃記憶體等的形式的非依電性記憶體(例如，RAM或ROM)、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編解碼器、視頻編解碼器、功率放大器、全球定位系統(GPS)裝置、指南針、加速器、陀螺儀、音箱、相機、及大量儲存裝置(諸如硬碟機、固態硬碟(SSD)、光碟(CD)、數位多功能光碟(DVD)等等)。
通訊晶片1006的至少一者能夠致使無線通訊轉移資料至及自計算裝置1000。用詞“無線”及其衍生詞可被使用來說明可經由非固態媒體利用調變的電磁幅射傳達資料之電路、裝置、系統、方法、技術、通訊通道等。該用詞未意味關聯的裝置不含有任何線，雖然某些實施例中它們可能不會。通訊晶片1006可實施一些無線標準或協定的任一者，包括但不限於，文中其它所述。計算裝置1000可包括複數通訊晶片1006。例如，第一通訊晶片1006可專屬於較短距離無線通訊諸如Wi-Fi及藍芽，以及第二通訊晶片1006可專屬於較長距離無線通訊諸如GPS,EDGE,GPRS,CDMA,WiMAX,LTE,Ev-DO及其它。
因此，溝渠侷限的異質磊晶裝置堆疊及其製造的實施例被說明。於實施例中，形成異質磊晶裝置層在基板上的方法，該方法包括：接收具有半導體晶種表面的基板；形成硬掩罩鰭片在晶種表面之上；形成鄰接該硬掩罩鰭片的隔離區；藉由相對於該隔離區選擇性地移除該硬 掩罩鰭片，形成溝渠，該晶種表面在該溝渠的底部；及磊晶地成長半導體層在該溝渠內，該半導體層具有與該半導體晶種表面之晶格常數失配或熱膨脹係數(CTE)失配的至少一者。於實施例中，形成該硬掩罩鰭片進一步包含沉積多晶矽或氮化矽層在該晶種表面之上；以及以各向異性蝕刻圖案化該多晶矽或氮化矽層。於實施例中，形成該硬掩罩鰭片進一步包含直接地沉積蝕刻終止層在該晶種表面上以及沉積該多晶矽或氮化矽層在氧化物層之上。於實施例中，各向異性蝕刻形成垂直側壁或些微正向傾斜側壁，以及其中該硬掩罩鰭片具有至少5：1的深寬比。於實施例中，形成隔離區進一步包含：沉積隔離介電質層在該硬掩罩鰭片之上，及平面化該隔離介電質層以暴露該硬掩罩鰭片的頂表面。於實施例中，形成該隔離區進一步包含：蝕刻該基板鄰接該硬掩罩鰭片的部分以使未受該硬掩罩鰭片保護的該基板部分相對於該晶種表面而凹陷；及沉積該隔離介電質層在該凹陷的基板表面之上。於實施例中，該方法進一步包含：平面化具有該隔離區之該磊晶裝置層的頂表面；及使該隔離區相對於該磊晶裝置層的頂表面而凹陷以形成非平面半導體本體，其包含具有鄰接至該非平面半導體本體的該隔離區之該磊晶裝置層。於實施例中，該方法進一步包含：形成閘極介電質及閘極電極在該磊晶裝置層的至少二相對側之上，用於耦接至該裝置層之源極及汲極區之間的載子傳導的控制。於實施例中，該磊晶裝置層包含Ge或第III-V族二元、三元、或四元半導體合金， 以及形成該閘極介電質及該閘極電極進一步包含蝕刻配置在該晶種表面及該磊晶裝置層之間的犧牲半導體層以暴露該磊晶裝置層的底表面；及回填該閘極介電質及該閘極電極在該底表面之上。
於實施例中，一種配置在矽基板之上的非平面場效電晶體(FET)，該非平面FET包含：源極區及汲極區，具有非矽半導體通道配置於其間且在平面半導體晶種表面之上，該平面半導體晶種表面具有除了該非矽半導體通道的組成之外之組成，該平面半導體晶種表面係由隔離介電質所圍繞之半導體台面的頂表面；閘極介電質層及閘極電極層，配置在該非矽半導體通道之上。於實施例中，該非矽半導體通道為Ge或第III-V族二元、三元、或四元化合物半導體合金，以及其中該通道的中央係與該平面半導體晶種表面的中央對準。於實施例中，該隔離介電質的底表面係與凹陷在該晶種表面下方的半導體表面接觸。於實施例中，該晶種表面係凹陷在該介電質隔離的頂表面下方。於實施例中，該非矽半導體通道係具有配置離該晶種表面有該晶種表面的最小側向尺寸至少三倍的距離的頂表面之半導體堆疊的一層。
於實施例中，一種配置在矽基板之上的CMOS裝置，該CMOS裝置包含：pMOS裝置，具有第一源極區及第一汲極區，具有Ge半導體通道配置於其間且配置在第一平面半導體晶種表面之上，該第一平面半導體晶種表面具有除了該通道的組成之外之組成，該第一平面 半導體晶種表面係由隔離介電質所圍繞之第一半導體台面的頂表面；及第一閘極介電質層及第一閘極電極層，配置在該Ge半導體通道之上；以及nMOS裝置，具有：第二源極區及第二汲極區，具有第III-V族半導體通道配置於其間且配置在第二平面半導體晶種表面之上，該第二平面半導體晶種表面具有除了該通道的組成之外之組成，該第二平面半導體晶種表面係由隔離介電質所圍繞之第二半導體台面的頂表面；及第二閘極介電質層及第二閘極電極層，配置在該第III-V族半導體通道之上。於實施例中，該Ge半導體通道具有配置離該晶種表面的第一距離之頂表面，以及該第III-V族半導體通道具有配置離該晶種表面不同於該第一距離的第二距離之頂表面。於實施例中，該Ge半導體通道的中央係與該第一平面半導體晶種表面的中央對準，以及其中該第III-V族半導體通道的中央係與該第二平面半導體晶種表面的中央對準。於實施例中，該第一及第二晶種表面係凹陷在該隔離介電質的頂表面下方。於實施例中，該第一及第二閘極介電質完全包圍延伸在該源極及汲極之間的該半導體通道的表面。
於實施例中，行動計算平台包括含有本文所述的非平面FET或文中所述的CMOS裝置之積體電路、顯示螢幕及無線收發器。
因此，本發明的一或多個實施例廣泛地關於溝渠侷限的異質磊晶裝置堆疊。將瞭解到，以上說明打算用於解說，而非限制。例如，雖然圖式中的流程圖顯示由 本發明的某些實施例所實施之操作的特殊順序，應瞭解到，此種順序不是必要(例如，替代實施例可實施不同順序的操作，組合某些操作，重疊某些操作等)。再者，對熟悉此項技術者而言，在閱讀且瞭解以上說明之後，許多其它實施例將是顯而易知。雖然本發明已參照特定示範性實施例予以說明，將領會到，本發明未限制所述的實施例，但可以附加請求項的精神及範圍內之修改及變更而實施。本發明的範圍因此應參照附加請求項以及這些請求項被賦予權利之等效物的全部範圍予以決定。

Claims (20)

  1. 一種形成異質磊晶裝置層在基板上的方法，該方法包含：接收具有半導體晶種表面的基板；形成硬掩罩鰭片在該晶種表面之上；形成鄰接該硬掩罩鰭片的隔離區；藉由移除該硬掩罩鰭片，形成溝渠，該晶種表面在該溝渠的底部；及磊晶地成長半導體層在該溝渠內，該半導體層具有與該半導體晶種表面之晶格常數失配或熱膨脹係數(CTE)失配的至少一者。
  2. 如申請專利範圍第1項的方法，其中形成該硬掩罩鰭片進一步包含沉積多晶矽或氮化矽層在該晶種表面之上，以及以各向異性蝕刻圖案化該多晶矽或氮化矽層。
  3. 如申請專利範圍第2項的方法，其中形成該硬掩罩鰭片進一步包含直接地沉積蝕刻終止層在該晶種表面上，以及沉積該多晶矽或氮化矽層在氧化物層之上。
  4. 如申請專利範圍第2項的方法，其中該各向異性蝕刻形成垂直側壁或些微正向傾斜側壁，以及該硬掩罩鰭片具有至少5：1的深寬比。
  5. 如申請專利範圍第1項的方法，其中形成該隔離區進一步包含：沉積隔離介電質層在該硬掩罩鰭片之上；及平面化該隔離介電質層以暴露該硬掩罩鰭片的頂表 面。
  6. 如申請專利範圍第5項的方法，其中形成該隔離區進一步包含：蝕刻該基板鄰接該硬掩罩鰭片的部分，以使未受該硬掩罩鰭片保護的該基板部分相對於該晶種表面而凹陷；及沉積該隔離介電質層在該凹陷的基板表面之上。
  7. 如申請專利範圍第1項的方法，進一步包含：平面化具有該隔離區之該磊晶裝置層的頂表面；及使該隔離區相對於該磊晶裝置層的頂表面而凹陷以形成非平面半導體本體，其包含具有鄰接至該非平面半導體本體的該隔離區之該磊晶裝置層。
  8. 如申請專利範圍第7項的方法，進一步包含：形成閘極介電質及閘極電極在該磊晶裝置層的至少二相對側之上，用於耦接至該裝置層之源極區及汲極區之間的載子傳導的控制。
  9. 如申請專利範圍第8項的方法，其中該磊晶裝置層包含Ge或第III-V族二元、三元、或四元半導體合金，以及其中形成該閘極介電質及該閘極電極進一步包含蝕刻配置在該晶種表面及該磊晶裝置層之間的犧牲半導體層以暴露該磊晶裝置層的底表面；及回填該閘極介電質及該閘極電極在該底表面之上。
  10. 一種配置在矽基板之上的非平面場效電晶體(FET)，該非平面FET包含：源極區及汲極區，具有非矽半導體通道配置於其間且 在平面半導體晶種表面之上，該平面半導體晶種表面具有除了該非矽半導體通道的組成之外的組成，該平面半導體晶種表面係為由隔離介電質所圍繞之半導體台面的頂表面；及閘極介電質層及閘極電極層，配置在該非矽半導體通道之上。
  11. 如申請專利範圍第10項的非平面FET，其中該非矽半導體通道為Ge或第III-V族二元、三元、或四元化合物半導體合金，以及其中該通道的中央係與該平面半導體晶種表面的中央對準。
  12. 如申請專利範圍第11項的非平面FET，其中該隔離介電質的底表面係與凹陷在該晶種表面下方的半導體表面接觸。
  13. 如申請專利範圍第12項的非平面FET，其中該晶種表面係凹陷在該介電質隔離的頂表面下方。
  14. 如申請專利範圍第12項的非平面FET，其中該非矽半導體通道係具有配置離該晶種表面有該晶種表面的最小側向尺寸至少三倍的距離的頂表面之半導體堆疊的一層。
  15. 一種配置在矽基板之上的CMOS裝置，該CMOS裝置包含：pMOS裝置，具有：第一源極區及第一汲極區，具有Ge半導體通道配置於其間且配置在第一平面半導體晶種表面之上，該第 一平面半導體晶種表面具有除了該通道的組成之外的組成，該第一平面半導體晶種表面係為由隔離介電質所圍繞之第一半導體台面的頂表面；及第一閘極介電質層及第一閘極電極層，配置在該Ge半導體通道之上；及nMOS裝置，具有：第二源極區及第二汲極區，具有第III-V族半導體通道配置於其間且配置在第二平面半導體晶種表面之上，該第二平面半導體晶種表面具有除了該通道的組成之外的組成，該第二平面半導體晶種表面係為由該隔離介電質所圍繞之第二半導體台面的頂表面；及第二閘極介電質層及第二閘極電極層，配置在該第III-V族半導體通道之上。
  16. 如申請專利範圍第15項的CMOS裝置，其中該Ge半導體通道具有配置離該晶種表面的第一距離之頂表面，以及該第III-V族半導體通道具有配置離該晶種表面不同於該第一距離的第二距離之頂表面。
  17. 如申請專利範圍第15項的CMOS裝置，其中該Ge半導體通道的中央係與該第一平面半導體晶種表面的中央對準，以及其中該第III-V族半導體通道的中央係與該第二平面半導體晶種表面的中央對準。
  18. 如申請專利範圍第17項的CMOS裝置，其中該第一晶種表面及該第二晶種表面係凹陷在該隔離介電質的頂表面下方。
  19. 如申請專利範圍第15項的CMOS裝置，其中該第一閘極介電質及該第二閘極介電質完全包圍延伸在該源極及汲極之間的該半導體通道的表面。
  20. 一種行動計算平台，包含：積體電路，包含如申請專利範圍第10項的非平面FET或如申請專利範圍第16項的CMOS裝置，顯示螢幕；及無線收發器。
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Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095656A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition
US9484447B2 (en) 2012-06-29 2016-11-01 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices
US9728464B2 (en) 2012-07-27 2017-08-08 Intel Corporation Self-aligned 3-D epitaxial structures for MOS device fabrication
EP2717316B1 (en) * 2012-10-05 2019-08-14 IMEC vzw Method for producing strained germanium fin structures
US8896101B2 (en) * 2012-12-21 2014-11-25 Intel Corporation Nonplanar III-N transistors with compositionally graded semiconductor channels
US9171843B2 (en) 2013-08-02 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
US11404325B2 (en) 2013-08-20 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation
US9184269B2 (en) * 2013-08-20 2015-11-10 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US9147766B2 (en) * 2013-11-14 2015-09-29 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device having fin-type channel and method for forming the same
US9590090B2 (en) 2014-01-08 2017-03-07 Taiwan Semiconductor Manufacturing Company Limited Method of forming channel of gate structure
US9214553B2 (en) * 2014-03-07 2015-12-15 Globalfoundries Inc. Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
US9412822B2 (en) 2014-03-07 2016-08-09 Globalfoundries Inc. Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
WO2015199655A1 (en) * 2014-06-24 2015-12-30 Intel Corporation Techniques for forming ge/sige-channel and iii-v-channel transistors on the same die
US9252208B1 (en) 2014-07-31 2016-02-02 Stmicroelectronics, Inc. Uniaxially-strained FD-SOI finFET
US9306019B2 (en) * 2014-08-12 2016-04-05 GlobalFoundries, Inc. Integrated circuits with nanowires and methods of manufacturing the same
GB201415119D0 (en) 2014-08-27 2014-10-08 Ibm Method for fabricating a semiconductor structure
US20160071729A1 (en) * 2014-09-04 2016-03-10 Samsung Electronics Co., Ltd. Rectangular nanosheet fabrication
CN107004712B (zh) * 2014-12-23 2021-04-20 英特尔公司 利用基于深宽比沟槽的工艺形成均匀层
CN107004711B (zh) 2014-12-23 2021-04-06 英特尔公司 用于非平面半导体器件鳍下中的iii-v族半导体合金及其形成方法
KR102309367B1 (ko) * 2014-12-24 2021-10-07 인텔 코포레이션 비대칭 프로파일을 갖는 핀 구조체들을 형성하는 방법 및 장치
KR102349897B1 (ko) * 2014-12-24 2022-01-12 인텔 코포레이션 Ingaas epi 구조체 및 art 트렌치에서 iii-v gaa를 가능하게 하는 습식 에치 공정
CN107210259B (zh) * 2014-12-26 2020-10-27 英特尔公司 使用牺牲子鳍状物在硅衬底上形成的高迁移率纳米线鳍状物沟道
US9847333B2 (en) * 2015-03-09 2017-12-19 Globalfoundries Inc. Reducing risk of punch-through in FinFET semiconductor structure
US9437502B1 (en) 2015-06-12 2016-09-06 International Business Machines Corporation Method to form stacked germanium nanowires and stacked III-V nanowires
CN107636834B (zh) * 2015-06-16 2021-11-09 英特尔公司 具有子鳍状物层的晶体管
EP3314661A4 (en) * 2015-06-24 2019-02-13 Intel Corporation SUB-FIN SIDE WALL PASSIVATION AT REPLACEMENT CHANNEL FINFETS
KR102492181B1 (ko) 2015-06-27 2023-01-26 인텔 코포레이션 희생층으로서 gaas를 가지는 ge 나노와이어 트랜지스터
US9647139B2 (en) * 2015-09-04 2017-05-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
WO2017052587A1 (en) 2015-09-25 2017-03-30 Intel Corporation Passivation of transistor channel region interfaces
US9484405B1 (en) 2015-09-29 2016-11-01 International Business Machines Corporation Stacked nanowire devices formed using lateral aspect ratio trapping
KR102379701B1 (ko) * 2015-10-19 2022-03-28 삼성전자주식회사 멀티-채널을 갖는 반도체 소자 및 그 형성 방법
US20200258740A1 (en) * 2015-11-16 2020-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Forming Stacked Nanowire Transistors
US10204985B2 (en) * 2015-11-16 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10164121B2 (en) * 2015-11-25 2018-12-25 Samsung Electronics Co., Ltd. Stacked independently contacted field effect transistor having electrically separated first and second gates
US9425291B1 (en) 2015-12-09 2016-08-23 International Business Machines Corporation Stacked nanosheets by aspect ratio trapping
CN106910716B (zh) * 2015-12-22 2021-10-15 Imec 非营利协会 Si基高迁移率CMOS装置的制造方法及所得装置
KR102367408B1 (ko) 2016-01-04 2022-02-25 삼성전자주식회사 복수의 시트들로 구성된 채널 영역을 포함하는 sram 소자
KR102366953B1 (ko) * 2016-01-06 2022-02-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9755017B1 (en) * 2016-03-01 2017-09-05 International Business Machines Corporation Co-integration of silicon and silicon-germanium channels for nanosheet devices
US10749032B2 (en) * 2016-03-11 2020-08-18 Intel Corporation Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers
US10439039B2 (en) * 2016-03-25 2019-10-08 Qualcomm Incorporated Integrated circuits including a FinFET and a nanostructure FET
US10249492B2 (en) 2016-05-27 2019-04-02 International Business Machines Corporation Fabrication of compound semiconductor structures
US9735010B1 (en) 2016-05-27 2017-08-15 International Business Machines Corporation Fabrication of semiconductor fin structures
US9768075B1 (en) 2016-06-20 2017-09-19 International Business Machines Corporation Method and structure to enable dual channel fin critical dimension control
US9876090B1 (en) * 2016-06-30 2018-01-23 International Business Machines Corporation Lattice matched and strain compensated single-crystal compound for gate dielectric
US10332986B2 (en) 2016-08-22 2019-06-25 International Business Machines Corporation Formation of inner spacer on nanosheet MOSFET
US9876088B1 (en) * 2016-09-19 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof
WO2018057023A1 (en) * 2016-09-25 2018-03-29 Intel Corporation Quantum dot qubits with iii-v compounds
US9853114B1 (en) * 2016-10-24 2017-12-26 Samsung Electronics Co., Ltd. Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
US10312152B2 (en) 2016-10-24 2019-06-04 Samsung Electronics Co., Ltd. Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
CN106549047B (zh) * 2016-11-03 2020-10-02 武汉华星光电技术有限公司 一种纳米线无结晶体管及其制备方法
KR102574454B1 (ko) * 2016-12-16 2023-09-04 삼성전자 주식회사 반도체 장치 및 그 제조 방법
EP3382761A1 (en) 2017-03-29 2018-10-03 IMEC vzw Integration of silicon-germanium semiconductor structures
KR102318560B1 (ko) * 2017-04-12 2021-11-01 삼성전자주식회사 반도체 소자
US10217900B2 (en) * 2017-07-06 2019-02-26 Globalfoundries Inc. Light emitting diode structures
US10103238B1 (en) 2017-07-18 2018-10-16 Globalfoundries Inc. Nanosheet field-effect transistor with full dielectric isolation
US9947804B1 (en) 2017-07-24 2018-04-17 Globalfoundries Inc. Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
US10056379B1 (en) 2017-07-28 2018-08-21 International Business Machines Corporation Low voltage (power) junction FET with all-around junction gate
US10700066B2 (en) 2017-11-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11081567B2 (en) 2018-03-12 2021-08-03 International Business Machines Corporation Replacement-channel fabrication of III-V nanosheet devices
US10431651B1 (en) 2018-04-30 2019-10-01 International Business Machines Corporation Nanosheet transistor with robust source/drain isolation from substrate
US10332809B1 (en) * 2018-06-21 2019-06-25 International Business Machines Corporation Method and structure to introduce strain in stack nanosheet field effect transistor
US10461154B1 (en) * 2018-06-21 2019-10-29 International Business Machines Corporation Bottom isolation for nanosheet transistors on bulk substrate
US11233152B2 (en) * 2018-06-25 2022-01-25 Intel Corporation Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
US10332881B1 (en) 2018-08-17 2019-06-25 Qualcomm Incorporated Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die
US11043578B2 (en) 2018-08-30 2021-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Nanowire stack GAA device with inner spacer
US10573755B1 (en) 2018-09-12 2020-02-25 International Business Machines Corporation Nanosheet FET with box isolation on substrate
US11038036B2 (en) 2018-09-26 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Separate epitaxy layers for nanowire stack GAA device
US11031298B2 (en) * 2018-11-30 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11062937B2 (en) 2019-01-11 2021-07-13 International Business Machines Corporation Dielectric isolation for nanosheet devices
US10665669B1 (en) 2019-02-26 2020-05-26 Globalfoundries Inc. Insulative structure with diffusion break integral with isolation layer and methods to form same
US10937860B2 (en) 2019-03-14 2021-03-02 International Business Machines Corporation Nanosheet transistor bottom isolation
DE102020114846B4 (de) 2019-10-29 2024-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zum bilden von gestapelten schichten
US11488858B2 (en) * 2019-10-29 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming stacked layers and devices formed thereof
KR20210059471A (ko) * 2019-11-15 2021-05-25 삼성전자주식회사 집적회로 장치 및 그 제조 방법
US11799009B2 (en) * 2019-12-17 2023-10-24 Intel Corporation Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact
US11222952B2 (en) 2020-01-22 2022-01-11 Qualcomm Incorporated Gate all around transistors with high charge mobility channel materials
US12046652B2 (en) * 2020-06-25 2024-07-23 Intel Corporation Plug and recess process for dual metal gate on stacked nanoribbon devices
US11532520B2 (en) 2020-08-14 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11664424B2 (en) 2020-09-30 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Device with epitaxial source/drain region
US11532708B2 (en) 2020-12-04 2022-12-20 Tokyo Electron Limited Stacked three-dimensional field-effect transistors
KR20220100161A (ko) * 2021-01-08 2022-07-15 삼성전자주식회사 분리 구조체를 갖는 반도체 소자들
US11605727B2 (en) * 2021-03-31 2023-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device and a semiconductor device
KR20230122831A (ko) * 2022-02-15 2023-08-22 삼성전자주식회사 반도체 소자 및 그의 제조 방법
WO2023225155A1 (en) * 2022-05-20 2023-11-23 Tokyo Electron Limited Sequential complimentary fet incorporating backside power distribution network through wafer bonding prior to formation of active devices
EP4283663A1 (en) * 2022-05-24 2023-11-29 Imec VZW A method for forming a stacked transistor device

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2010707A (en) 1935-01-17 1935-08-06 Young Edward Bicycle stand lock
US6617226B1 (en) * 1999-06-30 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
KR100487525B1 (ko) 2002-04-25 2005-05-03 삼성전자주식회사 실리콘게르마늄 게이트를 이용한 반도체 소자 및 그 제조방법
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
US6815738B2 (en) * 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
US6921700B2 (en) 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels
US6835618B1 (en) * 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100550343B1 (ko) 2003-11-21 2006-02-08 삼성전자주식회사 다중 채널 모오스 트랜지스터를 포함하는 반도체 장치의제조 방법
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
KR100576361B1 (ko) * 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US7098477B2 (en) 2004-04-23 2006-08-29 International Business Machines Corporation Structure and method of manufacturing a finFET device having stacked fins
KR100674914B1 (ko) 2004-09-25 2007-01-26 삼성전자주식회사 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법
US7205924B2 (en) 2004-11-18 2007-04-17 Texas Instruments Incorporated Circuit for high-resolution phase detection in a digital RF processor
US7282425B2 (en) * 2005-01-31 2007-10-16 International Business Machines Corporation Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
KR100699839B1 (ko) * 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US8324660B2 (en) * 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR100647710B1 (ko) * 2005-10-21 2006-11-23 삼성에스디아이 주식회사 박막 트랜지스터, 이의 제조 방법 및 이를 구비한 평판표시 장치
US7777250B2 (en) * 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
KR20080012055A (ko) * 2006-08-02 2008-02-11 주식회사 하이닉스반도체 마스크 패턴 형성 방법
WO2008039495A1 (en) * 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
WO2008051503A2 (en) * 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US7755140B2 (en) * 2006-11-03 2010-07-13 Intel Corporation Process charging and electrostatic damage protection in silicon-on-insulator technology
EP1975988B1 (en) * 2007-03-28 2015-02-25 Siltronic AG Multilayered semiconductor wafer and process for its production
KR100855857B1 (ko) 2007-04-13 2008-09-01 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
US7923337B2 (en) * 2007-06-20 2011-04-12 International Business Machines Corporation Fin field effect transistor devices with self-aligned source and drain regions
US20090001415A1 (en) * 2007-06-30 2009-01-01 Nick Lindert Multi-gate transistor with strained body
US7723798B2 (en) * 2007-08-07 2010-05-25 International Business Machines Corporation Low power circuit structure with metal gate and high-k dielectric
US7843264B2 (en) 2008-01-29 2010-11-30 Qualcomm, Incorporated Differential amplifier with accurate input offset voltage
US7839062B2 (en) * 2008-08-29 2010-11-23 Bridgelux Inc. Optical platform to enable efficient LED emission
US9117944B2 (en) * 2008-09-24 2015-08-25 Koninklijke Philips N.V. Semiconductor light emitting devices grown on composite substrates
US8253211B2 (en) * 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US7893492B2 (en) 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8440517B2 (en) * 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8937353B2 (en) * 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device
CN102299178B (zh) * 2010-06-22 2014-03-26 中国科学院微电子研究所 一种半导体结构及其制备方法
US8575653B2 (en) * 2010-09-24 2013-11-05 Intel Corporation Non-planar quantum well device having interfacial layer and method of forming same
US8753942B2 (en) * 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
US9673102B2 (en) * 2011-04-01 2017-06-06 Micron Technology, Inc. Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby
US8455883B2 (en) * 2011-05-19 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Stressed semiconductor device and method of manufacturing
US9761666B2 (en) * 2011-06-16 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US8395217B1 (en) * 2011-10-27 2013-03-12 International Business Machines Corporation Isolation in CMOSFET devices utilizing buried air bags
US8580624B2 (en) * 2011-11-01 2013-11-12 International Business Machines Corporation Nanowire FET and finFET hybrid technology
US8497171B1 (en) * 2012-07-05 2013-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET method and structure with embedded underlying anti-punch through layer
US8785909B2 (en) * 2012-09-27 2014-07-22 Intel Corporation Non-planar semiconductor device having channel region with low band-gap cladding layer

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US8765563B2 (en) 2014-07-01
US20140291726A1 (en) 2014-10-02
KR101988707B1 (ko) 2019-06-12
US9634007B2 (en) 2017-04-25
TW201426817A (zh) 2014-07-01
EP2901472A1 (en) 2015-08-05
KR20160125525A (ko) 2016-10-31
EP2901472A4 (en) 2016-05-18
CN104603920B (zh) 2017-06-13
EP2901472B1 (en) 2022-08-17
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TWI578383B (zh) 2017-04-11
CN107275331A (zh) 2017-10-20
CN107275331B (zh) 2022-01-25
KR20150038419A (ko) 2015-04-08
US20140091360A1 (en) 2014-04-03
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