CN104465580B - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN104465580B
CN104465580B CN201410471924.XA CN201410471924A CN104465580B CN 104465580 B CN104465580 B CN 104465580B CN 201410471924 A CN201410471924 A CN 201410471924A CN 104465580 B CN104465580 B CN 104465580B
Authority
CN
China
Prior art keywords
metal
semiconductor packages
package
packages according
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410471924.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN104465580A (zh
Inventor
金东先
柳盛旭
李知行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020130110974A external-priority patent/KR102109042B1/ko
Priority claimed from KR1020130115333A external-priority patent/KR102091619B1/ko
Priority claimed from KR1020130115332A external-priority patent/KR102093927B1/ko
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of CN104465580A publication Critical patent/CN104465580A/zh
Application granted granted Critical
Publication of CN104465580B publication Critical patent/CN104465580B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
CN201410471924.XA 2013-09-16 2014-09-16 半导体封装 Active CN104465580B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR1020130110974A KR102109042B1 (ko) 2013-09-16 2013-09-16 반도체 패키지
KR10-2013-0110974 2013-09-16
KR10-2013-0115332 2013-09-27
KR10-2013-0115333 2013-09-27
KR1020130115333A KR102091619B1 (ko) 2013-09-27 2013-09-27 반도체 패키지
KR1020130115332A KR102093927B1 (ko) 2013-09-27 2013-09-27 반도체 패키지

Publications (2)

Publication Number Publication Date
CN104465580A CN104465580A (zh) 2015-03-25
CN104465580B true CN104465580B (zh) 2017-08-04

Family

ID=51518709

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410471924.XA Active CN104465580B (zh) 2013-09-16 2014-09-16 半导体封装

Country Status (5)

Country Link
US (1) US9252112B2 (https=)
EP (1) EP2849226B1 (https=)
JP (1) JP6419500B2 (https=)
CN (1) CN104465580B (https=)
TW (1) TWI646639B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI517269B (zh) * 2013-09-27 2016-01-11 矽品精密工業股份有限公司 層疊式封裝結構及其製法
KR102152865B1 (ko) * 2014-02-06 2020-09-07 엘지이노텍 주식회사 인쇄회로기판, 이를 포함하는 패키지 기판 및 이의 제조 방법
JP2016171190A (ja) * 2015-03-12 2016-09-23 イビデン株式会社 パッケージ−オン−パッケージ用プリント配線板
KR102446861B1 (ko) 2017-09-21 2022-09-23 삼성전자주식회사 적층 패키지 및 그의 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
CN101083244A (zh) * 2006-01-19 2007-12-05 尔必达存储器股份有限公司 半导体封装及制造方法和衬底和半导体器件及制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145327A (ja) * 1997-11-07 1999-05-28 Shinko Electric Ind Co Ltd 半導体装置および該半導体装置の実装構造
JP4917874B2 (ja) * 2006-12-13 2012-04-18 新光電気工業株式会社 積層型パッケージ及びその製造方法
JP5003260B2 (ja) * 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
JP5217043B2 (ja) * 2007-07-11 2013-06-19 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5056718B2 (ja) * 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
JP5193898B2 (ja) * 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置
KR20100121231A (ko) * 2009-05-08 2010-11-17 삼성전자주식회사 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package
US8482111B2 (en) * 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
JP5599276B2 (ja) * 2010-09-24 2014-10-01 新光電気工業株式会社 半導体素子、半導体素子実装体及び半導体素子の製造方法
JP5462777B2 (ja) * 2010-12-09 2014-04-02 日本特殊陶業株式会社 多層配線基板の製造方法
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
KR101167805B1 (ko) * 2011-04-25 2012-07-25 삼성전기주식회사 패키지 기판 및 이의 제조방법
JP5906812B2 (ja) * 2012-02-29 2016-04-20 富士通株式会社 配線構造、半導体装置及び配線構造の製造方法
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
CN101083244A (zh) * 2006-01-19 2007-12-05 尔必达存储器股份有限公司 半导体封装及制造方法和衬底和半导体器件及制造方法

Also Published As

Publication number Publication date
JP6419500B2 (ja) 2018-11-07
JP2015057827A (ja) 2015-03-26
TW201517222A (zh) 2015-05-01
EP2849226B1 (en) 2018-08-22
CN104465580A (zh) 2015-03-25
TWI646639B (zh) 2019-01-01
EP2849226A2 (en) 2015-03-18
US20150076691A1 (en) 2015-03-19
EP2849226A3 (en) 2015-04-29
US9252112B2 (en) 2016-02-02

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