JP5217043B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5217043B2 JP5217043B2 JP2007181994A JP2007181994A JP5217043B2 JP 5217043 B2 JP5217043 B2 JP 5217043B2 JP 2007181994 A JP2007181994 A JP 2007181994A JP 2007181994 A JP2007181994 A JP 2007181994A JP 5217043 B2 JP5217043 B2 JP 5217043B2
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- chip
- metal post
- solder
- film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81013—Plasma cleaning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Wire Bonding (AREA)
Description
本発明の実施の形態1に係る半導体装置の製造方法について説明する。はじめに、マザーチップの製造工程について、フローチャートおよび工程図に基づいて説明する。まず、図1のステップS1に示すように、所定の半導体素子および回路等が形成されたマザーチップとなるウェハに対して、プローブによる検査が行なわれる。
ここでは、半導体装置におけるドータチップのメタルポストに形成される金膜の形成の仕方と電気的短絡との関係について説明する。
ここでは、ドータチップのメタルポストに形成する金膜(金めっき)の形成の仕方(めっき方法)と電気的短絡との関係について説明する。金めっきの工程を電解めっき法と無電解めっき法とに振り分け、金めっきの工程以外の工程については、実施の形態に2おいて説明した方法と同じ方法で製造したマザーチップとドータチップとを準備した。
ここでは、ドータチップのメタルポストの形状と電気的短絡との関係について説明する。まず、マザーチップのメタルポストとして、以下のようにして製造されたものを準備した。はじめに、電解めっきにより、ピッチ30μm、大きさφ15μm、厚み5μmのニッケル(Ni)めっきからなるメタルポストを形成した。次に、電解めっきにより、大きさφ15μm、厚み5μmのはんだ膜(Sn−3重量%Ag)を形成した。その後、フラックスを塗布した。
ここでは、ドータチップとマザーチップとの接合部分におけるボイドの評価について説明する。まず、マザーチップのメタルポストとして、以下のようにして製造されたものを準備した。はじめに、電解めっきにより、厚み5μmのニッケル(Ni)めっきからなるメタルポストを形成した。次に、電解めっきにより、厚み5μmのはんだ膜(Sn−3重量%Ag)を形成した。その後、フラックスを塗布した。
ここでは、ドータチップをマザーチップに接合したものを、さらに回路基板に接合した半導体装置について説明する。まず、実施の形態1において説明した方法と同様の方法によって、ドータチップ20のメタルポスト26とマザーチップ10のメタルポスト16とをそれぞれ形成した。次に、マザーチップ10のメタルポスト16と、ドータチップ20のメタルポスト26とをはんだ膜17を介して熱圧着し、その後、アンダーフィル34を注入した。
Claims (1)
- 第1半導体基板の主表面に、はんだ膜が表面に露出した複数の第1電極をピッチPをもって形成する工程と、
第2半導体基板の主表面に、金が表面の全体にわたり露出した複数の第2電極を、ピッチP、高さP/6以上P/2以下をもって形成する工程と、
前記第1電極を第1の温度に設定するとともに、前記第2電極を前記第1の温度よりも高い第2の温度に設定し、前記第1電極の表面の前記はんだ膜を溶融して前記はんだ膜と前記金とを接合することにより、前記第1電極と前記第2電極とを接合する工程と
を備え、
前記第2電極を形成する工程では、前記金は電解めっき法によって形成される、半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007181994A JP5217043B2 (ja) | 2007-07-11 | 2007-07-11 | 半導体装置の製造方法 |
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Application Number | Priority Date | Filing Date | Title |
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JP2007181994A JP5217043B2 (ja) | 2007-07-11 | 2007-07-11 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009021329A JP2009021329A (ja) | 2009-01-29 |
JP5217043B2 true JP5217043B2 (ja) | 2013-06-19 |
Family
ID=40360735
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JP2007181994A Expired - Fee Related JP5217043B2 (ja) | 2007-07-11 | 2007-07-11 | 半導体装置の製造方法 |
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JP (1) | JP5217043B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5696367B2 (ja) * | 2010-03-30 | 2015-04-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP5913055B2 (ja) * | 2012-11-09 | 2016-04-27 | 日本特殊陶業株式会社 | 配線基板 |
JP5913063B2 (ja) * | 2012-11-27 | 2016-04-27 | 日本特殊陶業株式会社 | 配線基板 |
KR102190382B1 (ko) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
KR102109042B1 (ko) * | 2013-09-16 | 2020-05-12 | 엘지이노텍 주식회사 | 반도체 패키지 |
EP2849226B1 (en) * | 2013-09-16 | 2018-08-22 | LG Innotek Co., Ltd. | Semiconductor package |
US11024569B2 (en) * | 2017-08-09 | 2021-06-01 | Advanced Semiconducor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
CN116953007A (zh) * | 2023-09-19 | 2023-10-27 | 成都电科星拓科技有限公司 | 一种用于芯片框架开发新产品的成分分析方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08340000A (ja) * | 1995-06-12 | 1996-12-24 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH09283564A (ja) * | 1996-04-16 | 1997-10-31 | Hitachi Ltd | 半導体接合構造 |
JP3723453B2 (ja) * | 2000-09-12 | 2005-12-07 | ローム株式会社 | 半導体装置 |
JP3823318B2 (ja) * | 2003-03-11 | 2006-09-20 | セイコーエプソン株式会社 | 半導体チップの回路基板への実装方法、半導体装置、電子デバイスおよび電子機器 |
JP4742844B2 (ja) * | 2005-12-15 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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