CN104282686B - 宽带隙半导体装置 - Google Patents

宽带隙半导体装置 Download PDF

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CN104282686B
CN104282686B CN201410320367.1A CN201410320367A CN104282686B CN 104282686 B CN104282686 B CN 104282686B CN 201410320367 A CN201410320367 A CN 201410320367A CN 104282686 B CN104282686 B CN 104282686B
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mosfet
band gap
layer
wide band
source
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CN104282686A (zh
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末川英介
鹿口直斗
池上雅明
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Mitsubishi Electric Corp
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Abstract

本发明提供一种宽带隙半导体装置，其能够抑制栅极电极与源极电极之间的静电破坏，而不会增加芯片成本。本发明的宽带隙半导体装置具备：第2源极层(n+源极层(4A))，其在p基极层(3A)的表层夹着场绝缘膜(11)形成，且与n+源极层(4)在同一工序中形成；第2栅极电极(栅极多晶硅(7A))，其至少形成于场绝缘膜(11)上，且与栅极多晶硅(7)为同一层；第3栅极电极(栅极电极(12))，其形成于一侧的第2源极层上，与第2栅极电极电连接；以及第2源极电极(源极电极(9A))，其形成于另一侧的第2源极层上。

Description

宽带隙半导体装置
技术领域
本发明涉及形成逆变器装置等的MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)等宽带隙半导体装置。
背景技术
作为宽带隙半导体装置的一个例子即材料采用了SiC晶片的MOSFET(以下，记作SiC-MOSFET)构成为，在同一芯片内配置有多个个体单元(unit cell)。
此处，通常，宽带隙半导体是指具有约大于或等于2eV的禁带宽度的半导体，已知以GaN为代表的III族氮化物、以ZnO为代表的II族氮化物、以ZnSe为代表的II族硫属化合物以及SiC等。
在SiC-MOSFET中，与采用了Si晶片的MOSFET(以下，记作Si-MOSFET)的情况相比，由于能够降低漏极电极与源极电极之间的正向压降(导通电压)，因此能够减少个体单元数量，能够缩减芯片尺寸(参照专利文献1)。
专利文献1：日本特开2012-54378号公报
如前所述，SiC-MOSFET与Si-MOSFET相比，能够缩减芯片尺寸。然而，另一方面，却存在栅极电极与源极电极之间的电容减小，栅极电极与源极电极之间的耐静电破坏量降低的问题。
在Si-MOSFET中，作为通常的静电破坏对策，大多利用形成个体单元时的源极工序(形成n型扩散层)和P+扩散工序(形成p型扩散层)而在多晶硅(Poly-Si)上形成pn结，并内置齐纳二极管。
在SiC-MOSFET中，为了激活p型杂质以及n型杂质，需要在晶片工艺中实施大于或等于1500℃的热处理，通常，在形成多晶硅的工序之前，实施p型杂质以及n型杂质的离子注入。
因此，存在如下问题：为了将齐纳二极管内置于SiC-MOSFET中，在晶片工艺工序中，需要在与形成个体单元的工序不同的工序中形成pn结，芯片加工费增加而芯片成本提升。
发明内容
本发明就是为了解决如上述的问题而提出的，其目的在于提供一种不会增加芯片成本，而能够抑制栅极电极与源极电极之间的静电破坏的宽带隙半导体装置。
本发明的一个方式所涉及的宽带隙半导体装置的特征在于，具备纵型宽带隙半导体MOSFET以及横型宽带隙半导体MOSFET，该纵型宽带隙半导体MOSFET具备：第2导电型的第1基极层，其形成于第1导电型的宽带隙半导体层的表层；第1导电型的第1源极层，其形成于所述第1基极层的表层；栅极绝缘膜，其形成于夹在所述第1源极层与所述宽带隙半导体层之间的所述第1基极层上；第1栅极电极，其形成于所述栅极绝缘膜上；层间绝缘膜，其形成为将所述第1栅极电极覆盖；第1源极电极，其形成为将所述层间绝缘膜、所述第1基极层以及所述第1源极层覆盖；以及漏极电极，其形成于所述宽带隙半导体层的下方，该横型宽带隙半导体MOSFET具备：第2基极层，其在所述宽带隙半导体层的表层与所述第1基极层在同一工序中形成；场绝缘膜，其形成于所述第2基极层上；第2源极层，其在所述第2基极层的表层夹着所述场绝缘膜形成，且与所述第1源极层在同一工序中形成；第2栅极电极，其至少形成于所述场绝缘膜上，且与所述第1栅极电极为同一层；第3栅极电极，其形成于一侧的所述第2源极层上，与所述第2栅极电极电连接；以及第2源极电极，其形成于另一侧的所述第2源极层上。
发明的效果
根据本发明的上述方式，能够在正的过电压施加于纵型宽带隙半导体MOSFET的栅极电极与源极电极之间时，横型宽带隙半导体MOSFET的沟道开启，使得由于过电压而产生的栅极电流流向横型n沟道MOSFET侧。由此，不会增加芯片成本，而能够抑制SiC-MOSFET的栅极电极与源极电极之间的正侧的静电破坏。
附图说明
图1是实施方式所涉及的宽带隙半导体装置的电路图。
图2是用于说明实施方式所涉及的宽带隙半导体装置的动作的图。
图3是用于说明实施方式所涉及的宽带隙半导体装置的动作的图。
图4是示出实施方式所涉及的宽带隙半导体装置的结构的俯视图。
图5是示出实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。
图6是示出实施方式所涉及的宽带隙半导体装置的结构的俯视图。
图7是示出实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。
图8是示出实施方式所涉及的宽带隙半导体装置的结构的俯视图。
图9是实施方式所涉及的宽带隙半导体装置的电路图。
图10是示出实施方式所涉及的宽带隙半导体装置的结构的俯视图。
图11是用于说明实施方式所涉及的宽带隙半导体装置的制造工序的图。
图12是用于说明实施方式所涉及的宽带隙半导体装置的制造工序的图。
图13是示出实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。
图14是示出图13中的A-A’处的浓度分布的图。
图15是示出实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。
图16是示出图15中的B-B'处的浓度分布的图。
图17是前提技术所涉及的宽带隙半导体装置的电路图。
图18是前提技术所涉及的宽带隙半导体装置的概要剖视图。
标号的说明
1缓冲层；2n－层；3、3A p基极层；4、4A n+源极层；5p+层；6栅极氧化膜；7、7A、7B栅极多晶硅；8、8A层间绝缘膜；9、9A源极电极；9B GND配线；10漏极电极；11场绝缘膜；12栅极电极；13、13A NiSi层；14终端区域保护膜；20凹部；30源极焊盘；31栅极焊盘；32栅极配线；33FLR；34电流检测焊盘。
具体实施方式
下面，参照附图对实施方式进行说明。
在图17及图18中作为前提技术所涉及的宽带隙半导体装置即碳化硅(SiC)半导体装置的一个例子，示出材料采用了SiC晶片的纵型MOSFET(以下，记作SiC-MOSFET)的电路图(参照图17)、以及个体单元(激活区域)的概要剖视图(参照图18)。此外，所使用的半导体材料只要是宽带隙半导体即可，例如可以是GaN等。
如图18所示，材料采用了SiC晶片的MOSFET(以下，记作SiC-MOSFET)，构成为在同一芯片内配置有多个个体单元。
具体而言，作为宽带隙半导体层，在n型的n+缓冲层1上形成有n－层2，在n－层2的表层形成有p型的p基极层3(第1基极层)。
进而，在p基极层3的表层形成有n+源极层4(第1源极层)，至少在夹在n+源极层4与n－层2之间的p基极层3上形成有栅极氧化膜6(栅极绝缘膜)。
另外，在栅极氧化膜6上形成有栅极多晶硅7(第1栅极电极)。该栅极多晶硅7被层间绝缘膜8覆盖。
并且，以将层间绝缘膜8、p基极层3以及n+源极层4覆盖的方式形成有源极电极9。
另一方面，在n+缓冲层1的下方形成有漏极电极10。
此外，在p基极层3上还可以具有被n+源极层4包围的p+层5、以及以覆盖n+源极层4的局部以及p+层5的方式形成的NiSi层13。
与采用了Si晶片的MOSFET(以下，记作Si-MOSFET)的情况相比，在SiC-MOSFET中，由于能够降低漏极电极与源极电极之间的正向压降(导通电压)，因此能够减少个体单元数量，能够缩减芯片尺寸。
然而，另一方面，却存在栅极电极与源极电极之间的电容减小，栅极电极与源极电极之间的耐静电破坏量降低的问题。
作为通常的静电破坏对策，大多利用形成个体单元时的源极工序(形成n型扩散层)与P+扩散工序(形成p型扩散层)而在多晶硅(Poly-Si)上形成pn结，并内置齐纳二极管。
然而，在试图将齐纳二极管内置于SiC-MOSFET中时，为了使p型杂质以及n型杂质激活，需要在晶片工艺中实施大于或等于1500℃的热处理，通常，在形成多晶硅的工序之前，实施p型杂质以及n型杂质的离子注入。
因此，存在如下问题：为了在SiC-MOSFET中内置齐纳二极管，在晶片工艺工序中，需要在与形成个体单元的工序不同的工序中形成pn结，芯片加工费增加，芯片成本提升。
下面说明的实施方式涉及解决上述问题的宽带隙半导体装置。
<第1实施方式>
<结构>
在图1中示出在SiC-MOSFET的栅极电极与源极电极之间内置有横型n沟道MOSFET的宽带隙半导体装置的电路图。
如图1所示，在SiC-MOSFET内置有横型n沟道MOSFET。即，在SiC-MOSFET的栅极电极侧连接有横型n沟道MOSFET的漏极以及栅极电极。
通过以上述方式构成，在正的过电压施加于SiC-MOSFET的栅极电极与源极电极之间时，电流流向横型n沟道MOSFET侧，所以能够抑制SiC-MOSFET的栅极电极与源极电极之间的静电破坏等过电压破坏。
在图2及图3中，示出在SiC-MOSFET的栅极电极与源极电极之间施加有过电压时的横型n沟道MOSFET的动作。
首先，参照图3对横型n沟道MOSFET的构造进行说明。此外，参照与图18所示的构造之间的关联性而对图3所示的构造进行说明。
如图3所示，作为宽带隙半导体层，在n型的n+缓冲层1上形成有n－层2，在n－层2的表层形成有p型的p基极层3A(第2基极层)。该p基极层3A是与p基极层3在同一工序中形成的层。
进而，在p基极层3A上形成有场绝缘膜11。并且，在p基极层3A的表层夹着场绝缘膜11而形成有n+源极层4A(第2源极层)。该n+源极层4A是与n+源极层4在同一工序中形成的层，是通过对栅极氧化膜6以及场绝缘膜11进行局部蚀刻，对露出的p基极层3以及p基极层3A注入n型离子等而形成的。另外，在n+源极层4A上形成有NiSi层13A。
另外，在场绝缘膜11上形成有栅极多晶硅7A(第2栅极电极)。该栅极多晶硅7A与栅极多晶硅7为同一层，与栅极氧化膜6以及场绝缘膜11一同被蚀刻。此处，“同一层”是指在同一工序中形成、且图案连续的层。
另外，该栅极多晶硅7A被层间绝缘膜8A覆盖。该层间绝缘膜8A与层间绝缘膜8为同一层，与栅极氧化膜6以及场绝缘膜11一同被蚀刻。
并且，以将层间绝缘膜8A以及一侧的n+源极层4A覆盖的方形成有栅极电极12(第3栅极电极)。此外，上述栅极多晶硅7A以及层间绝缘膜8A还形成于形成有栅极电极12侧的场绝缘膜11的侧面。
另外，以将层间绝缘膜8A以及另一侧的n+源极层4A局部覆盖的方式形成有源极电极9A(第2源极电极)。
另一方面，在n+缓冲层1的下方形成有漏极电极10。
<效果>
在过电压施加于SiC-MOSFET的栅极电极与源极电极之间时，内置的横型n沟道MOSFET的栅极电极与源极电极之间也被施加电压。从而，在横型n沟道MOSFET中形成n沟道。
由于在横型n沟道MOSFET形成n沟道，因此，由于SiC-MOSFET的栅极电极与源极电极之间的过电压而产生的栅极电流流向横型n沟道MOSFET侧(参照图2及图3中的X1)。因此，能够抑制所述栅极电流流向SiC-MOSFET的栅极电极与源极电极之间，能够防止由于栅极电极与源极电极之间的过电压而造成的破坏。
根据本实施方式，宽带隙半导体装置具备纵型宽带隙半导体MOSFET以及横型宽带隙半导体MOSFET。
纵型宽带隙半导体MOSFET具备：第2导电型的第1基极层(p基极层3)，其形成于第1导电型的宽带隙半导体层表层(n－层2)；第1导电型的第1源极层(n+源极层4)，其形成于p基极层3表层；栅极绝缘膜(栅极氧化膜6)，其形成于夹在n+源极层4与n－层2之间的p基极层3上；第1栅极电极(栅极多晶硅7)，其形成于栅极氧化膜6上；层间绝缘膜8，其形成为将栅极多晶硅7覆盖；源极电极9，其形成为将层间绝缘膜8、p基极层3以及n+源极层4覆盖；以及漏极电极10，其形成于n－层2的下方。
横型宽带隙半导体MOSFET具备：第2基极层(p基极层3A)，其与p基极层3在同一工序中形成于n－层2表层；场绝缘膜11，其形成于p基极层3A上；第2源极层(n+源极层4A)，其在p基极层3A表层夹着场绝缘膜11，与n+源极层4在同一工序中形成；第2栅极电极(栅极多晶硅7A)，其至少形成于场绝缘膜11上、且与栅极多晶硅7为同一层；第3栅极电极(栅极电极12)，其形成于一侧的n+源极层4A上、且与栅极多晶硅7A电连接；以及第2源极电极(源极电极9A)，其形成于另一侧的n+源极层4A上。
根据这种结构，在正的过电压施加于SiC-MOSFET(纵型宽带隙半导体MOSFET)的栅极电极与源极电极之间时，横型n沟道MOSFET(横型宽带隙半导体MOSFET)的沟道开启，由于过电压而产生的栅极电流流向横型n沟道MOSFET侧，由此能够抑制SiC-MOSFET的栅极电极与源极电极之间的正侧的静电破坏。
另外，根据本实施方式，将横型n沟道MOSFET(横型宽带隙半导体MOSFET)中的栅极多晶硅7A与源极电极9A之间的阈值电压设为大于或等于25V。
通常的SiC-MOSFET的栅极电极与源极电极之间的最大额定电压为20V。通过将横型n沟道MOSFET的栅极电极和源极电极之间的阈值电压设为大于或等于25V，从而在栅极电极与源极电极之间的电压小于或等于20V的最大额定电压以内的正常的动作下，横型n沟道MOSFET不会对SiC-MOSFET的动作造成影响。
<第2实施方式>
<结构>
在第1实施方式所示的宽带隙半导体装置中，通过将内置的横型n沟道MOSFET的栅极电极与源极电极之间的阈值电压(以下，记作VGSth)设为大于或等于25V，从而能够防止横型n沟道MOSFET对SiC-MOSFET的正常的动作造成影响。
其原因在于，由于通常的SiC-MOSFET的栅极电极与源极电极之间的最大额定电压为20V，因此，通过将内置的横型n沟道MOSFET的VGSth设为大于或等于25V，从而在栅极电极与源极电极之间的电压小于或等于20V，SiC-MOSFET正常地动作时，横型n沟道MOSFET并不动作。
此外，通过将横型n沟道MOSFET的VGSth设为大于或等于25V，从而使得横型n沟道MOSFET的正向压降(导通电压)也增大，能够利用横型n沟道MOSFET消耗由于栅极过电压而产生的栅极电流。因此，在横型n沟道MOSFET与SiC-MOSFET之间无需追加用于消耗栅极电流的电阻。
<效果>
根据本实施方式，第2源极电极与第1源极电极为同一层。
根据这种结构，通过将内置横型n沟道MOSFET的源极电极与SiC-MOSFET的源极电极连接，从而不需要SiC-MOSFET的终端接合区域的接地(GND)配线，能够抑制芯片的无效区域的增加。因此，不会增加芯片成本，能够内置横型n沟道MOSFET。
<第3实施方式>
<结构>
图4是示出本实施方式所涉及的宽带隙半导体装置的结构的俯视图，另外，图5是示出本实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。
在本实施方式中，示出内置的横型n沟道MOSFET的源极电极与在SiC-MOSFET的终端区域形成的接地(以下，记作GND)配线9B连接的情况。
如图4所示，以将形成多个个体单元的激活区域包围的方式形成有栅极配线32、GND配线9B以及场限环(以下，记作FLR)33。另外，以覆盖激活区域的方式配置源极焊盘30，并沿栅极配线32配置有栅极焊盘31。
内置于SiC-MOSFET的横型n沟道MOSFET配置于激活区域与终端区域的边界。
图5是示出图4中的A-A'剖面的图。
在图5中，作为横型n沟道MOSFET的源极电极而使用了终端区域的GND配线9B。该GND配线9B以及横型n沟道MOSFET被终端区域保护膜14覆盖。
在过电压施加于SiC-MOSFET的栅极电极与源极电极之间时，对内置的横型n沟道MOSFET的栅极电极与源极电极之间也会施加电压。由此，在横型n沟道MOSFET中形成n沟道。
由于在横型n沟道MOSFET中形成n沟道，因此，由于SiC-MOSFET的栅极电极与源极电极之间的过电压而产生的栅极电流流向横型n沟道MOSFET侧(参照图5中的X2)。
通过将内置的横型n沟道MOSFET的源极电极设为SiC-MOSFET的终端区域的GND配线9B，从而不会对SiC-MOSFET的激活动作(个体单元动作)造成影响，能够将过电压施加于栅极电极与源极电极之间时所产生的栅极电流向GND配线释放。
<效果>
根据本实施方式，第2源极电极是以将纵型宽带隙半导体MOSFET包围的方式形成的终端区域的接地配线。
根据这种结构，通过将内置横型n沟道MOSFET的源极电极与SiC-MOSFET的终端接合区域的接地(GND)配线连接，从而不会对SiC-MOSFET的激活区域的动作造成影响，能够将由于过电压施加于SiC-MOSFET的栅极电极与源极电极之间而产生的栅极电流向接地(GND)配线释放。
<第4实施方式>
<结构>
图6是示出本实施方式所涉及的宽带隙半导体装置的结构的俯视图，另外，图7是示出本实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。
在本实施方式中，示出了内置的横型n沟道MOSFET的源极电极与SiC-MOSFET的源极电极为同一层的情况。
如图6所示，以将形成多个个体单元的激活区域包围的方式形成有栅极配线32以及FLR33。另外，以将激活区域覆盖的方式配置有源极焊盘30，并沿栅极配线32而配置有栅极焊盘31。
内置于SiC-MOSFET中的横型n沟道MOSFET配置于激活区域与终端区域的边界。
图7是示出了图6中的A-A’剖面的图。
在图7中，横型n沟道MOSFET的源极电极为SiC-MOSFET的源极电极9。
并且，以将一侧的n+源极层4A(图5的相反侧)覆盖的方式形成有栅极电极12。此外，上述的栅极多晶硅7B也形成于形成有栅极电极12的那一侧的场绝缘膜11的侧面。
另外，以将层间绝缘膜8A以及另一侧的n+源极层4A局部覆盖的方式形成有源极电极9。横型n沟道MOSFET的栅极多晶硅7B并未被层间绝缘膜8A覆盖。另外，横型n沟道MOSFET被终端区域保护膜14覆盖。
在过电压施加于SiC-MOSFET的栅极电极与源极电极之间时，内置的横型n沟道MOSFET的栅极电极与源极电极之间也被施加电压。由此，在横型n沟道MOSFET中形成n沟道。
由于在横型n沟道MOSFET形成n沟道，因此，由于SiC-MOSFET的栅极电极与源极电极之间的过电压而产生的栅极电流流向横型n沟道MOSFET侧(参照图7中的X3)。
<效果>
通过将内置的横型n沟道MOSFET的源极电极设为SiC-MOSFET的源极电极，从而无需重新形成横型n沟道MOSFET的源极电极，能够抑制SiC-MOSFET芯片的无效区域的增加。通过抑制无效区域的增加，从而不会增加芯片面积，能够内置横型n沟道MOSFET，能够抑制芯片成本的增加。
<第5实施方式>
<结构>
图8是示出本实施方式所涉及的宽带隙半导体装置的结构的俯视图。
在本实施方式中，示出了内置的横型n沟道MOSFET配置于SiC-MOSFET的栅极电极的导线接合焊盘区域内的情况。
如图8所示，以将形成多个个体单元的激活区域包围的方式形成有栅极配线32以及FLR33。另外，以将激活区域覆盖的方式而配置有源极焊盘30，并沿栅极配线32而配置有栅极焊盘31。
内置于SiC-MOSFET中的横型n沟道MOSFET配置于激活区域与终端区域的边界、且配置于栅极焊盘31内。
<效果>
这样，通过配置于SiC-MOSFET的栅极电极的导线接合焊盘区域内，从而不会增加SiC-MOSFET芯片的无效区域，能够内置横型n沟道MOSFET，能够抑制芯片成本的增加。另外，能够防止芯片的无效面积的增加。
<第6实施方式>
<结构>
图9中示出了将横型n沟道MOSFET内置于电流检测MOSFET的栅极电极与源极电极之间的宽带隙半导体装置的电路图。此外，该电流检测MOSFET是内置于SiC-MOSFET中的MOSFET。
电流检测元件内置于在Intelligent Power Module(智能功率模块；以下，记作IPM)等中使用的IGBT芯片、MOSFET芯片等中，用于在过电流流过芯片时的保护以及检测。
通常，在作为电流检测元件的MOSFET中，激活区域的面积设为能够流动在IGBT芯片或MOSFET芯片等的激活区域中流动的电流的1万分之1左右的电流，由于电流检测元件的激活区域面积较小，栅极电极与源极电极之间的电容较小，因此，栅极电极与源极电极之间的耐静电破坏量较低。
如图9所示，在电流检测MOSFET中内置有横型n沟道MOSFET。即，电流检测MOSFET的栅极电极侧连接有横型n沟道MOSFET的漏极以及栅极电极。
<效果>
通过以该方式构成，在正的过电压施加于电流检测MOSFET的栅极电极与源极电极之间时，电流流向横型n沟道MOSFET侧，因此能够抑制电流检测MOSFET的栅极电极与源极电极之间的静电破坏等过电压破坏。另外，能够防止芯片的无效面积的增加。
<第7实施方式>
<结构>
在第6实施方式所示的宽带隙半导体装置中，通过将内置的横型n沟道MOSFET的栅极电极与源极电极之间的阈值电压(VGSth)设为大于或等于25V，从而能够防止横型n沟道MOSFET对电流检测MOSFET的正常动作造成影响。
其原因在于，由于通常的电流检测MOSFET的栅极电极与源极电极之间的最大额定电压为20V，因此，通过将内置的横型n沟道MOSFET的VGSth设为大于或等于25V，从而在栅极电极与源极电极之间的电压小于或等于20V，电流检测MOSFET正常动作时，横型n沟道MOSFET不进行动作。
此外，通过将横型n沟道MOSFET的VGSth设为大于或等于25V，从而横型n沟道MOSFET的正向压降(导通电压)也增大，能够利用横型n沟道MOSFET消耗由于栅极过电压而产生的栅极电流。因此，无需在横型n沟道MOSFET与电流检测MOSFET之间追加消耗栅极电流的电阻。
<第8实施方式>
<结构>
图10是示出本实施方式所涉及的宽带隙半导体装置的结构的俯视图。
在本实施方式中，示出内置的横型n沟道MOSFET配置于电流检测MOSFET的导线接合焊盘区域内的情况。
如图10所示，以将形成多个个体单元的激活区域包围的方式形成有栅极配线32以及FLR33。另外，以将激活区域覆盖的方式配置有源极焊盘30，并沿栅极配线32而配置有栅极焊盘31以及电流检测焊盘34。
内置于电流检测MOSFET中的横型n沟道MOSFET配置于电流检测焊盘34内。
<效果>
这样，通过配置于电流检测MOSFET的导线接合焊盘区域内，从而不会增加SiC-MOSFET芯片的无效区域，能够内置横型n沟道MOSFET，能够抑制芯片成本的增加。
<第9实施方式>
<结构>
图11及图12示出在第2实施方式以及第7实施方式中，在SiC-MOSFET的场氧化工序中同时形成了内置的横型n沟道MOSFET的场绝缘膜11的情况。
通常，SiC-MOSFET周边区域中的在场氧化工序中形成的氧化膜，与激活区域(个体单元)中的栅极氧化膜6相比，膜厚较厚。通过将在场氧化工序中形成的该氧化膜用作横型n沟道MOSFET的栅极绝缘膜，从而无需增加工序便能够形成横型n沟道MOSFET的栅极绝缘膜。另外，由于该氧化膜的膜厚较厚，因此能够使横型n沟道MOSFET的VGSth高于SiC-MOSFET的VGSth。
因此，不会增加芯片成本，能够内置不对SiC-MOSFET的正常动作造成影响的横型n沟道MOSFET。
<效果>
根据本实施方式，场绝缘膜11在包围纵型宽带隙半导体MOSFET的周边区域的形成工序中形成。
通常，SiC-MOSFET的在场氧化工序中形成的氧化膜与SiC-MOSFET的激活区域的栅极氧化膜相比较厚。通过将场氧化工序的氧化膜用作横型n沟道MOSFET的栅极氧化膜，从而无需增加工序便能够使横型n沟道MOSFET的栅极电极与源极电极之间的阈值电压高于SiC-MOSFET的激活区域的栅极电极与源极电极之间的阈值电压。
<第10实施方式>
<结构>
在本实施方式中，示出在第2实施方式及第7实施方式中，对宽带隙半导体层的表层进行蚀刻而形成凹部20，在该凹部20内形成有横型n沟道MOSFET的n+源极层4A的情况。
图13及图15是示出本实施方式所涉及的宽带隙半导体装置的结构的概要剖视图。图14是示出图13中的A-A’处的浓度分布的图，图16是示出图15中的B-B'处的浓度分布的图。在图14及图16中，纵轴表示各层的杂质浓度，横轴表示在将图13及图15中的横向设为X轴的情况下的X轴方向上的位置。
如图14及图16所示，通常，p基极层的浓度是从n－层2的表层进入得越深的部分，p型浓度越高。由此，通过对n－层2表层进行蚀刻而形成凹部20，在凹部20内形成横型n沟道MOSFET的n+源极层4A，从而能够在与SiC-MOSFET的激活区域相比p型浓度更高的区域，形成横型n沟道MOSFET的n沟道。
因此，在横型n沟道MOSFET中，即使不增厚栅极绝缘膜，也能够获得比SiC-MOSFET的激活区域(个体单元)高的VGSth。
因此，能够内置即使在栅极电极与源极电极之间的最大额定电压为小于或等于20V的正常动作中，也不会对SiC-MOSFET的正常动作造成影响的横型n沟道MOSFET。
<效果>
根据本实施方式，宽带隙半导体装置具备在p基极层3A(第2基极层)的表层形成的凹部20。并且，n+源极层4A形成于凹部20内。
通常，SiC-MOSFET的p基极层浓度是，自SiC最表面层越深的部分的p层浓度越高。因此，通过对SiC表面进行蚀刻而形成凹部20，形成n+源极层4A位于凹部20内的横型n沟道MOSFET，由此能够在与SiC-MOSFET的激活区域相比p层浓度更高的区域中形成沟道。
因此，无需增厚横型n沟道MOSFET的栅极氧化膜便能够获得与SiC-MOSFET的激活区域相比更高的栅极电极与源极电极之间的阈值电压。因此，在栅极电极与源极电极之间的最大额定电压小于或等于20V的正常动作中，横型n沟道MOSFET不会对SiC-MOSFET的激活区域、电流检测元件的动作造成影响。
虽然在上述实施方式中还记载有各构成要素的材质、材料、实施条件等，但是这些仅为示例，并不限于记载的内容。
此外，本发明能够在其发明的范围内，对各实施方式进行自由组合或对各实施方式的任意构成要素进行变形，或者在各实施方式中省略任意的构成要素。

Claims (10)

1.一种宽带隙半导体装置，其特征在于，具备纵型宽带隙半导体MOSFET以及横型宽带隙半导体MOSFET，
该纵型宽带隙半导体MOSFET具备：
第2导电型的第1基极层，其形成于第1导电型的宽带隙半导体层的表层；
第1导电型的第1源极层，其形成于所述第1基极层的表层；
栅极绝缘膜，其形成于夹在所述第1源极层与所述宽带隙半导体层之间的所述第1基极层上；
第1栅极电极，其形成于所述栅极绝缘膜上；
层间绝缘膜，其形成为将所述第1栅极电极覆盖；
第1源极电极，其形成为将所述层间绝缘膜、所述第1基极层以及所述第1源极层覆盖；以及
漏极电极，其形成于所述宽带隙半导体层的下方，
该横型宽带隙半导体MOSFET具备：
第2基极层，其在所述宽带隙半导体层的表层与所述第1基极层在同一工序中形成；
场绝缘膜，其形成于所述第2基极层上；
第2源极层，其在所述第2基极层的表层夹着所述场绝缘膜形成，且与所述第1源极层在同一工序中形成；
第2栅极电极，其至少形成于所述场绝缘膜上，且与所述第1栅极电极为同一层；
第3栅极电极，其形成于一侧的所述第2源极层上，与所述第2栅极电极电连接；以及
第2源极电极，其形成于另一侧的所述第2源极层上，
同一层是指在同一工序中形成、且图案连续的层。
2.根据权利要求1所述的宽带隙半导体装置，其特征在于，
所述第2源极电极与所述第1源极电极为同一层。
3.根据权利要求1所述的宽带隙半导体装置，其特征在于，
所述第2源极电极是以包围所述纵型宽带隙半导体MOSFET的方式形成的终端区域的接地配线。
4.根据权利要求1至3中任一项所述的宽带隙半导体装置，其特征在于，
在所述横型宽带隙半导体MOSFET中所述第2栅极电极与所述第2源极电极之间的阈值电压设为大于或等于25V。
5.根据权利要求1至3中任一项所述的宽带隙半导体装置，其特征在于，
所述场绝缘膜在将所述纵型宽带隙半导体MOSFET包围的周边区域的形成工序中形成。
6.根据权利要求1至3中任一项所述的宽带隙半导体装置，其特征在于，
所述纵型宽带隙半导体MOSFET是电流检测MOSFET。
7.根据权利要求1至3中任一项所述的宽带隙半导体装置，其特征在于，
所述横型宽带隙半导体MOSFET配置于所述纵型宽带隙半导体MOSFET的栅极焊盘区域内。
8.根据权利要求6所述的宽带隙半导体装置，其特征在于，
所述横型宽带隙半导体MOSFET配置于所述纵型宽带隙半导体MOSFET的电流检测焊盘区域内。
9.根据权利要求1至3中任一项所述的宽带隙半导体装置，其特征在于，
还具备在所述第2基极层的表层形成的凹部，
所述第2源极层形成于所述凹部内。
10.根据权利要求1至3中任一项所述的宽带隙半导体装置，其特征在于，
所述宽带隙半导体是SiC或GaN。
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