CN104157631A - 具有嵌入在封装中的硅通孔（tsv）管芯的多芯片集成 - Google Patents

具有嵌入在封装中的硅通孔（tsv）管芯的多芯片集成 Download PDF

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Publication number
CN104157631A
CN104157631A CN201410199136.XA CN201410199136A CN104157631A CN 104157631 A CN104157631 A CN 104157631A CN 201410199136 A CN201410199136 A CN 201410199136A CN 104157631 A CN104157631 A CN 104157631A
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Prior art keywords
tube core
tsv
adhesive layer
route characteristics
coupled
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CN201410199136.XA
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Inventor
D·A·劳瑞恩
李永刚
R·N·马内帕利
J·索托冈萨雷斯
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Intel Corp
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Intel Corp
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Publication of CN104157631A publication Critical patent/CN104157631A/zh
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Abstract

本公开的实施例涉及具有多个管芯的三维(3D)集成的集成电路(IC)封装组件，以及对应的制造方法和包含这种3D IC封装组件的系统。可在诸如微处理器管芯的第一管芯上形成无凸块建立层(BBUL)封装衬底。激光辐射可用于在管芯背面薄膜中形成开口以暴露第一管芯的背侧上的TSV焊盘。诸如存储器管芯堆叠的第二管芯可通过在对应的第一和第二管芯的TSV之间形成的管芯互连耦合至第一管芯。可施加底部填充材料以填充第一和第二管芯之间的任何剩余间隙中的一些或所有，和/或可密封剂施加于第二管芯和/或封装衬底上。可描述和/或要求保护其它的实施例。

Description

具有嵌入在封装中的硅通孔(TSV)管芯的多芯片集成
技术领域
本公开的实施例一般涉及集成电路的领域，并且更具体地涉及用于实现具有多个管芯的三维(3D)集成的集成电路(IC)封装组件的技术和配置。 
背景技术
当形状因数不断缩小时，消费者对移动设备中更快的处理速度和增加的存储容量的需求持续上升。近来，IC行业已开始实施利用层叠封装(PoP)或采用硅通孔(TSV)的直接管芯到管芯互连的倒装芯片封装和外围器件的三维(3D)集成。然而，目前可利用的技术不提供使用更薄的封装衬底，诸如，3D集成方案中的无凸块建立层。 
附图简述 
通过结合附图的以下详细描述将容易理解多个实施例。为了便于该描述，相同的附图标记指示相同结构的元件。在附图的多个图中通过示例而非作为限制地说明多个实施例。 
图1a-1c示出了根据多个实施例的示例集成电路(IC)封装组件及其部分的截面侧视示意图。 
图2示意性地示出了根据一些实施例的用于制造IC封装组件的方法的流程图。 
图3a-3g示意性地示出了根据多个实施例的IC封装组件制造的多个阶段。 
图4示意性地示出了根据一些实施例的用于制造IC封装组件的方法的流程图。 
图5a-5g示意性地示出了根据多个实施例的IC封装组件制造的多个阶段。 
图6a-6f示意性地示出了根据多个实施例的IC封装组件制造的多个阶段。 
图7示意性地示出根据多个实施例的计算设备。 
详细描述 
本公开的实施例描述了用于IC封装组件中的3D多芯片集成的技术和配置。在以下描述中，将使用本领域技术人员所通常使用的术语来描述示例性实现的各个方面，以向其他本领域技术人员传达它们的工作的实质。然而，对本领域技术人员将显而易见的是，仅采用所描述方面中的一些也可实施本公开。为了说明的目的，陈述具体的数字、材料和配置以提供对示例性实现的全面理解。然而，本领域技术人员将可理解，没有这些特定细节也可实施本公开的实施例。在其他实例中，省略或简化已知特征以不模糊示例性实现。 
在以下详细描述中，参照形成本说明书的一部分的附图，其中在全部附图中相同的标记指示相同的部件，并且在附图中以可实施本公开的主题的示例实施例的方式显示。将理解，可利用其它实施例，且可做出结构上或逻辑上的改变，而不偏离本公开的范围。因此，以下详细描述不应按照限制性意义来理解，且多个实施例的范围由所附权利要求及其等价方案来限定。 
为了本公开的目的，短语“A和/或B”表示(A)、(B)或(A和B)。为了本公开的目的，短语“A、B和/或C”表示(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。 
说明书可使用基于视角的描述，诸如顶部/底部、内/外、上/下等等。这种描述仅用于便于讨论并且不旨在将本文所描述的实施例的应用限制在任何特定方向。 
说明书可使用短语“在实施例中”或“在多个实施例中”，它们均可 表示相同或不同实施例中的一个或多个。此外，有关本公开的多个实施例使用的术语“包括”、“包含”、“具有”等等是同义的。 
本文可使用术语“与……耦合”及其派生词。“耦合”可表示以下一个或多个。“耦合”可表示两个或多个元件直接物理或电气接触。然而，“耦合”还可表示两个或多个元件彼此间接接触，但仍彼此协作或交互，以及可表示一个或多个其他元件被耦合或连接在所述将彼此耦合的元件之间。术语”直接耦合”可表示两个或多个元件直接接触。 
在各个实施例中，短语“在第二特征上形成、沉积或以其他方式设置第一特征”，可表示第一特征被形成、沉积、或设置在第二特征之上，并且第一特征的至少一部分可与第二特征的至少一部分直接接触(例如，直接物理和/或电接触)或间接接触(在第一特征和第二特征之间具有一个或多个其他特征)。 
为了便于参考，用三位数字标记在附图中所示的IC封装组件部件，其中第一位数字对应于图号(例如，图1a-1c的特征被标记为“1XX”)而第二和第三位数字识别部件。因此，虽然可参照特定附图(例如，图1a-1c的第一管芯102a)描述IC封装组件部分，但描述应当被理解为同样地应用于其他附图的对应部件。例如，图3a-3g的第一管芯302a、图5a-5g的第一管芯502、图6a-6f的第一管芯602a以及图7的第一管芯702a可具有针对图1a-1c的第一管芯102a描述的任何或所有特征/配置。 
如本文所使用的，短语“硅通孔”或“TSV”可用于提及至少部分地通过管芯或其他半导体衬底/器件(诸如，插入器)延伸的导电通孔。即使当半导体材料由不是硅的材料组成时，短语“硅通孔”或“TSV”也可用于此类导电特征。 
在本文中所描述的实施例提供三维(3D)集成电路(IC)封装组件配置和对应的制造技术。在多个实施例中，IC封装组件可包括嵌入在封装衬底中的第一管芯、与第一管芯耦合的第二管芯以及设置在第一和第二管芯之间的粘合层。第一管芯可以是诸如具有一个或多个TSV的微处理器/CPU，以及封装衬底可以是无凸块建立层(BBUL)封装衬底。在一些实 施例中，封装衬底可以是无芯衬底。在多个实施例中，第二管芯可以是具有通过TSV耦合的多个存储器管芯的存储器管芯堆叠，以及粘合层可以是管芯背面薄膜(DBF)层。在多个实施例中，可在粘合层中形成开口。在第一管芯上的TSV焊盘和在第二管芯上的TSV焊盘可定位在开口的相对侧并且与管芯互连耦合以形成导电路径。在一些实施例中，可将密封剂施加于第二管芯之上，和/或底部填充材料可用于填充粘合层中的开口或粘合层和第二管芯之间的其他剩余空间。 
在一些实施例中，可在第一管芯上形成封装衬底之前在粘合层中形成开口。在其他实施例中，可在形成封装衬底之后在粘合层中形成开口。在多个实施例中，可通过采用激光图案化投影(LPP)工具选择性地将粘合层的一部分暴露至激光能量来形成开口。在其他实施例中，可通过用激光扫描系统(例如，电扫描器(galvano scanner))扫描粘合层或粘合层的一部分应用激光能量。在多个实施例中，激光可以是UV激光。 
图1a-1c示出了根据多个实施例的集成电路(IC)封装组件100的示意截面侧视图。首先参照图1a，IC封装组件100可包括嵌入在封装衬底104中的第一管芯102a、与第一管芯102a耦合的第二管芯102b、以及与封装衬底104耦合的电路板122。在一些实施例中，第二管芯102b可包括以堆叠的三维(3D)配置(例如，图1b的管芯140)排列的多个管芯。在多个实施例中，第二管芯102b可包括一个或多个存储器管芯。 
在多个实施例中，第二管芯102b可嵌入在密封剂108中。密封剂108可以是任何合适的材料，诸如(但不限于)味之素(Ajinomoto)建立薄膜(ABF)衬底或其他建立薄膜、其他介电/有机材料、树脂、环氧树脂，聚合物粘合剂、硅树脂、丙烯酸树脂、聚酰亚胺、氰酸酯、热塑性塑料和/或热固性材料。 
在一些实施例中，第一管芯102a和第二管芯102b可以是单片(singulated)管芯。在其他实施例中，第一管芯102a和/或第二管芯102b可包括以堆叠排列的两个或多个管芯。在其他实施例中，第一管芯102a和/或第二管芯102b可以是具有形成于其上的两个或多个管芯的晶片(或晶片 的一部分)。 
在多个实施例中，第一管芯102a和/或第二管芯102b可以是主逻辑管芯。在其他实施例中，第一管芯102a和/或第二管芯102b可被配置成用作存储器、专用电路(ASIC)、处理器或它们的一些组合。在一些实施例中，第一管芯102a可以是CPU/处理器，以及第二管芯102b可以是一个或多个存储器管芯。 
在一些实施例中，接口层124可设置在第一管芯102a和第二管芯102b之间。 
接口层124可以是、或可包括底部填充、粘合、介电、或其他材料的层。接口层124可提供多种功能，诸如提供机械强度、导电性、散热或粘附。 
在一些实施例中，封装衬底104可以是无芯衬底。例如，封装衬底104可以是无凸块建立层(BBUL)组件，该无凸块建立层组件包括多个“无凸块的”建立层。如本文中所使用的，“无凸块建立层”可指的是在不使用焊料或可被认为是“凸块”的其他附连装置的情况下嵌入在其中的衬底和部件的层。在多个实施例中，本文所描述的一个或多个建立层可具有可针对可靠性、减少翘曲等等而被改变和/或优化的材料性质。在其他实施例中，封装衬底104可由聚合物、陶瓷、玻璃或半导体材料组成。在一些实施例中，封装衬底104可以是传统的有芯衬底和/或插入器。 
第一管芯102a可耦合至封装衬底104的第一侧。在多个实施例中，第一管芯102a可嵌入到封装衬底104中。封装衬底104的相对的第二侧可通过封装互连112耦合至电路板122。封装互连112可将设置在封装衬底104的第二侧上的电路由特征110耦合至在电路板122上的对应的电路由特征116。封装衬底104可具有导电特征134(诸如，迹线、沟槽和/或通孔)，导电特征134形成于封装衬底104中，以在第一/第二管芯102a/102b和电路板122和/或IC封装组件100外部的其它电气部件之间路由电信号。封装互连112可包括多种合适的结构和/或材料中的任一种，例如，合适的结构和/或材料包括使用金属、合金、可焊接材料、或它们的组合形成的凸块、 柱或球。在多个实施例中，电路由特征110可以球栅阵列(BGA)或其他配置排列。 
在一些实施例中，电路板122可以为由电绝缘材料(诸如环氧层叠)组成的印刷电路板(PCB)。例如，电路板122可包括由利用环氧树脂预浸材料层压在一起的材料(诸如聚四氟乙烯、酚醛棉纸材料(诸如阻燃剂4(FR-4)、FR-1、棉纸)和环氧树脂的材料(诸如CEM-1或CEM-3)、或编织的玻璃材料)组成的电绝缘层。在其他实施例中，电路板122可由其他合适的材料组成。 
电路板122的一些部分/特征可能不在图1a中描绘。在多个实施例中，电路板122可包括耦合至电路板的其他电器件，该电路板被配置成将电信号通过电路板122路由至第一/第二管芯102a/102b或将来自第一/第二管芯102a/102b的电信号路由通过电路板122。在一些实施例中，电路板122可包括在其上形成的结构(诸如，迹线、沟槽、和/或通孔)，以将电信号路由通过电路板122。在一些实施例中，电路板122可以为主板(例如，图7的主板722)。 
图1b描绘了根据多个实施例的IC封装组件100的管芯部分的截面侧视示意图。如所示的，第一管芯102a可具有第一侧S1和与第一侧S1相对的第二侧S2。第一侧S1可以是一般被称为管芯的“有源”或“顶”或“正”侧的管芯的侧面。第一侧S1可包括一个或多个晶体管。第二侧S2可以是一般被称为管芯的“无源”或“底”或“背”侧的管芯的侧面。 
第一侧S1可包括具有在其上形成的一个或多个晶体管的有源层114。一个或多个晶体管可位于第一侧S1的外部表面之下并且通过一系列金属和氧化物层路由至第一侧S1的外表面。第二侧S2可包括由半导体材料构成的半导体衬底118。半导体衬底118可由n型或p型材料体系构成并且可包括例如使用体硅或绝缘体上硅子结构(substructure)形成的结晶衬底。在一些实施例中，半导体衬底118可使用替换材料形成，该替换材料可以与或可以不与硅结合，该替换材料包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。其他II-VI、III-V族或IV族材料体系还可 用于形成根据多个实施例的半导体衬底118。 
在多个实施例中，第一管芯102a可包括至少部分地穿过半导体衬底118形成的一个或多个硅通孔(TSV)126。第一管芯102a的第一侧S1可包括电路由特征106。在一些实施例中，电路由特征106可以是接合焊盘。第二侧S2还可包括一个或多个电路由特征128。在一些实施例中，电路由特征128可以是耦合至对应的TSV126的TSV焊盘。TSV126可配置成在第一侧S1上的有源层114和在管芯102a的第二侧S2上的电路由特征128之间路由电信号。 
在一些实施例中，第二管芯102b可包括多个管芯140和穿过管芯140中的一些或所有设置的一个或多个TSV136。在多个实施例中，可将电路由特征138设置在第二管芯102b的管芯140中的一个或多个上。电路由特征138中的一个或多个可与对应的TSV136电耦合。可使用包括互连结构(例如，焊盘、凸起、柱、可焊接材料或它们的组合)的任何合适的技术将管芯140耦合在一起。也就是说，TSV136可能不由一些实施例中所描述的单个、连续的材料结构构成。 
电路由特征128/138可以是导电焊盘、凸起、柱或其他此类结构。在多个实施例中，电路由特征128/138可具有金属的一个或多个层，该金属包括但不限于单独的或以任何组合的镍、钯、铂、锡、银、金、铜或其他金属。在一些实施例中，电路由特征128可具有一个或多个铜层。在其他实施例中，电路由特征138可具有外部的金表面。 
第二管芯102b的电路由特征138可通过管芯互连120与第一管芯102a的电路由特征128耦合。在多个实施例中，可使用可焊接材料(例如，焊膏、焊球)形成管芯互连120。在一些实施例中，第一管芯102a的第一TSV126可通过对应的电路由特征128/138和管芯互连120与第二管芯102b的第二TSV136耦合，以形成至少部分地穿过第一管芯102a和第二管芯102b延伸的导电路径142。导电路径142可在第二管芯102b和第一管芯102a之间路由电信号。在一些实施例中，例如，电信号可包括与第一管芯102a/第二管芯102b的操作相关联的输入/输出(I/O)信号和/或功率或接地信号。 
例如，如图1b所示，第二管芯102b可按从前到后的配置耦合至第一管芯102a(例如，第二管芯102b的“前”或“有源”侧耦合至第一管芯102a的“后”或“无源”侧S1)。在其他实施例中，第一和第二管芯102a/102b可按背对背排列彼此耦合。在多个实施例中，一个或多个附加的管芯可与第一管芯102a、第二管芯102b和/或封装衬底104耦合。 
在一些实施例中，粘合层130可设置在第一管芯102a的第二侧S2上。粘合层130可包括聚合物基质。用于粘合层130的合适的材料的示例可包括，但不限于，环氧树脂、丙烯酸、聚酰亚胺、环氧树脂-丙烯酸酯、其他聚合物材料和它们的组合。在多个实施例中，粘合层130可以是管芯背面薄膜(DBF)。 
在一些实施例中，粘合层130可包括开口132，并且电路由特征128和/或管芯互连120中的一个或多个可定位在开口132内。在一些实施例中，开口132可对应于整个粘合层130。例如，在一些IC封装组件中，形成开口132可包括移除整个粘合层130。 
例如，如图1a－1b所示，可通过将底部填充材料或其他合适的材料添加至开口132和/或粘合层130和第二管芯102b之间在第一管芯102a和第二管芯102b之间形成接口层124。接口层124和粘合层130中的一个或两个可给予机械强度/对IC封装组件100的翘曲抵抗。此外，一些实施例可能没有粘合层130和开口132。例如，在一些实施例中，粘合层130可在IC封装组件制造的一个阶段被应用至第一管芯102a，并且随后在制造完成之前被移除。 
诸如电路由特征128/138和管芯互连120的特征的空间/间距可在多个实施例中间变化。在一些实施例中，相邻的电路由特征128和/或相邻的电路由特征138之间的距离可在30-80μm、40-100μm、小于40μm、或大于100μm的范围内。 
现参照图1c，诸如电路由特征128/138、粘合层130和管芯互连120的特征的尺寸可在多个实施例中间变化。 
在多个实施例中，粘合层130可具有小于10μm的厚度(箭头A)。 在其他实施例中，粘合层130可具有在0.1-20μm、0.1-9.9μm、1-9.9μm或5-9.9μm范围内的厚度(箭头A)。 
在多个实施例中，电路由特征128可具有20μm的宽度(箭头B)和3μm的高度/厚度(箭头C)。在其他实施例中，电路由特征128可具有在5-40μm、10-30μm或15-25μm范围内的宽度(箭头B)，和在0.5-15μm、1-10μm或2-5μm范围内的高度/厚度(箭头C)。 
在多个实施例中，电路由特征138可具有20μm的宽度(箭头D)和10μm的高度/厚度(箭头E)。在其他实施例中，电路由特征138可具有在5-40μm、10-30μm或15-25μm范围内的宽度(箭头D)，和在1-20μm、5-15μm或8-12μm范围内的高度/厚度(箭头E)。 
在多个实施例中，管芯互连120可具有10μm的高度/厚度(箭头F)。在其他实施例中，管芯互连120可具有在1-20μm、5-15μm或8-12μm范围的高度/厚度(箭头F)。 
在特定的实施例中，粘合层130可具有小于10μm的厚度(箭头A)，电路由特征128可具有20μm的宽度(箭头B)和3μm的高度/厚度(箭头C)，电路由特征138可具有20μm的宽度(箭头D)和10μm的高度/厚度(箭头E)，以及管芯互连120可具有10μm的高度/厚度(箭头F)。 
在多个实施例中，粘合层130可施加至第一管芯102a的第二侧S2并且随后与牺牲面板(panel)耦合。然后封装衬底(例如，封装衬底104)可在第一管芯102a的第一侧S1上形成，或与第一管芯102a的第一侧S1耦合，并且然后可移除牺牲面板。在一些实施例中，在建立过程期间粘合层130可覆盖电路由特征128，并且可穿过粘合层130形成开口132以在移除牺牲面板之后暴露电路由特征128。在其他实施例中，可在将粘合层130施加至第一管芯102a之前在粘合层130中形成开口132，并且粘合层130可定位在第二侧S2上，使得电路由特征138中的一个或多个在开口132内。在此类实施例中，可通过在建立过程之后移除牺牲面板来暴露电路由特征128。在任何情况下，在电路由特征138已被暴露之后，第二管芯102b可与第一管芯102a耦合。 
在其他实施例中，粘合层130可与牺牲面板耦合，并且可在将第一管芯102a与粘合层130耦合之前在粘合层130中形成开口132。可在粘合层130与牺牲面板耦合之前或之后在粘合层130中形成开口132。然后，可通过将第二侧S2定位在粘合层130上使第一管芯102a与粘合层130耦合，使得电路由特征128的一个或多个设置在开口132内。然后，封装衬底104可在第一管芯102a的第一侧S1上形成，或者与第一管芯102a的第一侧S1耦合。接着可移除牺牲面板以暴露电路由特征128。在其他实施例中，在建立过程期间粘合层130可覆盖电路由特征128，并且可在形成建立层和移除牺牲面板之后在粘合层130中形成开口132。在任何情况下，如以下更充分描述的，可通过将粘合层130暴露至辐射能量来形成开口132。 
图2和4示意性地示出了根据一些实施例的制造IC封装组件的方法的流程图。图3a－3g描绘了对应于图2中所示的方法的制造的多个阶段。图5a－5f和图6a－6f描绘了对应于图4所示的方法的制造的多个阶段。 
虽然为了易于参考一些图仅示出在牺牲面板的一侧上的制造过程，然而应当理解，本文中所描述的方法中任一个可在相同牺牲面板的相对侧和/或沿着牺牲面板的相同侧的多个部分上执行。 
首先参照图2，方法200可在框201处通过提供第一管芯开始，该第一管芯具有第一侧、第二侧和第一TSV(例如，TSV126)，第一侧具有一个或多个晶体管，第二侧具有电路由特征(例如，电路由特值128)，第一TSV(例如，TSV126)耦合至电路由特征。 
在框203，粘合层可与第一管芯的第二侧耦合。图3a示出了制造IC封装组件300的对应的阶段。如所示的，粘合层330可与第一管芯302a的第二侧S2耦合并且可覆盖一个或多个电路由特征328。在多个实施例中，电路由特征328可以是TSV焊盘，以及第一TSV326可导电耦合至TSV焊盘328。在多个实施例中，粘合层330可在第一管芯302a从晶片单分之前或之后与第一管芯302a耦合。 
在框205，粘合层可耦合至牺牲面板。例如，如图3b所示，牺牲面板346可具有以堆叠配置排列的一个或多个层。例如，牺牲面板346可包括设 置在一个或多个外部金属层(诸如铜箔)之间的环氧树脂芯。在特定的实施例中，牺牲面板346的外部层中的一层或多层可被配置成当其他层被机械地剥离时保持粘附至粘合层330。随后可通过传统的蚀刻工艺将外部层(多个外部层)从粘合层330移除。 
在框207，可在第一管芯的第一侧上形成一个或多个建立层。图3c示出了制造具有无芯封装衬底304的IC封装组件300的对应阶段，无芯封装衬底304包括多个建立层350、352、354和356。建立层的数量和配置可在多个实施例中变化。虽然通过示例示出四个建立层，但在其他实施例中，封装衬底304可具有一个、两个、三个或超过四个建立层。在一些实施例中，可在第一管芯302a上连续形成建立层(或多个层建立层)。在其他实施例中，封装衬底304可在单独的工艺中形成并且随后与第一管芯302a耦合。 
在一些实施例中，可通过将介电材料的层(例如，ABS薄膜)层压到第一管芯302a的第一侧S1上、穿过介电材料(例如，通过激光钻孔)到电路由特征306钻通孔、用导电材料(例如，铜)填充/电镀通孔、以及通过已知方法在介电材料上和通孔上形成导电迹线来形成第一建立层350。可以相同或类似的方式连续形成附加的建立层352、354和356。可在最外层356中向导电特征(例如导电特征334，诸如通孔或迹线，或图1a的电路由特征110)中的一个或多个钻开口，并且可在开口中形成封装互连312。在一些实施例中，粘合层330可随着建立层形成而被固化(例如，通过加热、压力、和/或UV光固化)。 
在框209，可从粘合层移除牺牲面板，以暴露粘合层。在多个实施例中，牺牲面板的一些部分(诸如，环氧树脂芯)可从保持粘附至粘合层的另一部分(例如，铜箔的层)剥离。该剩余部分可通过传统的蚀刻工艺移除。图3d示出了制造的对应阶段，其中牺牲面板346已从粘合层330和封装衬底304移除。 
在框211，可在粘合层中形成开口以暴露电路由特征。图3e示出了根据多个实施例的制造的对应阶段。如所示的，激光器辐射源358可用于选 择性地消融粘合层330的一部分，从而在粘合层330中形成开口332以暴露电路由特征328。在多个实施例中，激光辐射360可以是紫外线(UV)激光辐射，并且激光器辐射源358可以是二氧化碳(CO2)激光器、一氧化碳(CO)激光器、以多种的谐波的钕掺杂钇铝石榴石(Nd：YAG)激光器、准分子激光器、或任何其他合适类型的激光器辐射源。在一些实施例中，激光器辐射源358可以是脉冲激光器。在其他实施例中，激光器辐射源358可以是连续激光器。在一些实施例中，激光辐射360可以是诸如绿色(例如，532nm)的短可见波长的激光辐射。 
在多个实施例中，可通过用基于光束扫描器的系统或基于掩模投影仪的系统消融粘合层330的一些或全部来形成开口332。在多个实施例中，可通过激光投影图案化(LPP)形成开口332。一些实施例中，LPP可用于在不扫描/切削的情况下和在对电路由特征328很少损坏或不损坏的相对低的通量(例如，0.3-0.8J/cm2)下暴露整个所选择的区域。在其他实施例中，电扫描器可用于采用激光辐射可控制地移除所选择的区域以形成开口332。此外，激光辐射可具有相对低的通量，该通量低于电路由特征328和/或第一管芯302a的第二侧S2的激光损坏阈值。在一些实施例中，可移除全部的粘合层330。 
在一些实施例中，框211可进一步包括去污过程，以从电路由特征328移除任何剩余的衬底残留。在其他实施例中，框211可进一步包括清洁过程(例如，用熔剂)以从电路由特征328的外部表面移除氧化/污染物。其他实施例可省略去污/清洁过程中的一个或两个。 
在框213，第二管芯可与第一管芯的第二侧耦合，且粘合层设置在第一和管芯之间。在多个实施例中，第二管芯302b可使用管芯连接工具或通过适用于精细间距应用(例如，小于100μm的凸起间距)的其他技术(诸如，热压接合(TCB))与第一管芯302a耦合。在一些实施例中，焊球可用于将第一管芯的TSV耦合至第二管芯的TSV。 
图3f示出了制造的对应阶段。如所示的，第二管芯302b可具有一个或多个TSV336，且第一管芯302a具有一个或多个TSV326。可在第一管 芯302a的第一TSV326和第二管芯302b的第二TSV336之间形成管芯互连320(例如，焊料)。TSV326和336、电路由特征328/138(分别参见图3f和1b)和管芯互连320可共同地形成导电路径(例如，图1b，导电路径142)，该导电路径通过粘合层330的开口332延伸。在一些实施例中，可通过传统的方法(诸如通过焊膏印刷/回流技术)形成管芯互连320。 
在框215，底部填充材料可置于第一管芯和第二管芯之间的开口中。在框217，可在第二管芯和一个或多个建立层上施加密封剂(例如，模制材料)。图3g示出了制造的对应阶段。如图所示，可在第一管芯302a和第二管芯302b之间添加填充材料以形成接口层324。接口层324可基本上填充开口332和/或第二管芯302b和粘合层330之间的剩余空间。在一些实施例中，在框209中，可移除全部的粘合层330，并且填充材料可用于填充第一管芯302a和第二管芯302b之间的一些或所有空间。在其他实施例中，可在第二管芯302b和/或封装衬底304上形成密封剂308。 
一些实施例可包括框215和217两者。在其他实施例中，可省略框215和217中的一个或两个。例如，在一些实施例中，可省略框215。在其他实施例中，可省略框217。在又一其他实施例中，可省略框215和框217两者。 
在其他实施例中，可在第一管芯与粘合层耦合之前图案化粘合层以形成开口，使得粘合层不接触电路由特征(例如，TSV焊盘)。图4示出了这种实施例的示例。图5a-5g和6a-6g示出了图4的实施例的两个变型。 
现参照图4，方法400可在框401处通过提供第一管芯开始(例如，图1的第一管芯102a)，该第一管芯具有第一侧、第二侧和第一TSV(例如，TSV126)，第一侧具有一个或多个晶体管，第二侧具有电路由特征(例如，电路由特征128)，第一TSV(例如，TSV126)耦合至电路由特征。 
在框403，粘合层可耦合至牺牲面板。在一些实施例中，如图5a中作为示例所示的，框403可包括在牺牲面板546上形成最外层的铜层570和在最外层的铜层570中形成开口572。可通过传统的技术(诸如，通过拾取和放置工具)将粘合层530定位到开口572内。 
替代地，如图6a中作为示例所示的，粘合层630可与牺牲面板646耦 合而不形成最外层的铜层570或开口572。 
在框405，可在粘合层中形成开口。如图5b和6b中作为示例所示的，可通过使用激光辐射源558/658在粘合层530/630中形成开口532/632，以将粘合层530/630的所选择的区域暴露至激光辐射560/660。 
在框407，可将粘合层耦合至第一管芯的第二侧，并且电路由特征定位在开口中。图5c和6c示出了制造的对应阶段。如所示的，将第一管芯502a/602a和电路由特征528/628定位在开口532/632中可减少或消除电路由特征528/628和粘合层530/630之间的接触。这可减少或消除对后续去污过程的需要。 
在框409，可在第一管芯上形成一个或多个建立层。图5d和6d示出了制造的对应阶段。如所示的，可在第一管芯502a/602a和电路由特征506/606上连续形成封装衬底504/604(例如，具有一个或多个建立层的BBUL衬底)。 
在框411，可从如上结合图2的框209所述的IC封装组件移除牺牲面板。 
可以与参照图2的框213、215和217所述的相同或相似的方式执行框413、415和417。 
在框413，如图5e和6e中作为示例所示的，第二管芯502b/602b可与第一管芯502a/602a的第二侧耦合。粘合层530/630可设置在第一管芯502a/602a和第二管芯502b/602b之间。在多个实施例中，可使用管芯连接工具或通过其他技术(诸如，热压缩接合(TCB))将第二管芯502b/602b与第一管芯502a/602a耦合。 
可在第一管芯502a/602a的第一TSV526/626和第二管芯502b/602b的第二TSV536/636之间形成管芯互连520/620(例如，焊球)。TSV526/626和536/636、电路由特征528/628、第二管芯502b/602b的对应的电路由特征(参见例如图1b，电路由特征138)以及管芯互连520/620可共同地形成导电路径(参见例如图1b，导电路径142)，该导电路径延伸通过粘合层530/630的开口532/632。在一些实施例中，可通过传统的方法(诸如通过 焊膏印刷/回流技术)形成管芯互连520/620。 
在框415，底部填充材料可置于到第一管芯和第二管芯之间的开口中。在框417，可在第二管芯和一个或多个建立层上施加密封剂(例如，模制材料)。图5f和6f示出了制造的对应阶段。在多个实施例中，底部填充材料可用于形成接口层524/624。在其他实施例中，可在第二管芯502b/602b和/或封装衬底504/604上形成密封剂508/608。此外，一些实施例可包括框415和417两者。在其他实施例中，可省略框415和417中的一个或两个。例如，在一些实施例中，可省略框415。在其他实施例中，可省略框417。在又一其他实施例中，可省略框415和框417两者。 
多个操作又以最有助于理解所要求保护的主题的方式被描述为多个不连续的操作。然而，描述的顺序不应当被解释为暗示这些操作一定是依赖于顺序。可在使用任何合适硬件和/或软件按需配置的系统中实现本公开的实施例。 
图7示出了根据多个实施例的计算设备701。本文所描述的IC封装组件可安装在计算/通信设备上。例如，IC封装组件700可安装在计算设备701上。IC封装组件700可包括嵌入在封装衬底704中的第一管芯和与第一管芯702a耦合的第二管芯702b。在本文中可参照IC封装组件100、300、500和/或600中的任一个描述IC封装组件700的部件、特征和/或配置。 
计算设备701可容纳电路板(诸如，主板722)。主板722可包括多个部件，多个部件包括但不限于IC封装组件700和至少一个通信芯片762。IC封装组件700可物理和电耦合至主板722(例如，图1的电路板122)。在一些实现中，通信芯片762也可物理和电耦合至主板722。在进一步实现中，通信芯片762可以是IC封装组件700的一部分。在多个实施例中，至少一个通信芯片762可物理和电耦合至IC封装组件700。在进一步实现中，通信芯片762可以是IC封装组件700的一部分，例如，在IC封装组件700中的建立层上的附加管芯或嵌入到IC封装组件700中的建立层中的附加管芯。对于这些实施例，IC封装组件700和通信芯片762可设置在主板722上。在替代的实施例中，可在不使用主板722的情况下耦合多个部件。 
在一些实施例中，IC封装组件700的管芯(例如，第一管芯702a)可以是计算设备701的处理器。术语“处理器”可表示任何设备或设备的一部分，其处理来自寄存器和/或存储器的电子数据，以将该电子数据转换成可存储于寄存器和/或存储器中的其它电子数据。 
根据其应用，计算设备701可包括可能或可能不物理和电耦合至主板722的其他部分。这些其他部件包括，但不限于，易失性存储器(例如，动态随机存取存储器，也称为“DRAM”)、非易失性存储器(例如，只读存储器，也称为“ROM”)、闪存存储器、输入/输出控制器、数字信号处理器(未示出)、加密处理器(未示出)、图形处理器、一个或多个天线、显示器(未示出)、触摸屏显示器、触摸屏控制器、电池、音频编解码器(未示出)、视频编解码器(未示出)、全球定位系统(“GPS”)设备、指南针、加速度计(未示出)、陀螺仪(未示出)、扬声器、照相机和大容量存储设备(如硬盘驱动器、固态驱动器、压缩盘(“CD”)、数字多功能盘(“DVD”))(未示出)、微反射镜(未示出)等等。在多个实施例中，多个部件可与其他部件集成以形成片上系统(“SoC”)。在进一步实施例中，一些部件(诸如，DRAM)可嵌入到IC封装组件700中或在IC封装组件700内。 
通信芯片762可实现用于从计算设备701传输数据和将数据传输到计算设备701的有线和/或无线通信。术语“无线”及其派生词可用于描述可通过使用通过非固态的介质的经调制的电磁辐射传播数据的电路、设备、系统、方法、技术、通信信道等等。术语不隐含相关联的设备不包含任何有线，虽然在一些实施例中它们可能不包括。通信芯片762可实现多个无线标准或协议中的任一个，包括但不限于包括Wi-Fi(IEEE802.11系列)、IEEE802.16标准(例如，IEEE802.16-2005修订)的电子与电气工程师协会(IEEE)标准、长期演进(LTE)项目以及任何修改、更新和/或修订(例如，先进的LTE项目、超移动宽带(UMB)项目(也被称为“3GPP2”)等等)。可兼容BWA网络的IEEE802.16一般被称为WiMAX网络，代表全球微波接入互操作性的首字母的缩写是用于通过针对IEEE802.16标准 的整合和互操作性测试的产品的认证标志。通信芯片762可根据全球移动通信系统(GSM)、通用分组无线业务(GPRS)、通用移动电信系统(UMTS)、高速分组接入(HSPA)、演进的HSPA(E-HSPA)或LTE网络操作。通信芯片762可根据用于GSM演进的增强型数据(EDGE)、GSM EDGE无线电接入网络(GERAN)、通用陆地无线接入网络(UTRAN)或演进的UTRAN(E-UTRAN)操作。通信芯片762可根据码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳通信(DECT)、演进数据优化(EV-DO)、它们的衍生物以及被指定为3G、4G、5G及以上的任何其他无线协议操作。在其他实施例中，通信芯片762可根据其他无线协议操作。 
计算设备701可包括多个通信芯片762。例如，第一通信芯片762可致力于更短范围的无线通信(诸如，Wi-Fi和蓝牙)以及第二通信芯片762可致力于更长范围的无线通信(诸如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他)。 
在多个实现中，计算设备701可以为膝上型计算机、上网本、笔记本电脑、超级笔记本、智能电话、平板电脑、个人数字助理(“PDA”)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元(例如，游戏控制台)、数码相机、便携式音乐播放器、数字视频录像机或数字手表。在进一步实现中，计算设备701可以是处理数据的任何其他电子设备。 
示例 
本文中描述3D IC封装组件、用于制造这种3D IC封装组件的方法和包含这种3D IC封装组件的系统的多个实施例。在多个实施例中，封装组件可包括具有多个建立层的封装衬底、嵌入到封装衬底中的第一管芯和与第一管芯耦合的第二管芯。在多个实施例中，第一管芯可具有第一侧、第二侧、第一硅通孔(TSV)和电路由特征，第一侧具有一个或多个晶体管，第二侧与第一侧相对，电路由特征设置在第二侧的第一部分上。在多个实施例中，电路由特征可通过第一TSV与一个或多个晶体管电耦合。 
在多个实施例中，第二管芯可具有与第一TSV电耦合的第二TSV。在 多个实施例中，封装组件可进一步包括设置在第一管芯的第二侧的第二部分上的粘合层，并且电路由特征可设置在粘合层中的开口内。在多个实施例中，第二管芯可以是存储器管芯。在多个实施例中，电路由特征可以是TSV焊盘。在多个实施例中，第一TSV可以是第一管芯的多个第一TSV中的一个。在多个实施例中，第二TSV可以是第二管芯的多个第二TSV中的一个，第二管芯的多个第二TSV与多个第一TSV对应并且以与多个第一TSV垂直对齐的方式排列。 
在多个实施例中，第二管芯可以是以三维(3D)存储器管芯堆叠配置的多个存储器管芯中的一个。在多个实施例中，电路由特征可以是第一TSV焊盘。在多个实施例中，第二管芯可具有与第二TSV耦合的第二TSV焊盘。在多个实施例中，封装组件可进一步包括与第一TSV焊盘和第二TSV焊盘耦合的管芯互连。在多个实施例中，封装组件可进一步包括设置在第一管芯和第二管芯之间的底部填充层。在多个实施例中，底部填充层可设置在第一管芯和第二管芯之间。在多个实施例中，底部填充层可设置在粘合层中的开口内。在多个实施例中，底部填充层的一部分可设置在粘合层和第一管芯之间。在多个实施例中，封装组件可进一步包括配置成包封第二管芯的模制材料层。 
在多个实施例中，方法可包括提供第一管芯，其中第一管芯具有第一侧、第二侧以及第一硅通孔(TSV)，第一侧具有一个或多个晶体管，第二侧具有电路由特征，以及第一硅通孔(TSV)耦合至电路由特征和设置在第一侧和第二侧之间，将粘合层耦合至第一管芯的第二侧、在第一管芯的第一侧上形成一个或多个建立层、在粘合层中形成开口、以及将第二管芯与第一管芯的第二侧耦合，并且粘合层设置在第一管芯和第二管芯之间。在多个实施例中，第二管芯可具有第二TSV，以及第一TSV可通过穿过开口的设置的导电路径与第二TSV电耦合。在多个实施例中，方法可进一步包括在将粘合层耦合至第一管芯的第二侧之前将粘合层耦合至牺牲面板。在多个实施例中，在粘合层中形成开口可包括在将粘合层耦合至管芯的第二侧之前形成穿过粘合层到牺牲面板的开口。在多个实施例中，将粘合层 耦合至管芯的第二侧可包括通过设置在开口中的电路由特征将管芯的第二侧放置在粘合层上。 
在多个实施例中，该方法可进一步包括在牺牲面板上形成铜层和在铜层中形成腔。在多个实施例中，将粘合层耦合至牺牲面板可包括在形成穿过粘合层到牺牲面板的开口之前将粘合层置于腔中。在多个实施例中，将粘合层耦合至第一管芯的第二侧可包括将粘合层的一部分置于电路由特征上。在多个实施例中，方法可进一步包括将第一管芯和粘合层置于牺牲面板上，并且粘合层设置在第一管芯和牺牲面板之间，以及在管芯的第一侧上形成一个或多个建立层之后从粘合层移除牺牲面板。在多个实施例中，在粘合层中形成开口可包括在移除牺牲面板之后移除粘合层的一部分以暴露电路由特征。在多个实施例中，在粘合层中形成开口可包括将粘合层的一部分暴露至激光辐射。在多个实施例中，可通过激光投影图案化工具执行将粘合层的一部分暴露至激光辐射。在多个实施例中，激光投影图案化工具可包括一个或多个准分子激光器。 
在多个实施例中，移除粘合层的一部分可进一步包括用紫外线(UV)激光器扫描粘合层的一部分。在多个实施例中，移除粘合层的一部分可进一步包括通过准分子激光器将粘合层的一部分暴露至激光辐射。在多个实施例中，移除粘合层的一部分可进一步包括通过激光直接成像将粘合层的一部分暴露至激光辐射。在多个实施例中，移除粘合层的一部分可进一步包括通过激光投影图案化将粘合层的一部分暴露至激光辐射。在多个实施例中，激光辐射可以是UV或绿光激光辐射。在多个实施例中，方法可进一步包括在第二管芯和一个或多个建立层上应用模制材料。在多个实施例中，第二管芯可嵌入到模制材料中。在多个实施例中，该方法可进一步包括在第一管芯和第二管芯之间应用底部填充材料。 
在多个实施例中部，系统可包括电路板和通过设置在封装组件的外部表面上的电路由特征与电路板耦合的封装组件。在多个实施例中，封装组件可包括包含一个或多个建立层的衬底、嵌入到衬底中的第一管芯、第二管芯、管芯互连和电路径。在多个实施例中，第一管芯可具有第一侧、第 二侧、第一TSV和第一电路由特征，第一侧具有一个或多个晶体管，第二侧与第一侧相对，第一电路由特征在第二侧上。在多个实施例中，第一侧可通过第一TSV与第一电路由特征电耦合。在多个实施例中，封装组件可进一步包括设置在第一管芯的第二侧上的粘合层。在多个实施例中，第二管芯可具有第二TSV和与第二TSV电耦合的第二电路由特征。在多个实施例中，管芯互连可设置在第一电路由特征和第二电路由特征之间。在多个实施例中，电路径可包括第一TSV和第二TSV，并且可配置成通过一个或多个建立层在第二管芯和电路板之间路由电信号。 
在多个实施例中，第一管芯可包括微处理器管芯。在多个实施例中，第一TSV可以是第一管芯的多个第一TSV中的一个。在多个实施例中，第二管芯可以是以三维(3D)堆叠的方式排列的多个存储器管芯。在多个实施例中，第二TSV可以是第二管芯的多个TSV中的一个，第二管芯的多个TSV与多个第一TSV对应并且以与多个第一TSV垂直对齐的方式排列。在多个实施例中，该系统可进一步包括设置在第一管芯和第二管芯之间的底部填充材料。在多个实施例中，系统可进一步包括设置成包封第二管芯的模制化合物。在多个实施例中，系统可进一步包括天线、触摸屏显示器、触摸屏控制器、电池、全球定位系统(GPS)装置、指南针、扬声器、照相机和大容量存储设备中的一个或多个。 
多个实施例可包括以上描述的实施例的任何合适的组合。此外，一些实施例可包括具有存储在其上的指令的一个或多个非暂时性计算机可读介质，该指令当执行时产生以上描述的实施例中的任何一个动作。此外，一些实施例可包括具有用于执行以上实施例的各种操作的任何合适装置的装置或系统。 
所示的实现的上述描述、包括摘要中的描述的不旨在穷举或将本公开的实施例限制为所公开的精确形式。虽然为了说明目的在本文中描述了特定实现和示例，但如相关领域技术人员将认识到的，在本发明的范围内有许多等效修改是可能的。 
鉴于以上详细描述，可对本公开的实施例进行这些修改。下面权利要 求中使用的术语不应当解释成将本公开的各个实施例限定于说明书和权利要求书所披露的特定实现。相反，本发明的范围完全由所附权利要求确定，所附权利要求将根据已确立的权利要求解释原则来解读。 

Claims (25)

1.一种封装组件，包括：
具有多个建立层的封装衬底；
嵌入到所述封装衬底中的第一管芯，所述第一管芯具有第一侧、第二侧、第一硅通孔(TSV)以及电路由特征，所述第一侧具有一个或多个晶体管，第二侧与第一侧相对，电路由特征设置在所述第二侧上，其中所述电路由特征通过第一TSV与一个或多个晶体管中的至少一个晶体管电耦合；以及
与所述第一管芯的第二侧耦合的第二管芯，所述第二管芯具有第二TSV，其中所述第二TSV与第一TSV电耦合。
2.如权利要求1所述的封装组件，其特征在于，进一步包括设置在所述第一管芯的第二侧的第二部分上的粘合层，所述电路由特征设置在粘合层中的开口内。
3.如权利要求1所述的封装组件，其特征在于：
所述第二管芯为存储器管芯；
所述电路由特征为TSV焊盘；
所述第一TSV为所述第一管芯的多个第一TSV中的一个；以及
第二TSV为所述第二管芯的多个第二TSV中的一个，所述第二管芯的多个第二TSV与多个第一TSV对应并且以与多个第一TSV垂直对齐的方式排列。
4.如权利要求1－3中的任一项所述的封装组件，其特征在于，所述第二管芯为配置为三维(3D)存储器管芯堆叠的多个存储器管芯中的一个。
5.如权利要求1－3中的任一项所述的封装组件，其特征在于，所述电路由特征为第一TSV焊盘，所述第二管芯具有与第二TSV耦合的第二TSV，以及所述封装组件进一步包括与所述第一TSV焊盘和第二TSV焊盘耦合的管芯互连。
6.如权利要求1－3中的任一项所述的封装组件，其特征在于，进一步包括设置在所述第一管芯和第二管芯之间的底部填充层。
7.如权利要求2所述的封装组件，进一步包括设置在粘合层中的开口内的底部填充层。
8.如权利要求1－3中的任一项所述的封装组件，其特征在于，所述底部填充层的一部分设置在所述粘合层和第一管芯之间。
9.如权利要求1－3中的任一项所述的封装组件，其特征在于，进一步包括配置成封装第二管芯的模制材料层。
10.一种制造集成电路封装组件的方法，包括：
提供第一管芯，其中所述第一管芯具有第一侧、第二侧和第一硅通孔(TSV)，所述第一侧具有一个或多个晶体管，所述第二侧具有电路由特征，所述第一硅通孔耦合至所述电路由特征并且设置在所述第一管芯和第二管芯之间；
将粘合层耦合至所述第一管芯的第二侧；
在所述第一管芯的第一侧上形成一个或多个建立层；
在粘合层中形成开口；以及
将第二管芯与所述第一管芯的第二侧耦合，并且所述粘合层设置在所述第一管芯和第二管芯之间，其中所述第二管芯具有第二TSV，并且其中所述第一TSV通过穿过开口设置的导电路径与所述第二TSV电耦合。
11.如权利要求10所述的方法，其特征在于，进一步包括在将所述粘合层耦合至所述第一管芯的第二侧之前将粘合层耦合至牺牲面板。
12.如权利要求11所述的方法，其特征在于，在粘合层中形成开口包括在将粘合层耦合至管芯的第二侧之前形成穿过所述粘合层到牺牲面板的开口，并且其中将粘合层耦合至管芯的第二侧包括通过设置在开口中的电路由特征将管芯的第二侧置于粘合层上。
13.如权利要求12所述的方法，其特征在于，进一步包括：
在牺牲面板上形成铜层；以及
在铜层中形成腔，
其中将粘合层耦合至牺牲面板包括在形成穿过粘合层到牺牲面板的开口之前将粘合层置于腔中。
14.如权利要求10所述的方法，其特征在于，将粘合层耦合至第一管芯的第二侧包括将粘合层的一部分置于电路由特征上，所述方法进一步包括：
将第一管芯和粘合层置于牺牲面板上，并且粘合层设置在第一管芯和牺牲面板之间；以及
在管芯的第一侧上形成一个或多个建立层之后从粘合层移除牺牲面板，
其中在粘合层中形成开口包括在移除牺牲面板之后移除粘合层的一部分以暴露电路由特征。
15.如权利要求10所述的方法，其特征在于，在粘合层中形成开口包括将粘合层的一部分暴露至激光辐射。
16.如权利要求15所述的方法，其特征在于，将粘合层的一部分暴露至激光辐射通过激光投影图案化工具执行。
17.如权利要求15所述的方法，其特征在于，移除粘合层的一部分进一步包括用紫外线(UV)激光器扫描粘合层的一部分。
18.如权利要求10-17中的任一项所述的方法，其特征在于，进一步包括在第二管芯和一个或多个建立层上施加模制材料，其中所述第二管芯嵌入到所述模制材料中。
19.如权利要求10－17中的任一项所述的方法，其特征在于，进一步包括在所述第一管芯和第二管芯之间施加底部填充材料。
20.一种计算设备，包括：
电路板；以及
封装组件，所述封装组件通过设置在封装组件的外表面上的电路由特征与所述电路板耦合，所述封装组件包括：
衬底，所述衬底包括一个或多个建立层；
嵌入在衬底中的第一管芯，所述第一管芯具有第一侧、第二侧、第一TSV和第一电路由特征，所述第一侧具有一个或多个晶体管，所述第二侧与所述第一侧相对，所述第一电路由特征在所述第二侧上，所述第一侧通过第一TSV与第一电路由特征电耦合；
第二管芯，所述第二管芯具有第二TSV和与所述第二TSV电耦合的第二电路由特征；
管芯互连，所述管芯互连设置在第一电路由特征和第二电路由特征之间；以及
电路径，所述电路径包括第一TSV和第二TSV，其中所述电路径被配置成通过一个或多个建立层在第二管芯和电路板之间路由电信号。
21.如权利要求20所述的计算设备，其特征在于，进一步包括设置在第一管芯的第二侧上的粘合层。
22.如权利要求20所述的计算设备，其特征在于，所述第一管芯包括微处理器管芯。
23.如权利要求20所述的计算设备，其特征在于，所述第一TSV为第一管芯的多个第一TSV中的一个，所述第二管芯为以三维(3D)堆叠排列的多个存储器管芯，并且所述第二TSV为第二管芯的多个TSV中的一个，所述第二管芯的多个TSV与多个第一TSV对应并且以与多个第一TSV垂直对齐的方式排列。
24.如权利要求20-23中的任一项所述的计算设备，其特征在于，进一步包括：
设置在第一管芯和第二管芯之间的底部填充材料；或
设置成包封第二管芯的模制化合物。
25.如权利要求20-23中的任一项所述的计算设备，其特征在于，进一步包括天线、触摸屏显示器、触摸屏控制器、电池、全球定位系统(GPS)装置、指南针、扬声器、照相机和大容量存储设备中的一个或多个。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107111573A (zh) * 2015-01-22 2017-08-29 高通股份有限公司 采用分布式穿硅通孔(tsv)场的三维(3d)集成电路(ic)(3dic)中的存储器控制器放置
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9000599B2 (en) * 2013-05-13 2015-04-07 Intel Corporation Multichip integration with through silicon via (TSV) die embedded in package
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US20150380343A1 (en) * 2014-06-27 2015-12-31 Raytheon Company Flip chip mmic having mounting stiffener
TWI582553B (zh) * 2014-09-30 2017-05-11 巨擘科技股份有限公司 實體指針式腕錶結構及將通訊功能附加於腕錶的方法
KR102316267B1 (ko) 2015-04-15 2021-10-22 삼성전자주식회사 씨오피 구조를 갖는 메모리 장치, 이를 포함하는 메모리 패키지 및 그 제조 방법
WO2017003407A1 (en) * 2015-06-27 2017-01-05 Intel Corporation Ge nano wire transistor with gaas as the sacrificial layer
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US10352991B2 (en) 2015-07-21 2019-07-16 Fermi Research Alliance, Llc Edgeless large area ASIC
KR102497239B1 (ko) 2015-12-17 2023-02-08 삼성전자주식회사 고속 신호 특성을 갖는 반도체 모듈
KR102493462B1 (ko) 2016-02-11 2023-01-30 삼성전자 주식회사 반도체 칩 적층을 위한 장치
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
DE112016006809T5 (de) * 2016-04-28 2019-02-14 Intel Corporation Integrierte schaltungsstrukturen mit erweiterten leitungswegen
US10256219B2 (en) 2016-09-08 2019-04-09 Intel Corporation Forming embedded circuit elements in semiconductor package assembles and structures formed thereby
KR102018616B1 (ko) * 2017-07-04 2019-09-06 삼성전자주식회사 반도체 장치
KR102077455B1 (ko) 2017-07-04 2020-02-14 삼성전자주식회사 반도체 장치
US10658281B2 (en) * 2017-09-29 2020-05-19 Intel Corporation Integrated circuit substrate and method of making
KR102450580B1 (ko) 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
US11036030B2 (en) * 2018-06-15 2021-06-15 Silicon Light Machines Corporation MEMS posting for increased thermal dissipation
KR102596758B1 (ko) 2018-10-24 2023-11-03 삼성전자주식회사 반도체 패키지
CN109546278B (zh) * 2018-10-25 2021-05-28 西安电子科技大学 一种基于硅通孔的三维耦合器及其制备方法
TWI719670B (zh) * 2018-11-30 2021-02-21 台灣積體電路製造股份有限公司 積體電路封裝體及其製造方法
US11217538B2 (en) 2018-11-30 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10803548B2 (en) 2019-03-15 2020-10-13 Intel Corporation Disaggregation of SOC architecture
EP3771028A1 (en) * 2019-07-25 2021-01-27 Nxp B.V. Semiconductor device and method
KR20210120221A (ko) 2020-03-26 2021-10-07 삼성전자주식회사 반도체 스택 및 그 제조 방법
US20220102344A1 (en) * 2020-09-25 2022-03-31 Intel Corporation Gallium nitride (gan) three-dimensional integrated circuit technology

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161833A1 (en) * 2004-01-20 2005-07-28 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20110057327A1 (en) * 2009-09-10 2011-03-10 Elpida Memory, Inc. Semiconductor device and method of manufacturing the same
US20120074581A1 (en) * 2010-09-24 2012-03-29 Guzek John S Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
CN103022021A (zh) * 2011-09-22 2013-04-03 株式会社东芝 半导体装置及其制造方法
WO2013066294A1 (en) * 2011-10-31 2013-05-10 Intel Corporation Multi die package structures

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3732148B2 (ja) * 2002-02-19 2006-01-05 住友ベークライト株式会社 半導体装置の製造方法及び半導体装置
JP4540642B2 (ja) * 2006-07-05 2010-09-08 積水化学工業株式会社 半導体の製造方法
JP2009110995A (ja) * 2007-10-26 2009-05-21 Toray Eng Co Ltd ３次元実装方法及び装置
KR101481577B1 (ko) * 2008-09-29 2015-01-13 삼성전자주식회사 잉크 젯 방식의 댐을 구비하는 반도체 패키지 및 그 제조방법
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
KR101058621B1 (ko) * 2009-07-23 2011-08-22 삼성전기주식회사 반도체 패키지 및 이의 제조 방법
JP2011071381A (ja) 2009-09-28 2011-04-07 Toshiba Corp 積層型半導体装置およびその製造方法
US8993377B2 (en) * 2010-09-29 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of bonding different size semiconductor die at the wafer level
JP5361840B2 (ja) * 2010-10-18 2013-12-04 信越化学工業株式会社 半導体装置の製造方法、及び該製造方法を用いて製作された半導体装置
JP2012138394A (ja) * 2010-12-24 2012-07-19 Elpida Memory Inc 半導体装置の製造方法
JP2012212698A (ja) * 2011-03-30 2012-11-01 Toshiba Corp 半導体装置の製造方法
JP2013021119A (ja) * 2011-07-11 2013-01-31 Shin Etsu Chem Co Ltd ウエハーレベルアンダーフィル剤組成物、これを用いた半導体装置及びその製造方法
US9000599B2 (en) * 2013-05-13 2015-04-07 Intel Corporation Multichip integration with through silicon via (TSV) die embedded in package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161833A1 (en) * 2004-01-20 2005-07-28 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20110057327A1 (en) * 2009-09-10 2011-03-10 Elpida Memory, Inc. Semiconductor device and method of manufacturing the same
US20120074581A1 (en) * 2010-09-24 2012-03-29 Guzek John S Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
CN103022021A (zh) * 2011-09-22 2013-04-03 株式会社东芝 半导体装置及其制造方法
WO2013066294A1 (en) * 2011-10-31 2013-05-10 Intel Corporation Multi die package structures

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107111573A (zh) * 2015-01-22 2017-08-29 高通股份有限公司 采用分布式穿硅通孔(tsv)场的三维(3d)集成电路(ic)(3dic)中的存储器控制器放置
CN107111573B (zh) * 2015-01-22 2020-03-31 高通股份有限公司 三维3d集成电路及其中使用的方法
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
US11031377B2 (en) 2019-04-15 2021-06-08 Yangtze Memory Technologies Co., Ltd. Integration of three-dimensional NAND memory devices with multiple functional chips
US11923339B2 (en) 2019-04-15 2024-03-05 Yangtze Memory Technologies Co., Ltd. Integration of three-dimensional NAND memory devices with multiple functional chips

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