CN104009007B - 模塑料结构 - Google Patents

模塑料结构 Download PDF

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Publication number
CN104009007B
CN104009007B CN201310190559.0A CN201310190559A CN104009007B CN 104009007 B CN104009007 B CN 104009007B CN 201310190559 A CN201310190559 A CN 201310190559A CN 104009007 B CN104009007 B CN 104009007B
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pseudo
block
substrate
package
semiconductor element
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CN104009007A (zh
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陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种器件，包括封装部件，该封装部件包括形成在封装部件的第一侧上的多个凸块，安装在封装部件的第一侧上的半导体管芯，形成在封装部件的第一侧上方的介电材料，其中封装部件的顶面的四个角部都没有介电材料，以及接合在封装部件的第一侧上的顶部封装件，其中半导体管芯位于顶部封装件和封装部件之间。本发明还公开了模塑料结构。

Description

模塑料结构
技术领域
本发明涉及半导体技术领域，更具体地，涉及模塑料结构。
背景技术
由于各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的改进，半导体工业经历了快速增长。在很大程度上，集成密度的改进来自半导体工艺节点的缩小(例如，使工艺节点朝亚20nm节点缩小)。随着近来对微型化、更高速度和更大带宽以及较低功率损耗和延迟的需求增长，日益需要用于半导体管芯的更小和更新的封装技术。
随着半导体技术的进一步改进，堆叠封装半导体器件作为有效的替代应运而生以进一步缩小半导体器件的物理尺寸。在堆叠封装半导体器件中，在不同的晶圆和封装件上制造诸如逻辑电路、存储电路、处理电路等有源电路。两个或多个封装件安装在另一个封装件上方，即堆叠，它们之间具有标准接口以路由信号。通过使用堆叠封装半导体器件来实现更高的密度。而且，堆叠封装半导体器件能够实现较小的形状因数、成本效益、增强的性能以及较低的功率损耗。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种器件，包括：
封装部件，包括：多个凸块，形成在所述封装部件上；
半导体管芯，安装在所述封装部件上；
介电材料，形成在所述封装部件上方，所述封装部件的顶面的四个角部没有所述介电材料；以及
顶部封装件，接合在所述封装部件上，所述半导体管芯位于所述顶部封装件和所述封装部件之间。
在可选实施例中，所述介电材料形成位于所述封装部件上方的模塑料层，并且所述半导体管芯嵌入在所述模塑料层中。
在可选实施例中，所述模塑料层是梯形。
在可选实施例中，所述梯形具有范围在约50度至约80度之间的内角。
在可选实施例中，所述模塑料层的截面是剪切同一侧角部的矩形，并且所述剪切同一侧角部的矩形包括：矩形；以及，梯形，位于所述矩形上方，并且所述梯形具有范围在约50度至约80度之间的内角。
在可选实施例中，所述封装部件是封装衬底。
在可选实施例中，所述封装部件的顶面的四个边缘区域没有所述介电材料，每一个边缘区域的宽度均约等于50um。
在可选实施例中，每个角部的形状都是三角形。
在可选实施例中，所述三角形的第一边的第一尺寸约大于或等于所述凸块的节距的一半；以及，所述三角形的第二边垂直于所述第一边，所述第二边的第二尺寸约大于或等于所述凸块的节距的一半。
根据本发明的另一个方面，还提供了一种方法，包括：
在封装衬底的顶面的子部中设置半导体管芯；
在所述子部的四个角部处设置伪块状件；
在所述封装衬底的顶面上形成多个凸块，以行和列的方式布置所述多个凸块；
在所述封装衬底的顶面上方沉积密封层，所述半导体管芯嵌入到所述密封层中；
从所述封装衬底卸离所述伪块状件；
将所述封装衬底切割成多个芯片封装件；以及
将顶部封装件连接至所述封装衬底，其中：在所述封装衬底和所述顶部封装件之间设置所述半导体管芯；并且，所述顶部封装件和所述封装衬底通过所述凸块连接在一起。
在可选实施例中，所述方法进一步包括：将释放层附接在所述封装衬底的每一个角部上方；将所述伪块状件通过所述释放层附接至所述封装衬底；以及，对所述封装衬底实施释放工艺以卸离所述伪块状件。
在可选实施例中，所述方法进一步包括：将释放层附接在所述封装衬底的顶面的边缘区域上方；将所述边缘区域的伪块状件通过所述释放层附接至所述封装衬底；以及，对所述封装衬底实施释放工艺以卸离所述边缘区域的伪块状件。
在可选实施例中，所述方法进一步包括：将环形的伪块状件附接在所述封装衬底的顶面上，其中所述环形的伪块状件覆盖所述封装衬底的子部中的四个角部和四个边缘区域。
根据本发明的又一个方面，还提供了一种方法，包括：
在衬底的第一侧上附接第一半导体管芯；
在所述衬底的所述第一侧上附接第二半导体管芯；
在所述第一半导体管芯和所述第二半导体管芯之间附接伪块状件；
在所述衬底的第一侧上方沉积模塑料层，其中所述第一半导体管芯、所述第二半导体管芯和所述伪块状件嵌入在所述模塑料层中；以及
从所述衬底卸离所述伪块状件。
在可选实施例中，所述方法进一步包括：切割所述衬底以形成包括所述第一半导体管芯的第一芯片封装件；以及，在所述第一芯片封装件上附接顶部封装件，其中所述第一半导体管芯位于所述衬底和所述顶部封装件之间。
在可选实施例中，所述方法进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件是围绕所述第一半导体管芯的环。
在可选实施例中，所述方法进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件的形状是矩形。
在可选实施例中，所述方法进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件的形状是倒梯形。
在可选实施例中，所述方法进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件的形状是多边形。
在可选实施例中，所述方法进一步包括：通过多个第一微凸块将所述第一半导体管芯附接在所述衬底上；以及，通过多个第二微凸块将所述第二半导体管芯附接在所述衬底上。
附图说明
为了更充分地理解本发明和优点，现将结合附图所作的以下描述作为参考，其中：
图1示出根据本发明各种实施例的半导体器件的俯视图和两个截面图；
图2示出根据本发明各种实施例的另一半导体器件的俯视图；
图3示出根据本发明各种实施例的接合在封装部件顶部的多个半导体管芯；
图4示出根据本发明各种实施例的在两个相邻的半导体管芯之间安装多个伪块状件之后图3示出的半导体器件的截面图；
图5示出根据本发明各种实施例的在封装衬底上形成模塑料层之后图4示出的半导体器件的截面图；
图6示出根据本发明各种实施例的从封装衬底卸离伪块状件之后图5示出的半导体器件的截面图；
图7示出根据本发明各种实施例的对图6示出的半导体器件应用切割工艺之后单个的芯片封装件；
图8-12示出根据另一实施例的处于制造堆叠封装半导体器件的中间阶段的截面图；以及
图13示出根据本发明各种实施例的另一单个的芯片封装件的截面图。
除非另有指明，不同附图中相应的编号和符号通常指的是相应的部分。绘制附图是为了清晰地示出各个实施例的相关方面，并且附图不必按比例绘制。
具体实施方式
以下详细论述实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅是制造和使用实施例的示例性具体方式，而不用于限制实施例的范围。
将就具体环境中的实施例来描述本发明，即用于堆叠封装半导体器件的模塑料层结构。然而，本发明的实施例还可以应用到各种半导体器件。下文中，参考附图将详细说明各种实施例。
图1示出根据本发明各种实施例的半导体器件的俯视图和两个截面图。半导体器件10的俯视图100示出堆叠在封装衬底102上的半导体管芯104。在封装衬底102的顶面上安装多个凸块108。此外，如图1所示，以行和列的方式布置凸块108。凸块108的节距限定为P。在一些实施例中，P处于约350nm至约450nm的范围。
半导体器件10进一步包括形成在封装衬底102上方的模塑料层106。在封装衬底102的顶面上除了其四个角部之外沉积模塑料层106。如图1所示，封装衬底102的暴露的角部是三角形。角部的第一边可以是第一尺寸L1。角部的第二边可以是第二尺寸L2。角部的尺寸(例如，L1和L2)可能受到下列限制。在一些实施例中，第一尺寸L1和第二尺寸L2大于或者等于节距P的一半。
具有以上限制的一个有利特点是尺寸限制有助于降低半导体器件10的堆叠封装结构上的应力。降低堆叠封装结构上的应力有助于防止一些制造故障，诸如发生在后续的制造步骤和各种可靠性测试期间的翘曲和/或类似故障。
在一些实施例中，通过使用图1所示的模塑料层106，堆叠封装结构上的应力可以降低30％。因此，可以改善半导体器件10的可靠性。
为了更好地示出模塑料层106，分别沿线A-A’和B-B’获得截面图110和115。截面图110示出堆叠封装结构。通过多个凸块108在封装衬底102的顶部上堆叠顶部封装件112。半导体管芯104通过多个微凸块连接至封装衬底102的顶面。在封装衬底102上方形成模塑料层106。在模塑料层106中嵌入半导体管芯104。
顶部封装件112可以包括多个堆叠的管芯，其可以引线接合至顶部封装件112的输入端和输出端。顶部封装件112的堆叠管芯可以包括存储管芯、逻辑管芯、处理管芯和/或类似物。应该注意，虽然图1示出顶部封装件112中的两个堆叠管芯，但这仅是一个实例。同样，引线接合法的使用仅是示例性的，用于电连接堆叠管芯的其他方法也包含在本发明的考虑范围内。
除了模塑料层106不覆盖封装衬底102的顶面的角部之外，截面图115示出的结构类似于截面图110的结构。如图1中的截面图115所示，在封装衬底102的顶面上除了其角部之外沉积模塑料层106。具体而言，邻近封装衬底102的第一边缘的左边部分122和邻近封装衬底102的第二边缘的右边部分124没有模塑料。
通过合适的沉积技术在封装衬底102上沉积模塑料层106。通过使用多个伪块状件(dummy block)，封装衬底102的角部可以没有模塑料。以下参考图4和图5描述详细的制造工艺。
图2示出根据本发明各种实施例的另一半导体器件的俯视图。除了封装衬底102的四个边缘区域没有模塑料之外，图2示出的半导体器件20的结构类似于图1示出的半导体器件10的结构。图2的P、L1和L2类似于图1的P、L1和L2。此外，边缘区的宽度限定为R(如图2所示)。根据一些实施例，R约等于50um。以下将参考图5描述图2示出的模塑料层106的详细制造工艺。
图3-7示出根据本发明各种实施例的制造图1和图2示出的半导体器件的中间步骤。
图3示出根据本发明各种实施例的接合至封装部件的顶部上的多个半导体管芯。封装部件可以是硅晶圆。在一些实施例中，封装部件可以是厚度大于100um的标准晶圆。在可选的实施例中，封装部件可以是厚度为约770um的硅晶圆。
而且，封装部件可以是封装衬底。在整个说明书中，封装部件可选地被称为封装衬底102。封装衬底102可以由陶瓷材料、有机材料、它们的组合和/或类似物形成。
封装衬底102可以包括多个集成电路(未示出)，每一个都可以包括诸如有源电路层、衬底层、层间介电层(ILD)和金属间介电(IMD)层(未示出)的各种层。封装衬底102可以进一步包括多个通孔(未示出)。在一些实施例中，通孔是衬底通孔(TSV)或者硅通孔(TSV)。封装衬底102的有源电路层可以通过由多个TSV和微凸块312形成的导电沟道连接至接合在封装衬底102上的半导体管芯104。
在封装衬底102的微凸块(例如微凸块312)一侧的上方形成介电层。下文中介电层可以可选地被称为ILD层。在一些实施例中，ILD层由感光材料形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、它们的任何组合和/或类似物，使用光刻掩模可以很容易地将其图案化。在可选的实施例中，ILD层可以由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、它们的任何组合和/或类似物形成。可以通过诸如旋涂、CVD和PECVD和/或类似工艺的合适的制造技术形成ILD层。
在封装衬底102的顶面上方可以形成再分配层(未示出)。具体而言，可以在ILD层中/上形成再分配层。再分配层在封装衬底102的TSV和微凸块312之间提供导电路径。再分配层可以由诸如铝、铝合金、铜、铜合金、它们的组合和/或其他等任何合适的金属材料形成。
ILD层可以具有多个开口(未示出)，通过这些开口暴露再分配层的顶面。再分配层的暴露部分可以用作接合焊盘。半导体管芯104通过微凸块312接合在接合焊盘上。
将半导体管芯104拾起并放置在封装衬底102上方。在回流焊工艺之后，半导体管芯104通过微凸块312接合在封装衬底102的接合焊盘上。在一些实施例中，接合工艺可以是迹线上凸块(BOT)工艺。在封装衬底上接合半导体管芯的详细工艺是本领域已知的，因而在此不再论述以避免重复。
应该注意，虽然图3示出了接合在封装衬底102上的三个半导体管芯104，但是封装衬底102可以容纳任意数目的半导体管芯。
为了对各个实施例的发明方面有基本的了解，如图3所示，没有详细地绘制半导体管芯104。然而，应该注意，半导体管芯104可以包括基础半导体层，诸如有源电路层、衬底层、ILD层、IMD层、介电层和再分配层(没有分别示出)。
半导体管芯104可以包括衬底(未示出)。在一些实施例中，衬底可以是硅衬底。可选地，衬底可以是绝缘体上硅衬底。衬底可以进一步包括各种电路(未示出)。形成在衬底上的电路可以是适合于具体应用的任何类型的电路。
在一些实施例中，电路可以包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。可以互连电路以实现一个或多个功能。这些功能可以包括存储结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。
本领域技术人员将认识到，提供以上实例仅用于说明的目的以进一步说明本发明的应用，而不打算以任何方式限制本发明。
在衬底上形成隔离层(未示出)。隔离层可以由例如低k介电材料形成，诸如氧化硅。可以通过本领域已知的任何合适的方法形成隔离层，诸如旋涂、化学汽相沉积(CVD)和等离子体增强化学汽相沉积(PECVD)。还应该注意，本领域技术人员应该认识到，隔离层可以进一步包括多个介电层。
可以在隔离层上形成再分配层(未示出)。可以通过再分配层桥接半导体管芯的有源电路层(未示出)从而使得半导体管芯104的有源电路层能够连接至其输入和输出(I/O)端。
凸块(微凸块312)提供了将半导体管芯104与封装衬底102连接的有效方法。凸块是半导体管芯104的I/O端。在一些实施例中，凸块(例如微凸块312)可以是多个焊球。
在将半导体管芯(例如半导体管芯104)接合在封装衬底102上之后，可以在封装衬底102和安装在封装衬底102上方的多个半导体管芯(例如半导体管芯104)之间的间隙中形成底部填充材料层(未示出)。在一些实施例中，底部填充材料层可以是环氧树脂，所述环氧树脂被分散在封装衬底102和半导体管芯104之间的间隙中。可以施加液态的环氧树脂，并且可以在固化工艺之后硬化环氧树脂。在可选的实施例中，底部填充层可以由可固化的材料形成，诸如基于聚合物的材料、基于树脂的材料、聚酰亚胺、环氧树脂和它们的任何组合。
可以通过旋涂工艺、干膜层压工艺和/或类似物来形成底部填充层。具有底部填充材料层的一个有利特点是底部填充材料层有助于防止微凸块312断裂。此外，底部填充材料层有助于降低制造工艺期间半导体管芯104上的机械应力和热应力。
图4示出根据本发明各种实施例的在相邻的半导体管芯之间安装多个伪块状件之后图3示出的半导体器件的截面图。可以通过合适的接合技术将伪块状件402连接至封装衬底102的顶面。伪块状件402可以由诸如玻璃、钢铁、硅和/或类似物的合适材料形成。
如图4所示，伪块状件402与半导体管芯104齐平。参考图1，封装衬底102可以具有多个子部(subdivision)，每一个子部都容纳有半导体管芯(例如半导体管芯104)。可以将伪块状件402设置在每一子部的四个角部上。因此，后续形成的模塑料层(图5示出)不覆盖每一子部的四个角部。
在可选的实施例中，伪块状件402可以是环形。返回参考图2，在封装衬底102的每一子部中，环形的伪块状件402可以覆盖封装衬底102的顶面的四个角部和四个边缘区域，从而使得后续形成的模塑料层不覆盖封装衬底的顶面的四个角部和四个边缘区域。
可以使用释放层(release layer)(未示出)将伪块状件402暂时接合在封装衬底102上。在一些实施例中，释放层可以由基于环氧树脂的热释材料形成。在可选的实施例中，释放层可以由紫外(UV)胶形成，当其暴露于UV光时失去粘附特性。
可以通过任何合适的半导体制造技术在封装衬底102上方形成释放层。在一些实施例中，释放层可以以液体分发随后将其固化。在可选的实施例中，可以将释放层层压到封装衬底102上。
图4进一步示出形成在封装衬底102的顶面上方的多个凸块108。采用凸块108将封装衬底102与顶部封装件连接(未示出但图1中示出)。
图5示出根据本发明各种实施例的在封装衬底的顶部形成模塑料层之后图4示出的半导体器件的截面图。如图5所示，半导体管芯104嵌入在模塑料层502中。模塑料层502可以由可固化的材料形成，诸如基于聚合物的材料、基于树脂的材料、聚酰亚胺、环氧树脂和它们的任何组合。应该注意，在整个说明书中，模塑料层可以可选地被称为密封层。
可以通过旋涂工艺、注入模塑工艺和/或类似物形成模塑料层502。在封装衬底102上具有模塑料层的一个有利特点是在半导体器件的工艺步骤(诸如背面研磨工艺)期间使用模塑料层502以防止封装衬底102和位于封装衬底102上方的半导体管芯104断裂、弯曲、翘曲和/或类似故障等。
图6示出根据本发明各种实施例的从封装衬底卸离伪块状件之后图5示出的半导体器件的截面图。可以使用各种卸离工艺将伪块状件402从封装衬底102分离。在一些实施例中，各种卸离工艺可以包括化学溶剂、UV曝光和/或类似工艺。
图7示出根据本发明各种实施例的将切割工艺应用到图6示出的半导体器件之后的单个芯片封装件。切割工艺是本领域已知的，因此不再详细论述。在单个的芯片封装件的顶部接合顶部封装件112以形成堆叠封装件(如图7所示)。以上参考图1描述了堆叠封装件的详细结构，因此不再论述以避免重复。
图8-12是根据另一实施例的处于制造堆叠封装半导体器件的中间阶段的截面图。图8示出的实施例的初始步骤与图3示出的制造步骤相同，因此不再论述以避免重复。
除了图9示出的伪块状件902是倒梯形而不是矩形之外，图9-12类似于图4-7。以上参考图5-7描述了图10示出的模塑料层沉积工艺、图11示出的卸离工艺和图12示出的切割工艺，因此不再论述以避免重复。
图12示出根据本发明各种实施例的将切割工艺应用到图11示出的半导体器件之后的单个芯片封装件的截面图。除了在模塑料层106的每一侧有斜坡(例如，斜坡1102或斜坡1104)而不是台阶之外，半导体器件的结构类似于图7示出的结构。换句话说，模塑料层106可以是梯形。斜坡(例如斜坡1102)和封装衬底可以形成角。该角被称为模塑料层106的侧壁角。在一些实施例中，侧壁角处于约50度至约80度的范围。
图13示出根据本发明各种实施例的另一单个芯片封装件的截面图。如图13所示，单个芯片封装件的截面图类似于图12示出的单个芯片封装件的截面图，除了模塑料层106是相同侧的角部被剪切的矩形(如图12所示)之外。换句话说，模塑料层106的截面图由矩形部分和梯形部分的组合形成。
如图13所示，在矩形部分上堆叠梯形部分。图13的梯形部分类似于图12示出的梯形的模塑料层。梯形部分具有角1302。在一些实施例中，角1302处于约50度至约80度的范围。应该注意，图7、图12和图13中的模塑料层的形状仅仅是实例。其他形状也包括在模塑料层106的各种实施例的范围和精神内。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的构思和范围的情况下，进行各种改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (17)

1.一种半导体器件，包括：
封装部件，包括：
多个凸块，形成在所述封装部件上；
半导体管芯，安装在所述封装部件上；
介电材料，形成在所述封装部件上方，所述封装部件的顶面在顶视图中仅四个角部没有所述介电材料；以及
顶部封装件，接合在所述封装部件上，所述半导体管芯位于所述顶部封装件和所述封装部件之间；
其中，所述介电材料形成位于所述封装部件上方的模塑料层，并且所述半导体管芯嵌入在所述模塑料层中；
其中，所述模塑料层是梯形，或者所述模塑料层的截面是剪切同一侧角部的矩形，并且所述剪切同一侧角部的矩形包括：
矩形；以及
梯形，位于所述矩形上方。
2.根据权利要求1所述的半导体器件，其中，所述梯形具有范围在50度至80度之间的内角。
3.根据权利要求1所述的半导体器件，其中，所述封装部件是封装衬底。
4.根据权利要求1所述的半导体器件，其中，所述封装部件的顶面的四个边缘区域没有所述介电材料，每一个边缘区域的宽度均等于50um。
5.根据权利要求1所述的半导体器件，其中，每个角部的形状都是三角形。
6.根据权利要求5所述的半导体器件，其中，
所述三角形的第一边的第一尺寸大于或等于所述凸块的节距的一半；以及
所述三角形的第二边垂直于所述第一边，所述第二边的第二尺寸大于或等于所述凸块的节距的一半。
7.一种制造半导体器件的方法，包括：
在封装衬底的顶面的子部中设置半导体管芯；
在所述子部的四个角部处设置伪块状件；
在所述封装衬底的顶面上形成多个凸块，以行和列的方式布置所述多个凸块；
在所述封装衬底的顶面上方沉积密封层，所述半导体管芯嵌入到所述密封层中；
从所述封装衬底卸离所述伪块状件；
将所述封装衬底切割成多个芯片封装件；以及
将顶部封装件连接至所述封装衬底，其中：
在所述封装衬底和所述顶部封装件之间设置所述半导体管芯；并且
所述顶部封装件和所述封装衬底通过所述凸块连接在一起；
其中，所述伪块状件的顶面的长度大于所述伪块状件的底面的长度，并且所述伪块状件仅设置在每个所述封装衬底的子部的四个角部上。
8.根据权利要求7所述的方法，进一步包括：
将释放层附接在所述封装衬底的每一个角部上方；
将所述伪块状件通过所述释放层附接至所述封装衬底；以及
对所述封装衬底实施释放工艺以卸离所述伪块状件。
9.根据权利要求7所述的方法，进一步包括：
将释放层附接在所述封装衬底的顶面的边缘区域上方；
将所述边缘区域的伪块状件通过所述释放层附接至所述封装衬底；以及
对所述封装衬底实施释放工艺以卸离所述边缘区域的伪块状件。
10.根据权利要求7所述的方法，进一步包括：
将环形的伪块状件附接在所述封装衬底的顶面上，其中所述环形的伪块状件覆盖所述封装衬底的子部中的四个角部和四个边缘区域。
11.一种制造半导体器件的方法，包括：
在衬底的第一侧上附接第一半导体管芯；
在所述衬底的所述第一侧上附接第二半导体管芯；
在所述第一半导体管芯和所述第二半导体管芯之间附接伪块状件；
在所述衬底的第一侧上方沉积模塑料层，其中所述第一半导体管芯、所述第二半导体管芯和所述伪块状件嵌入在所述模塑料层中；以及
从所述衬底卸离所述伪块状件；
其中，所述伪块状件的顶面的长度大于所述伪块状件的底面的长度并且所述伪块状件仅设置在每个所述衬底的四个角部上。
12.根据权利要求11所述的方法，进一步包括：
切割所述衬底以形成包括所述第一半导体管芯的第一芯片封装件；以及
在所述第一芯片封装件上附接顶部封装件，其中所述第一半导体管芯位于所述衬底和所述顶部封装件之间。
13.根据权利要求11所述的方法，进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件是围绕所述第一半导体管芯的环。
14.根据权利要求11所述的方法，进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件的形状是矩形。
15.根据权利要求11所述的方法，进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件的形状是倒梯形。
16.根据权利要求11所述的方法，进一步包括：将所述伪块状件附接至所述衬底，其中所述伪块状件的形状是多边形。
17.根据权利要求11所述的方法，进一步包括：
通过多个第一微凸块将所述第一半导体管芯附接在所述衬底上；以及
通过多个第二微凸块将所述第二半导体管芯附接在所述衬底上。
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