CN103871452B - 使用前端预充电的存储器和方法 - Google Patents
使用前端预充电的存储器和方法 Download PDFInfo
- Publication number
- CN103871452B CN103871452B CN201410048469.2A CN201410048469A CN103871452B CN 103871452 B CN103871452 B CN 103871452B CN 201410048469 A CN201410048469 A CN 201410048469A CN 103871452 B CN103871452 B CN 103871452B
- Authority
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- China
- Prior art keywords
- subgroup
- memory element
- precharge
- bit lines
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000004044 response Effects 0.000 claims abstract description 17
- 230000000977 initiatory effect Effects 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 1
- 239000011159 matrix material Substances 0.000 description 17
- 238000004891 communication Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
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- 230000008859 change Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
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- 230000006872 improvement Effects 0.000 description 2
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- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Secondary Cells (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
- Pit Excavations, Shoring, Fill Or Stabilisation Of Slopes (AREA)
- Measurement Of Force In General (AREA)
- Underground Structures, Protecting, Testing And Restoring Foundations (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
- Vehicle Body Suspensions (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US81929606P | 2006-07-07 | 2006-07-07 | |
| US60/819,296 | 2006-07-07 | ||
| US11/771,853 US7724593B2 (en) | 2006-07-07 | 2007-06-29 | Memories with front end precharge |
| US11/771,853 | 2007-06-29 | ||
| CN200780031629.0A CN101542629B (zh) | 2006-07-07 | 2007-07-06 | 存储器设备和计算系统 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780031629.0A Division CN101542629B (zh) | 2006-07-07 | 2007-07-06 | 存储器设备和计算系统 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103871452A CN103871452A (zh) | 2014-06-18 |
| CN103871452B true CN103871452B (zh) | 2017-03-01 |
Family
ID=38895499
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780031629.0A Active CN101542629B (zh) | 2006-07-07 | 2007-07-06 | 存储器设备和计算系统 |
| CN201410048469.2A Active CN103871452B (zh) | 2006-07-07 | 2007-07-06 | 使用前端预充电的存储器和方法 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780031629.0A Active CN101542629B (zh) | 2006-07-07 | 2007-07-06 | 存储器设备和计算系统 |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP2041750B1 (enExample) |
| JP (2) | JP5209619B2 (enExample) |
| KR (1) | KR101088548B1 (enExample) |
| CN (2) | CN101542629B (enExample) |
| AT (1) | ATE479186T1 (enExample) |
| DE (1) | DE602007008729D1 (enExample) |
| WO (1) | WO2008006075A2 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7755961B2 (en) * | 2006-07-07 | 2010-07-13 | Rao G R Mohan | Memories with selective precharge |
| US7995409B2 (en) * | 2007-10-16 | 2011-08-09 | S. Aqua Semiconductor, Llc | Memory with independent access and precharge |
| US20160141020A1 (en) * | 2014-11-18 | 2016-05-19 | Mediatek Inc. | Static random access memory free from write disturb and testing method thereof |
| CN105701040B (zh) * | 2014-11-28 | 2018-12-07 | 杭州华为数字技术有限公司 | 一种激活内存的方法及装置 |
| US10373665B2 (en) | 2016-03-10 | 2019-08-06 | Micron Technology, Inc. | Parallel access techniques within memory sections through section independence |
| CN108962324B (zh) * | 2017-05-24 | 2020-12-15 | 华邦电子股份有限公司 | 存储器存储装置 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5636174A (en) * | 1996-01-11 | 1997-06-03 | Cirrus Logic, Inc. | Fast cycle time-low latency dynamic random access memories and systems and methods using the same |
| US5657285A (en) * | 1995-07-14 | 1997-08-12 | Cirrus Logic, Inc. | Pipelined address memories, and systems and methods using the same |
| CN1199229A (zh) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | 含有选择性预充电电路的低功率存储器 |
| CN1392566A (zh) * | 2001-06-15 | 2003-01-22 | 三菱电机株式会社 | 以低功耗工作的半导体存储器 |
| US6529412B1 (en) * | 2002-01-16 | 2003-03-04 | Advanced Micro Devices, Inc. | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge |
| US6779076B1 (en) * | 2000-10-05 | 2004-08-17 | Micron Technology, Inc. | Method and system for using dynamic random access memory as cache memory |
| EP1630814A1 (fr) * | 2004-08-26 | 2006-03-01 | STMicroelectronics SA | Procédé de lecture de cellules mémoire programmables et effacables électriquement, à précharge anticipée de lignes de bit |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS581883A (ja) * | 1981-06-25 | 1983-01-07 | Fujitsu Ltd | 低電力スタチツクｒａｍ |
| JPS63266689A (ja) * | 1987-04-24 | 1988-11-02 | Hitachi Ltd | 半導体メモリ |
| US4845677A (en) * | 1987-08-17 | 1989-07-04 | International Business Machines Corporation | Pipelined memory chip structure having improved cycle time |
| JPH02128249A (ja) * | 1988-11-09 | 1990-05-16 | Hitachi Ltd | 記憶制御方式 |
| JPH04162665A (ja) * | 1990-10-26 | 1992-06-08 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JPH0512873A (ja) * | 1991-07-05 | 1993-01-22 | Fujitsu Ltd | 半導体記憶装置 |
| JPH0644784A (ja) * | 1991-12-13 | 1994-02-18 | Kawasaki Steel Corp | 半導体スタティックメモリ |
| JP3481263B2 (ja) * | 1992-02-19 | 2003-12-22 | 株式会社リコー | シリアル記憶装置 |
| JPH06119793A (ja) * | 1992-10-07 | 1994-04-28 | Matsushita Electric Ind Co Ltd | 読み出し専用記憶装置 |
| JP3559312B2 (ja) * | 1994-06-30 | 2004-09-02 | 松下電器産業株式会社 | Ｒｏｍ装置 |
| JP2773663B2 (ja) * | 1994-12-27 | 1998-07-09 | ヤマハ株式会社 | 半導体記憶装置 |
| JP2773665B2 (ja) * | 1994-12-28 | 1998-07-09 | ヤマハ株式会社 | 半導体記憶装置 |
| US5630174A (en) * | 1995-02-03 | 1997-05-13 | Cirrus Logic, Inc. | Adapter for detecting whether a peripheral is standard or multimedia type format and selectively switching the peripheral to couple or bypass the system bus |
| KR0147706B1 (ko) * | 1995-06-30 | 1998-09-15 | 김주용 | 고속 동기형 마스크 롬 |
| US6061759A (en) * | 1996-02-09 | 2000-05-09 | Apex Semiconductor, Inc. | Hidden precharge pseudo cache DRAM |
| JPH1011969A (ja) * | 1996-06-21 | 1998-01-16 | Toshiba Microelectron Corp | 半導体記憶装置 |
| JPH10106264A (ja) * | 1996-09-26 | 1998-04-24 | Nec Corp | 半導体記憶装置 |
| US6314049B1 (en) * | 2000-03-30 | 2001-11-06 | Micron Technology, Inc. | Elimination of precharge operation in synchronous flash memory |
| JP2003271445A (ja) * | 2002-03-15 | 2003-09-26 | Sony Corp | メモリ制御装置及び方法 |
| US6834023B2 (en) | 2002-08-01 | 2004-12-21 | Micron Technology, Inc. | Method and apparatus for saving current in a memory device |
| US7154795B2 (en) * | 2004-07-30 | 2006-12-26 | United Memories, Inc. | Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM |
| JP2007035169A (ja) * | 2005-07-27 | 2007-02-08 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| US7755961B2 (en) * | 2006-07-07 | 2010-07-13 | Rao G R Mohan | Memories with selective precharge |
| US7995409B2 (en) * | 2007-10-16 | 2011-08-09 | S. Aqua Semiconductor, Llc | Memory with independent access and precharge |
-
2007
- 2007-07-06 EP EP07812687A patent/EP2041750B1/en active Active
- 2007-07-06 KR KR1020097002540A patent/KR101088548B1/ko active Active
- 2007-07-06 CN CN200780031629.0A patent/CN101542629B/zh active Active
- 2007-07-06 WO PCT/US2007/072974 patent/WO2008006075A2/en not_active Ceased
- 2007-07-06 AT AT07812687T patent/ATE479186T1/de not_active IP Right Cessation
- 2007-07-06 CN CN201410048469.2A patent/CN103871452B/zh active Active
- 2007-07-06 JP JP2009518644A patent/JP5209619B2/ja active Active
- 2007-07-06 DE DE602007008729T patent/DE602007008729D1/de active Active
-
2012
- 2012-10-16 JP JP2012229226A patent/JP2013037760A/ja active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5657285A (en) * | 1995-07-14 | 1997-08-12 | Cirrus Logic, Inc. | Pipelined address memories, and systems and methods using the same |
| US5636174A (en) * | 1996-01-11 | 1997-06-03 | Cirrus Logic, Inc. | Fast cycle time-low latency dynamic random access memories and systems and methods using the same |
| CN1199229A (zh) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | 含有选择性预充电电路的低功率存储器 |
| US6779076B1 (en) * | 2000-10-05 | 2004-08-17 | Micron Technology, Inc. | Method and system for using dynamic random access memory as cache memory |
| CN1392566A (zh) * | 2001-06-15 | 2003-01-22 | 三菱电机株式会社 | 以低功耗工作的半导体存储器 |
| US6529412B1 (en) * | 2002-01-16 | 2003-03-04 | Advanced Micro Devices, Inc. | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge |
| EP1630814A1 (fr) * | 2004-08-26 | 2006-03-01 | STMicroelectronics SA | Procédé de lecture de cellules mémoire programmables et effacables électriquement, à précharge anticipée de lignes de bit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008006075A3 (en) | 2008-10-02 |
| CN103871452A (zh) | 2014-06-18 |
| KR20090032112A (ko) | 2009-03-31 |
| DE602007008729D1 (de) | 2010-10-07 |
| EP2041750A2 (en) | 2009-04-01 |
| JP2013037760A (ja) | 2013-02-21 |
| ATE479186T1 (de) | 2010-09-15 |
| CN101542629A (zh) | 2009-09-23 |
| EP2041750B1 (en) | 2010-08-25 |
| KR101088548B1 (ko) | 2011-12-05 |
| WO2008006075A2 (en) | 2008-01-10 |
| JP2009543269A (ja) | 2009-12-03 |
| CN101542629B (zh) | 2014-02-26 |
| EP2041750A4 (en) | 2009-09-09 |
| JP5209619B2 (ja) | 2013-06-12 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |