DE602007008729D1 - Speichereinheiten mit front-end-vorladung - Google Patents

Speichereinheiten mit front-end-vorladung

Info

Publication number
DE602007008729D1
DE602007008729D1 DE602007008729T DE602007008729T DE602007008729D1 DE 602007008729 D1 DE602007008729 D1 DE 602007008729D1 DE 602007008729 T DE602007008729 T DE 602007008729T DE 602007008729 T DE602007008729 T DE 602007008729T DE 602007008729 D1 DE602007008729 D1 DE 602007008729D1
Authority
DE
Germany
Prior art keywords
memory cells
load
storage units
end pre
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007008729T
Other languages
English (en)
Inventor
Mohan G R Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S Aqua Semiconductor LLC
Original Assignee
S Aqua Semiconductor LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/771,853 external-priority patent/US7724593B2/en
Application filed by S Aqua Semiconductor LLC filed Critical S Aqua Semiconductor LLC
Publication of DE602007008729D1 publication Critical patent/DE602007008729D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Vehicle Body Suspensions (AREA)
  • Underground Structures, Protecting, Testing And Restoring Foundations (AREA)
  • Pit Excavations, Shoring, Fill Or Stabilisation Of Slopes (AREA)
  • Measurement Of Force In General (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)
DE602007008729T 2006-07-07 2007-07-06 Speichereinheiten mit front-end-vorladung Active DE602007008729D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US81929606P 2006-07-07 2006-07-07
US11/771,853 US7724593B2 (en) 2006-07-07 2007-06-29 Memories with front end precharge
PCT/US2007/072974 WO2008006075A2 (en) 2006-07-07 2007-07-06 Memories with front end precharge

Publications (1)

Publication Number Publication Date
DE602007008729D1 true DE602007008729D1 (de) 2010-10-07

Family

ID=38895499

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007008729T Active DE602007008729D1 (de) 2006-07-07 2007-07-06 Speichereinheiten mit front-end-vorladung

Country Status (7)

Country Link
EP (1) EP2041750B1 (de)
JP (2) JP5209619B2 (de)
KR (1) KR101088548B1 (de)
CN (2) CN101542629B (de)
AT (1) ATE479186T1 (de)
DE (1) DE602007008729D1 (de)
WO (1) WO2008006075A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7755961B2 (en) * 2006-07-07 2010-07-13 Rao G R Mohan Memories with selective precharge
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US20160141020A1 (en) * 2014-11-18 2016-05-19 Mediatek Inc. Static random access memory free from write disturb and testing method thereof
CN105701040B (zh) 2014-11-28 2018-12-07 杭州华为数字技术有限公司 一种激活内存的方法及装置
US10373665B2 (en) 2016-03-10 2019-08-06 Micron Technology, Inc. Parallel access techniques within memory sections through section independence

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581883A (ja) * 1981-06-25 1983-01-07 Fujitsu Ltd 低電力スタチツクｒａｍ
JPS63266689A (ja) * 1987-04-24 1988-11-02 Hitachi Ltd 半導体メモリ
US4845677A (en) * 1987-08-17 1989-07-04 International Business Machines Corporation Pipelined memory chip structure having improved cycle time
JPH02128249A (ja) * 1988-11-09 1990-05-16 Hitachi Ltd 記憶制御方式
JPH04162665A (ja) * 1990-10-26 1992-06-08 Matsushita Electric Ind Co Ltd 半導体記憶装置
JPH0512873A (ja) * 1991-07-05 1993-01-22 Fujitsu Ltd 半導体記憶装置
JPH0644784A (ja) * 1991-12-13 1994-02-18 Kawasaki Steel Corp 半導体スタティックメモリ
JP3481263B2 (ja) * 1992-02-19 2003-12-22 株式会社リコー シリアル記憶装置
JPH06119793A (ja) * 1992-10-07 1994-04-28 Matsushita Electric Ind Co Ltd 読み出し専用記憶装置
JP3559312B2 (ja) * 1994-06-30 2004-09-02 松下電器産業株式会社 Ｒｏｍ装置
JP2773665B2 (ja) * 1994-12-28 1998-07-09 ヤマハ株式会社 半導体記憶装置
JP2773663B2 (ja) * 1994-12-27 1998-07-09 ヤマハ株式会社 半導体記憶装置
US5630174A (en) * 1995-02-03 1997-05-13 Cirrus Logic, Inc. Adapter for detecting whether a peripheral is standard or multimedia type format and selectively switching the peripheral to couple or bypass the system bus
KR0147706B1 (ko) * 1995-06-30 1998-09-15 김주용 고속 동기형 마스크 롬
US5598374A (en) * 1995-07-14 1997-01-28 Cirrus Logic, Inc. Pipeland address memories, and systems and methods using the same
US5636174A (en) * 1996-01-11 1997-06-03 Cirrus Logic, Inc. Fast cycle time-low latency dynamic random access memories and systems and methods using the same
US6061759A (en) * 1996-02-09 2000-05-09 Apex Semiconductor, Inc. Hidden precharge pseudo cache DRAM
JPH1011969A (ja) * 1996-06-21 1998-01-16 Toshiba Microelectron Corp 半導体記憶装置
JPH10106264A (ja) * 1996-09-26 1998-04-24 Nec Corp 半導体記憶装置
US5828610A (en) * 1997-03-31 1998-10-27 Seiko Epson Corporation Low power memory including selective precharge circuit
US6314049B1 (en) * 2000-03-30 2001-11-06 Micron Technology, Inc. Elimination of precharge operation in synchronous flash memory
US6779076B1 (en) * 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
JP5041631B2 (ja) * 2001-06-15 2012-10-03 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6529412B1 (en) * 2002-01-16 2003-03-04 Advanced Micro Devices, Inc. Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
JP2003271445A (ja) * 2002-03-15 2003-09-26 Sony Corp メモリ制御装置及び方法
US6834023B2 (en) 2002-08-01 2004-12-21 Micron Technology, Inc. Method and apparatus for saving current in a memory device
US7154795B2 (en) * 2004-07-30 2006-12-26 United Memories, Inc. Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM
FR2874734A1 (fr) * 2004-08-26 2006-03-03 St Microelectronics Sa Procede de lecture de cellules memoire programmables et effacables electriquement, a precharge anticipee de lignes de bit
JP2007035169A (ja) * 2005-07-27 2007-02-08 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7755961B2 (en) * 2006-07-07 2010-07-13 Rao G R Mohan Memories with selective precharge
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge

Also Published As

Publication number Publication date
JP2013037760A (ja) 2013-02-21
WO2008006075A3 (en) 2008-10-02
EP2041750A4 (de) 2009-09-09
EP2041750B1 (de) 2010-08-25
JP5209619B2 (ja) 2013-06-12
ATE479186T1 (de) 2010-09-15
CN101542629A (zh) 2009-09-23
JP2009543269A (ja) 2009-12-03
WO2008006075A2 (en) 2008-01-10
CN101542629B (zh) 2014-02-26
EP2041750A2 (de) 2009-04-01
KR20090032112A (ko) 2009-03-31
CN103871452A (zh) 2014-06-18
CN103871452B (zh) 2017-03-01
KR101088548B1 (ko) 2011-12-05

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