CN103855037A - 电子部件安装基板及其制造方法 - Google Patents

电子部件安装基板及其制造方法 Download PDF

Info

Publication number
CN103855037A
CN103855037A CN201310625260.3A CN201310625260A CN103855037A CN 103855037 A CN103855037 A CN 103855037A CN 201310625260 A CN201310625260 A CN 201310625260A CN 103855037 A CN103855037 A CN 103855037A
Authority
CN
China
Prior art keywords
metallic plate
silver
electronic components
components packaging
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310625260.3A
Other languages
English (en)
Other versions
CN103855037B (zh
Inventor
砂地直也
小山内英世
栗田哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dowa Metaltech Co Ltd
Original Assignee
Dowa Metaltech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dowa Metaltech Co Ltd filed Critical Dowa Metaltech Co Ltd
Publication of CN103855037A publication Critical patent/CN103855037A/zh
Application granted granted Critical
Publication of CN103855037B publication Critical patent/CN103855037B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/06—Alloys based on silver
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C24/00—Coating starting from inorganic powder
    • C23C24/08—Coating starting from inorganic powder by application of heat or pressure and heat
    • C23C24/10—Coating starting from inorganic powder by application of heat or pressure and heat with intermediate formation of a liquid phase in the layer
    • C23C24/103—Coating with metallic material, i.e. metals or metal alloys, optionally comprising hard particles, e.g. oxides, carbides or nitrides
    • C23C24/106—Coating with metal alloys or metal elements only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29399—Coating material
    • H01L2224/2949—Coating material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H01L2224/81075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/83054—Composition of the atmosphere
    • H01L2224/83075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83464—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/203—Ultrasonic frequency ranges, i.e. KHz
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12472—Microscopic interfacial wave or roughness

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Powder Metallurgy (AREA)
  • Die Bonding (AREA)
  • Laminated Bodies (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Ceramic Products (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明提供一种电子部件安装基板，包括：大致具有矩形平面形状的铝或铝合金的（用于安装电子部件的）金属板（10），该金属板（10）的一个主面经表面处理从而具有不低于0.2微米的表面粗糙度；形成在金属板（10）的一个主面上的镍或镍合金的镀膜（20）；通过（含有银的烧结体的）银粘接层（12）与镀膜（20）相接合的电子部件（14）；大致具有矩形平面形状的陶瓷基板（16），该陶瓷基板（16）的一个主面与金属板（10）的另一主面相接合；以及与陶瓷基板（16）的另一主面相接合的散热金属板（金属底板）（18）。

Description

电子部件安装基板及其制造方法
技术领域
本发明主要涉及电子部件安装基板及其制造方法。更详细而言，本发明涉及如下这种电子部件安装基板及其制造方法，即，在金属/陶瓷接合基板的铝或铝合金的金属板的一侧安装有半导体芯片等至少一个电子部件，该金属板的另一侧与陶瓷基板接合。
背景技术
功率模块被用于控制电动汽车、有轨电车、机床等中的大电流。在传统的功率模块中，将金属/陶瓷绝缘基板固定于金属板或复合材料底板的一侧，并通过焊接将半导体芯片固定在金属/陶瓷绝缘基板的金属电路板上。
近年来，提出了使用含微小银粒子的银膏作为物件之间的粘接剂，在将物件相互压接时加热该银膏一定时间，以对粘接剂中的银进行烧结，从而使物件相互接合（例如，参考日本专利公开No.2011-80147）。其试图用粘接剂代替焊料将半导体芯片等电子部件固定在金属/陶瓷绝缘基板的金属板上。
然而，若将日本专利公开No.2011-80147所公开的含微小银粒子的银膏用作粘接剂，则无法获得足够的接合强度，除非要接合的物件是由铜制成，或是镀敷有昂贵的贵金属，例如金、银或钯。因此，在（用于安装电子部件的）铝或铝合金的金属板与陶瓷基板相接合的金属/陶瓷绝缘基板的情况下，或在（用于安装电子部件的）铝或铝合金的金属板上镀敷有镍或镍合金来与陶瓷基板相接合的陶瓷/金属绝缘基板的情况下，无法使用日本专利公开No.2011-80147所公开的含微小银粒子的银膏来用作为有足够的接合力将半导体芯片等电子部件与（用于安装电子部件的）金属板相接合的粘接剂。
发明内容
因此，本发明的目的在于解决上述问题，提供一种有足够的接合力将电子部件与铝或铝合金的金属板相接合的电子部件安装基板及其制造方法。
为了实现上述及其它目的，本发明人经过不懈的努力发现，若利用对银膏中的银进行烧结而形成的银粘接层将电子部件与金属板的一侧相接合，则有足够的接合力将电子部件与铝或铝合金的金属板相接合，其中，是在对金属板的一侧进行表面加工使其表面粗糙度不低于0.2微米后，将该银膏涂布在金属板的一侧，并在其上设置电子部件。由此，发明人实现了本发明。
根据本发明的一个方面，提供了一种电子部件安装基板的制造方法，该电子部件安装基板在铝或铝合金的金属板的一侧安装有电子部件，所述方法包括如下步骤：对金属板的一侧进行表面加工从而使其表面粗糙度达到0.2微米以上；在金属板的经表面加工的一侧涂布银膏；在涂布于金属板的经表面加工的一侧的银膏上设置电子部件；以及对银膏中的银进行烧结来形成银粘接层，从而利用该银粘接层使电子部件与金属板的经表面加工的一侧相接合。
在该电子部件安装基板的制造方法中，优选通过在将电子部件与金属板压接的同时对银膏进行加热来进行烧结。优选在进行表面加工后但涂布银膏之前，对金属板的经表面加工的一侧镀敷镍或镍合金。该表面加工优选为喷砂或研磨加工。与金属板的经表面加工的一侧相接合的电子部件的表面优选覆盖有能与银膏相接合的金属。在该情况下，能与银膏相接合的金属优选为从金、银、铜、钯、或它们的合金所构成的组中选出的至少一种金属。与金属板的经表面加工的一侧相接合的电子部件的表面可以镀敷有从金、银、钯、或它们的合金所构成的组中选出的至少一种金属。优选将金属板的另一侧与陶瓷基板的一侧相接合。在该情况下，优选将陶瓷基板的另一侧与金属底板相接合。
根据本发明的另一个方面，提供了一种电子部件安装基板，包括：铝或铝合金的金属板，该金属板的一侧具有不低于0.2微米的表面粗糙度；形成在金属板的一侧的银粘接层；以及通过该银粘接层与该金属板的一侧相接合的电子部件。
在该电子部件安装基板中，优选在金属板的一侧形成有镍或镍合金的镀膜，并优选利用银粘接层并经由镀膜使电子部件与金属板的一侧相接合。在该情况下，该镀膜优选具有不低于0.4微米的表面粗糙度。与金属板的一侧相接合的电子部件的表面优选覆盖有能与银粘接层相接合的金属。在该情况下，能与银粘接层相接合的金属优选为从金、银、铜、钯、或它们的合金所构成的组中选出的至少一种金属。与金属板的一侧相接合的电子部件的表面可以镀敷有从金、银、钯、或它们的合金所构成的组中选出的至少一种金属。银粘接层优选含有银的烧结体。优选将金属板的另一侧与陶瓷基板的一侧相接合。在该情况下，优选将陶瓷基板的另一侧与金属底板相接合。
根据本发明，在金属板的一侧安装有电子部件的电子部件安装基板的制造方法中，有足够的接合力使电子部件与铝或铝合金的金属板相接合。
附图说明
根据以下给出的详细描述以及本发明优选实施方式的附图，能够更充分地理解本发明。然而，附图并非为了将本发明限定为具体的实施方式，而仅用于解释和理解。
在附图中：
图1是示意性示出本发明所涉及的电子部件安装基板的一个优选实施方式的剖视图。
图2是图1的电子部件安装基板的立体图。
具体实施方式
现在参照附图，对本发明所涉及的电子部件安装基板及其制造方法的优选实施方式进行说明。
如图1和图2所示，在电子部件安装基板的一个优选实施方式中，电子部件14通过（含有银烧结体的）银粘接层12与大致具有矩形平面形状的（用于安装电子部件的）金属板10的一个主面相接合。金属板10的另一主面与大致具有矩形平面形状的陶瓷基板16的一个主面相接合。陶瓷基板16的另一主面与大致具有矩形平面形状的散热金属板（金属底板）18相接。金属板10的一个主面上镀敷有镍或镍合金，从而在其上形成镍或镍合金的镀膜20，并通过银粘接层12在其上接合电子部件14。
此外，金属板10由铝或铝合金形成。金属板10的（要接合电子部件14的）一个主面的表面粗糙度不小于0.2μm，优选在0.3μm～2.0μm的范围内。当形成了镍或镍合金的镀膜20时，若镀膜20的表面粗糙度小于0.4μm，则将难以利用银粘接层12使电子部件14与该镀膜20接合。因此，优选镀膜20的表面粗糙度不小于0.4μm，更优选在0.5μm～2.0μm的范围内。
优选与金属板10的一个主面接合的电子部件14的表面覆盖有能与银粘接层12接合的金属，例如是从金、银、铜、钯、或其合金所构成的组中选出的至少一种金属，并优选为从金、银、钯、或其合金所构成的组中选出的至少一种金属。
在本发明所涉及的电子部件安装基板的制造方法的一个优选实施方式中，制造了在铝或铝合金的金属板10的一个主面上安装有电子部件14的电子部件安装基板。该方法中，对金属板10的一个主面进行加工，使其表面粗糙度不小于0.2μm，优选在0.3μm～2.0μm的范围内。在将银膏涂布在加工后的主面上并在该银膏上设置电子部件14后，对银膏中的银进行烧结来形成银粘接层12，从而利用该银粘接层12使电子部件14与金属板10的一个主面相接合。
此外，优选通过在将电子部件14与金属板10压接的同时进行加热，从而对银膏中的银进行烧结。烧结过程中的加热温度优选在200℃～400℃的范围内，更优选在220℃～300℃的范围内。烧结过程中的加热时间优选在1分钟～10分钟的范围内。烧结过程中施加的压力可以在10MPa以下，优选在2MPa～10MPa的范围内，更优选在3MPa～8MPa的范围内。
金属板10的一个主面与大致具有矩形平面形状的陶瓷基板16的一个主面相接合，陶瓷基板16的一个主面与大致具有矩形平面形状的散热金属板（金属底板）18相接合。该情况下，在对金属板10与陶瓷基板16之间、以及陶瓷基板16与金属底板18之间进行接合后，对金属板10的一个主面（要与电子部件14接合的表面）进行加工来在其上涂布银膏，并在银膏上设置电子部件14，然后对银膏中的银进行烧结来形成银粘接层12，从而利用该银粘接层12使电子部件14与金属板10的一个主面相接合。金属板10与陶瓷基板16之间、以及陶瓷基板16与金属底板18之间的接合优选通过包含以下步骤的方法来进行：在模具（未图示）中设置陶瓷基板16；将铝或铝合金的熔融金属注入到该模具中从而使熔融金属与所设置的陶瓷基板16的两个主面相接触；使所注入的熔融金属冷却并固化来分别在陶瓷基板16的主面上形成金属板10以及金属底板18，使它们直接与陶瓷基板16相接合。
在对金属板10的一个主面进行加工后但在该主面上涂布银膏之前，对金属板10的一个主面进行镀敷，来形成具有0.1～10μm、优选为0.5～6μm厚度的镍或镍合金的镀膜20。若形成这种镀膜20，则该镀膜20的表面粗糙度优选为0.4μm以上，更优选在0.5μm～2.0μm的范围内。
表面加工优选通过喷砂（例如湿式喷砂，在金属板的表面喷洒含有微小粒子的磨料浆）或研磨加工（例如利用作为磨粒的研磨剂对设置在研磨机上的金属板进行滑动和研磨，并同时对该金属板进行加压）来进行。
银膏可以是含有能在不高于400℃的温度下进行烧结的微小银粒子的糊料，优选为将涂敷了具有8个以下（优选为6～8个）碳原子的有机化合物的平均一次粒径为1～200nm的微小银粒子分散在分散介质（优选为极性分散介质）中而得到的粘接剂（例如市售的同和电子材料有限公司制的PA-HT-1503M-C）。银膏也可以是将平均一次粒径（D50直径）为0.5～3.0μm的银粒子分散在已分散有微小银粒子的分散介质中而得到的粘接剂（例如市售的同和电子材料有限公司制的PA-HT-1001L）。
在本发明所涉及的电子部件安装基板的制造方法的优选实施方式中，若在对银膏中的银进行烧结时在大约5～7MPa的低压下进行加压，同时在大约250～260℃的低温下对银膏进行加热，则能以足够的接合力使电子部件与铝或铝合金的金属板相接合（不会形成任何接合缺陷，例如接合部的间隙）。
在整个说明书中，“表面粗糙度”是指基于JIS B0601(2001)计算出的算术表面粗糙度Ra，“银粒子的平均一次粒径（D50直径）”是指利用激光衍射仪测量出的银粒子的50%粒径（D50直径）（累计50%重量的银粒子的直径），“微小银粒子的平均一次粒径”是指从透射电子显微镜的图像（TEM图像）获得的微小银粒子的一次粒径的平均值。
下面，对电子部件安装基板及其制造方法的实施方式进行详细说明。
实施例1
首先，在模具中设置尺寸为78mm×95mm×0.6mm的AlN陶瓷基板，并将纯度为99.9%（重量）的铝的熔融金属注入到模具中从而与陶瓷基板的两个主面相接触。然后，使该熔融金属冷却并固化从而在主面上分别形成尺寸为68mm×85mm×0.2mm的（用于安装电子部件的）金属板以及尺寸为68mm×85mm×0.2mm的（用于散热的）金属底板，并分别将它们直接与陶瓷基板的主面相接合。
然后，利用（Macoho有限公司制的型号No.NFR-737的市售的）湿式喷砂设备对（用于安装电子部件的）金属板进行表面处理。湿式喷砂设备的处理条件为：气压0.2Mpa，吞吐速度0.3m/min。此外，喷射距离为20mm，喷射角度为90°。另外，使用了在水中含有15%（体积）的平均粒径为40μm的氧化铝#320作为磨粒的磨料浆。对于利用喷砂进行处理的（用于安装电子部件的）金属板，通过超深度表面轮廓测量显微镜（或彩色激光显微镜）（市售的基恩士公司制的VK-8500）来测量与金属板的表面上尺寸为100μm×100μm的可选方形区域的一侧相平行的长度为100μm的可选直线上的线粗糙度。基于JIS B0601(2001)，根据测量到的线粗糙度计算表面粗糙度（算术表面粗糙度Ra）。其结果，表面粗糙度为1.19μm。
然后，通过进行两次锌酸盐转换的双锌酸盐（double zincate）转换工艺来对金属板进行预处理，之后将该金属板浸入到无电镀镍溶液（市售的上村（Uyemura）有限公司生产的NIMUDEN SX）中，从而在（用于安装电子部件的）金属板的表面形成厚度为5μm的Ni-P无电镀膜。以和上述相同的方法测量由此形成的镀膜的表面粗糙度。其结果，该镀膜的表面粗糙度为1.00μm。
然后，将含有分散在分散介质中的微小银粒子和散介质中的银粒子的银膏（市售的同和电子材料有限公司制的PA-HT-1001L）涂布在（用于安装电子部件的）金属板表面的镀膜的电子部件安装部分，之后将底面（反面）镀金的Si芯片（尺寸为13mm×13mm）设置在电子部件安装部分的银膏上。然后，在100℃下对经由银膏而设置在金属板上的Si芯片进行10分钟的预热，之后隔着Si橡胶板以7MPa的压力对其进行加压的同时在260℃下加热2分钟。由此使Si芯片与（用于安装电子部件的）金属板相接合。
对于由此制造出的电子部件安装基板，利用超声波测试设备（扫描声学断层扫描仪（SAT））（市售的日立建机精科有限公司制的FS100II）对Si芯片与（用于安装电子部件的）金属板的接合部分进行观察。其结果，未在接合部分发现剥离。
实施例2
除了用纯度为99.99%（重量）的铝的熔融金属来代替纯度为99.9%（重量）的铝的熔融金属以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.36μm，镀膜的表面粗糙度为1.17μm，并且未在接合部分发现剥离。
实施例3
除了用含有0.4%（重量）的Si和0.04%（重量）的B的Al-Si-B合金的熔融金属来代替纯度为99.9%（重量）的铝的熔融金属以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.39μm，镀膜的表面粗糙度为1.38μm，并且未在接合部分发现剥离。
实施例4
除了不进行Ni-P无电镀敷和预处理以外，采用与实施例2相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.36μm，并且未在接合部分发现剥离。
实施例5
除了采用研磨加工代替湿式喷砂来作为表面处理以外，采用与实施例2相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。此外，利用单侧研磨机（SPEEDFAM公司制），使用含有平均一次粒径为20μm的氧化铝#600作为磨粒的研磨剂，在0.1kg/cm2的加工压力下进行研磨加工。其结果，金属板的表面粗糙度为0.30μm，镀膜的表面粗糙度为0.71μm，并且未在接合部分发现剥离。
实施例6
除了用含有0.4%（重量）的Si和0.04%（重量）的B的Al-Si-B合金的熔融金属来代替纯度为99.99%（重量）的铝的熔融金属以外，采用与实施例5相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.30μm，镀膜的表面粗糙度为0.54μm，并且未在接合部分发现剥离。
比较例1
除了采用磨削机（市售的迪斯科公司制的DAS8920）在湿式喷砂的位置进行磨削来作为表面处理以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.02μm，镀膜的表面粗糙度为0.24μm。在接合部分，Si芯片从（用于安装电子部件的）金属板上剥离。
比较例2
除了用纯度为99.99%（重量）的铝的熔融金属代替纯度为99.9%（重量）的铝的熔融金属并且不进行Ni-P无电镀敷和预处理以外，采用与比较例1相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.02μm，在接合部分，Si芯片从（用于安装电子部件的）金属板上剥离。
比较例3
除了采用抛光代替湿式喷砂来作为表面处理以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。此外，利用单侧抛光机（SPEEDFAM公司制），使用含有平均一次粒径为20μm的氧化铝#600作为磨粒的抛光剂，在0.1kg/cm2的加工压力下进行抛光。其结果，金属板的表面粗糙度为0.07μm，镀膜的表面粗糙度为0.13μm。在接合部分，Si芯片从（用于安装电子部件）的金属板上剥离。
比较例4
除了用纯度为99.99%（重量）的铝的熔融金属代替纯度为99.9%（重量）的铝的熔融金属以外，采用与比较例3相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.07μm，镀膜的表面粗糙度为0.12μm。在接合部分，Si芯片从（用于安装电子部件的）金属板上剥离。
比较例5
除了用含有0.4%（重量）的Si和0.04%（重量）的B的Al-Si-B合金的熔融金属来代替纯度为99.9%（重量）的铝的熔融金属以外，采用与比较例3相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.07μm，镀膜的表面粗糙度为0.16μm。在接合部分，Si芯片从（用于安装电子部件的）金属板上剥离。
比较例6
除了不进行Ni-P无电镀敷和预处理以外，采用与比较例4相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.07μm，在接合部分，Si芯片从（用于安装电子部件的）金属板上剥离。
实施例7
除了不进行Ni-P无电镀敷和预处理并且使Si芯片与金属板接合时的压力为15MPa以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为29.1。
实施例8
除了使Si芯片与金属板接合时的压力为7MPa并且在氮气气氛下使Si芯片与金属板接合以外，采用与实施例7相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为29.1。
实施例9
除了不进行Ni-P无电镀敷和预处理而是将金属板的表面浸在硫酸中作为对与陶瓷基板接合的金属板的预处理、以及在氮气气氛下使Si芯片与金属板接合以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为29.1。
实施例10
除了不进行Ni-P无电镀敷和预处理而是将金属板的表面浸在氢氟酸中作为对与陶瓷基板接合的金属板的预处理、以及在氮气气氛下使Si芯片与金属板接合以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为29.1。
实施例11
除了不进行Ni-P无电镀敷和预处理并且使用在分散介质中含有微小银粒子的银膏（市售的同和电子材料有限公司制的PA-HT-1503M-C）以外，采用与实施例1相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为29.1。
实施例12
除了不进行Ni-P无电镀敷和预处理以外，采用与实施例2相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为23.2。
实施例13
除了不进行Ni-P无电镀敷和预处理以外，采用与实施例5相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.3μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为23.2。
实施例14
采用与实施例5相同的方法，从而制作出电子部件安装部件，并计算金属板和镀膜各自的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为0.3μm，镀膜的表面粗糙度为0.7μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为23.2。
实施例15
除了使Si芯片与金属板接合时的压力为5MPa以外，采用与实施例12相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为23.2。
实施例16
除了使Si芯片与金属板接合时的压力为5MPa以外，采用与实施例7相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为29.1。
实施例17
除了不进行Ni-P无电镀敷和预处理并且使Si芯片与金属板接合时的压力为5MPa以外，采用与实施例3相同的方法，从而制作出电子部件安装部件，并计算金属板的表面粗糙度，并对接合部分进行观察。其结果，金属板的表面粗糙度为1.4μm，并且未在接合部分发现剥离。此外，金属板的维氏硬度Hv为38.0。
表1示出了这些实施例和比较例中电子部件安装基板的制造条件。表1中，ST表示表面处理，WB表示湿式喷砂，LAP表示研磨加工，GRI表示磨削，POL表示抛光，DZ表示双锌酸盐。
表1
Figure BDA0000424640330000121
对于在实施例7～17中制造出的每个电子部件安装基板，在分别重复进行热循环（在一个循环内，将基板在-40℃下保持15分钟，之后在室温下保持1分钟，然后在250℃下保持5分钟）100次、300次、500次、800次以及1000次后，对接合状态进行观察。其结果，实施例7～15中制造的电子部件安装基板的（用于安装电子部件）的金属板与Si芯片的接合令人满意，但实施例16和17所制造的电子部件安装基板的接合部分，Si芯片从（用于安装电子部件的）金属板剥离。从这些结果可知，若使Si芯片与维氏硬度Hv相对较低、例如是含有纯度为99.99%（重量）的铝的金属板这样的（用于安装电子部件的）金属板接合时的压力不低于5MPa，则即使在上述热循环之后也能获得足够的接合强度，然而，若使Si芯片与维氏硬度Hv相对较高、例如是含有纯度为99.9%（重量）的铝或Al-Si-B合金的金属板这样的（用于安装电子部件的）金属板接合时的压力为5MPa，则在上述热循环之后无法获得足够的接合强度。因此，为了制造具有这种优异耐热性、也就是在上述热循环后仍能获得足够接合强度的电子部件安装基板，优选使Si芯片与维氏硬度Hv相对较低的、例如是含有纯度为99.99%（重量）的铝的金属板这样的（用于安装电子部件的）金属板相接合。或者，优选在使Si芯片与维氏硬度Hv相对较高、例如是含有纯度为99.9%（重量）的铝或Al-Si-B合金的金属板这样的（用于安装电子部件的）金属板接合时施加更高的压力。
虽然为便于更好的理解，就优选实施方式对本发明进行了揭示，但应当理解为在不脱离本发明中心思想的范围内，可以对本发明进行各种变更。因此，本发明应当理解为包含所有可能的实施方式以及对给出的实施方式进行的修改，并能在不脱离本发明中心思想的范围内体现在所附权利要求书中。

Claims (18)

1.一种电子部件安装基板的制造方法，该电子部件安装基板在铝或铝合金的金属板的一侧安装有电子部件，该方法包括如下步骤：
对所述金属板的一侧进行表面加工从而使其表面粗糙度达到0.2微米以上；
在所述金属板的经表面加工的一侧涂布银膏；
在所述金属板的经表面加工的一侧涂布的所述银膏上设置所述电子部件；以及
对所述银膏中的银进行烧结来形成银粘接层，从而利用该银粘接层使所述电子部件与所述金属板的经表面加工的一侧相接合。
2.如权利要求1所述的电子部件安装基板的制造方法，其特征在于，在将所述电子部件与所述金属板压接的同时对所述银膏进行加热，由此来进行所述烧结。
3.如权利要求1所述的电子部件安装基板的制造方法，其特征在于，在进行所述表面加工后但在涂布所述银膏之前，对所述金属板的经表面加工的一侧镀敷镍或镍合金。
4.如权利要求1所述的电子部件安装基板的制造方法，其特征在于，所述表面加工为喷砂或研磨加工。
5.如权利要求1所述的电子部件安装基板的制造方法，其特征在于，所述电子部件的与所述金属板的经表面加工的一侧相接合的表面覆盖有能与所述银膏相接合的金属。
6.如权利要求5所述的电子部件安装基板的制造方法，其特征在于，所述能与所述银膏相接合的金属是从金、银、铜、钯、或它们的合金所构成的组中选出的至少一种金属。
7.如权利要求1所述的电子部件安装基板的制造方法，其特征在于，所述电子部件的与所述金属板的经表面加工的一侧相接合的表面镀敷有从金、银、钯、或它们的合金所构成的组中选出的至少一种金属。
8.如权利要求1所述的电子部件安装基板的制造方法，其特征在于，使所述金属板的另一侧与陶瓷基板的一侧相接合。
9.如权利要求8所述的电子部件安装基板的制造方法，其特征在于，使所述陶瓷基板的另一侧与金属底板相接合。
10.一种电子部件安装基板，包括：
铝或铝合金的金属板，该金属板的一侧具有不低于0.2微米的表面粗糙度；
形成在所述金属板的一侧的银粘接层；以及
通过所述银粘接层与所述金属板的一侧相接合的电子部件。
11.如权利要求10所述的电子部件安装基板，其特征在于，还包括形成在所述金属板的一侧的镍或镍合金的镀膜，利用所述银粘接层并经由所述镀膜使所述电子部件与所述金属板的一侧相接合。
12.如权利要求11所述的电子部件安装基板，其特征在于，所述镀膜具有不低于0.4微米的表面粗糙度。
13.如权利要求10所述的电子部件安装基板，其特征在于，所述电子部件的与所述金属板的一侧相接合的表面覆盖有能与所述银粘接层相接合的金属。
14.如权利要求13所述的电子部件安装基板，其特征在于，所述能与所述银粘接层相接合的金属是从金、银、铜、钯、或它们的合金所构成的组中选出的至少一种金属。
15.如权利要求10所述的电子部件安装基板，其特征在于，所述电子部件的与所述金属板的一侧相接合的表面镀敷有从金、银、钯、或它们的合金所构成的组中选出的至少一种金属。
16.如权利要求10所述的电子部件安装基板，其特征在于，所述银粘接层含有银的烧结体。
17.如权利要求10所述的电子部件安装基板，其特征在于，所述金属板的另一侧与陶瓷基板的一侧相接合。
18.如权利要求17所述的电子部件安装基板，其特征在于，所述陶瓷基板的另一侧与金属底板相接合。
CN201310625260.3A 2012-11-28 2013-11-28 电子部件安装基板及其制造方法 Active CN103855037B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2012259329 2012-11-28
JP2012-259329 2012-11-28
JP2013068775A JP6099453B2 (ja) 2012-11-28 2013-03-28 電子部品搭載基板およびその製造方法
JP2013-068775 2013-03-28

Publications (2)

Publication Number Publication Date
CN103855037A true CN103855037A (zh) 2014-06-11
CN103855037B CN103855037B (zh) 2018-01-09

Family

ID=49709493

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310625260.3A Active CN103855037B (zh) 2012-11-28 2013-11-28 电子部件安装基板及其制造方法

Country Status (5)

Country Link
US (2) US10510557B2 (zh)
EP (2) EP3982397B1 (zh)
JP (1) JP6099453B2 (zh)
KR (1) KR102151824B1 (zh)
CN (1) CN103855037B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104582270A (zh) * 2014-12-05 2015-04-29 广东明路电力电子有限公司 金属层积连接电路及其制备方法
CN110731129A (zh) * 2017-06-09 2020-01-24 电化株式会社 陶瓷电路基板

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6262968B2 (ja) * 2013-09-09 2018-01-17 Ｄｏｗａメタルテック株式会社 電子部品搭載基板およびその製造方法
EP3057123B1 (en) * 2013-10-07 2021-12-08 Furukawa Electric Co., Ltd. Joining structure comprising layers with different average crystal grain sizes for a semiconductor chip
JP2015220341A (ja) * 2014-05-19 2015-12-07 三菱電機株式会社 金属ベース基板、パワーモジュール、および金属ベース基板の製造方法
JP6400501B2 (ja) * 2015-02-18 2018-10-03 Ｄｏｗａメタルテック株式会社 金属−セラミックス回路基板の製造方法
JP6753721B2 (ja) * 2016-07-29 2020-09-09 Ｄｏｗａメタルテック株式会社 金属−セラミックス回路基板およびその製造方法
DE102016118784A1 (de) 2016-10-04 2018-04-05 Infineon Technologies Ag Chipträger, konfiguriert zur delaminierungsfreien Kapselung und stabilen Sinterung
JP7141864B2 (ja) * 2018-06-22 2022-09-26 Ｄｏｗａメタルテック株式会社 電子部品搭載基板およびその製造方法
CN113130407B (zh) * 2020-01-15 2023-12-12 武汉利之达科技股份有限公司 一种封装盖板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06296920A (ja) * 1993-04-15 1994-10-25 Matsushita Electric Works Ltd 立体表面への膜形成方法
CN1314072A (zh) * 1998-07-28 2001-09-19 依索拉层压系统公司 高密度印制电路板及其制造方法
CN1368904A (zh) * 1999-07-09 2002-09-11 希普雷公司 在绝缘基板上形成薄金属层的方法
US20090243089A1 (en) * 2008-03-31 2009-10-01 Infineon Technologies Ag Module including a rough solder joint
US20100055839A1 (en) * 2008-08-28 2010-03-04 Infineon Technologies Ag Method of manufacturing a semiconductor device

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0525644A1 (en) * 1991-07-24 1993-02-03 Denki Kagaku Kogyo Kabushiki Kaisha Circuit substrate for mounting a semiconductor element
JPH06314718A (ja) * 1993-04-28 1994-11-08 Nec Corp 半導体集積回路ペレット
US6033787A (en) * 1996-08-22 2000-03-07 Mitsubishi Materials Corporation Ceramic circuit board with heat sink
US6124635A (en) * 1997-03-21 2000-09-26 Honda Giken Kogyo Kabushiki Kaisha Functionally gradient integrated metal-ceramic member and semiconductor circuit substrate application thereof
JP3615661B2 (ja) * 1998-06-30 2005-02-02 京セラ株式会社 アルミニウム薄膜配線の補修方法
US6404065B1 (en) * 1998-07-31 2002-06-11 I-Xys Corporation Electrically isolated power semiconductor package
JP4649027B2 (ja) * 1999-09-28 2011-03-09 株式会社東芝 セラミックス回路基板
JP2001185838A (ja) * 1999-12-22 2001-07-06 Kyocera Corp セラミック配線基板
DE10146227B4 (de) * 2000-09-20 2015-01-29 Hitachi Metals, Ltd. Siliciumnitrid-Sinterkörper, Leiterplatte und thermoelektrisches Modul
JP4326706B2 (ja) * 2001-01-09 2009-09-09 電気化学工業株式会社 回路基板の評価方法、回路基板及びその製造方法
DE10103294C1 (de) * 2001-01-25 2002-10-31 Siemens Ag Träger mit einer Metallfläche und mindestens ein darauf angeordneter Chip, insbesondere Leistungshalbleiter
CN1226752C (zh) * 2001-01-29 2005-11-09 捷时雅株式会社 介电体用复合颗粒、超微颗粒复合树脂颗粒、介电体形成用组合物及其用途
US6670216B2 (en) * 2001-10-31 2003-12-30 Ixys Corporation Method for manufacturing a power semiconductor device and direct bonded substrate thereof
JP2003163315A (ja) * 2001-11-29 2003-06-06 Denki Kagaku Kogyo Kk モジュール
US20040245648A1 (en) * 2002-09-18 2004-12-09 Hiroshi Nagasawa Bonding material and bonding method
JP3922166B2 (ja) * 2002-11-20 2007-05-30 三菱マテリアル株式会社 パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
US7005734B2 (en) * 2003-05-05 2006-02-28 Ixys Corporation Double-sided cooling isolated packaged power semiconductor device
US8257795B2 (en) * 2004-02-18 2012-09-04 Virginia Tech Intellectual Properties, Inc. Nanoscale metal paste for interconnect and method of use
US8123107B2 (en) * 2004-05-25 2012-02-28 Praxair S.T. Technology, Inc. Method for forming sputter target assemblies
JP4756165B2 (ja) * 2004-08-26 2011-08-24 Ｄｏｗａメタルテック株式会社 アルミニウム−セラミックス接合基板
JP4010311B2 (ja) 2004-09-06 2007-11-21 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP2006202586A (ja) * 2005-01-20 2006-08-03 Nissan Motor Co Ltd 接合方法及び接合構造
WO2006077755A1 (ja) * 2005-01-20 2006-07-27 A.L.M.T.Corp. 半導体装置用部材とその製造方法
JP2006210536A (ja) * 2005-01-26 2006-08-10 Ngk Spark Plug Co Ltd 電子部品の製造方法、電子部品付き配線基板
EP1950767B1 (en) * 2005-09-21 2012-08-22 Nihon Handa Co., Ltd. Pasty silver particle composition, process for producing solid silver, solid silver, joining method, and process for producing printed wiring board
US7710045B2 (en) * 2006-03-17 2010-05-04 3M Innovative Properties Company Illumination assembly with enhanced thermal conductivity
JP4780085B2 (ja) * 2007-11-02 2011-09-28 株式会社デンソー 半導体装置
JP4454658B2 (ja) * 2007-12-04 2010-04-21 パナソニック株式会社 電子部品製造方法
US8513534B2 (en) * 2008-03-31 2013-08-20 Hitachi, Ltd. Semiconductor device and bonding material
KR101428719B1 (ko) * 2008-05-22 2014-08-12 삼성전자 주식회사 발광 소자 및 발광 장치의 제조 방법, 상기 방법을이용하여 제조한 발광 소자 및 발광 장치
US7682875B2 (en) * 2008-05-28 2010-03-23 Infineon Technologies Ag Method for fabricating a module including a sintered joint
JP4623167B2 (ja) * 2008-08-26 2011-02-02 トヨタ自動車株式会社 放熱構造及び車両用インバータ
JP5824201B2 (ja) 2009-09-11 2015-11-25 Ｄｏｗａエレクトロニクス株式会社 接合材およびそれを用いた接合方法
CN102714930B (zh) * 2010-01-12 2015-04-22 日本轻金属株式会社 液冷一体型基板及液冷一体型基板的制造方法
CN102339818B (zh) * 2010-07-15 2014-04-30 台达电子工业股份有限公司 功率模块及其制造方法
CN103262172B (zh) * 2010-11-03 2018-05-15 阿尔发装配解决方案有限公司 烧结材料及使用该材料的附着方法
US8766100B2 (en) 2011-03-02 2014-07-01 Samsung Electronics Co., Ltd. Printed circuit board and semiconductor package using the same
US20120292009A1 (en) * 2011-05-20 2012-11-22 Baker Hughes Incorporated Method and Apparatus for Joining Members for Downhole and High Temperature Applications
US20120291454A1 (en) * 2011-05-20 2012-11-22 Baker Hughes Incorporated Thermoelectric Devices Using Sintered Bonding
US8716864B2 (en) * 2012-06-07 2014-05-06 Ixys Corporation Solderless die attach to a direct bonded aluminum substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06296920A (ja) * 1993-04-15 1994-10-25 Matsushita Electric Works Ltd 立体表面への膜形成方法
CN1314072A (zh) * 1998-07-28 2001-09-19 依索拉层压系统公司 高密度印制电路板及其制造方法
CN1368904A (zh) * 1999-07-09 2002-09-11 希普雷公司 在绝缘基板上形成薄金属层的方法
US20090243089A1 (en) * 2008-03-31 2009-10-01 Infineon Technologies Ag Module including a rough solder joint
US20100055839A1 (en) * 2008-08-28 2010-03-04 Infineon Technologies Ag Method of manufacturing a semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104582270A (zh) * 2014-12-05 2015-04-29 广东明路电力电子有限公司 金属层积连接电路及其制备方法
WO2016086892A1 (zh) * 2014-12-05 2016-06-09 广东明路电力电子有限公司 金属层积连接电路及其制备方法
CN104582270B (zh) * 2014-12-05 2018-04-27 广东明路电力电子有限公司 金属层积连接电路的制备方法
CN110731129A (zh) * 2017-06-09 2020-01-24 电化株式会社 陶瓷电路基板
CN110731129B (zh) * 2017-06-09 2024-01-09 电化株式会社 陶瓷电路基板

Also Published As

Publication number Publication date
US10510557B2 (en) 2019-12-17
US20140147695A1 (en) 2014-05-29
EP3982397A1 (en) 2022-04-13
US20200083062A1 (en) 2020-03-12
JP2014130989A (ja) 2014-07-10
KR102151824B1 (ko) 2020-09-03
EP2738795A3 (en) 2014-11-05
EP2738795A2 (en) 2014-06-04
KR20140068769A (ko) 2014-06-09
EP2738795B1 (en) 2021-09-29
EP3982397B1 (en) 2023-10-18
CN103855037B (zh) 2018-01-09
JP6099453B2 (ja) 2017-03-22

Similar Documents

Publication Publication Date Title
CN103855037A (zh) 电子部件安装基板及其制造方法
EP3048640B1 (en) Method for producing an electronic part mounting substrate
CN101427367B (zh) 铝-碳化硅复合体和使用该复合体的散热零件
JP5988977B2 (ja) 半導体素子用放熱部品
JP5759152B2 (ja) アルミニウム−ダイヤモンド系複合体及びその製造方法
WO2010007922A1 (ja) アルミニウム－ダイヤモンド系複合体及びその製造方法
KR20080077094A (ko) 알루미늄-탄화규소질 복합체 및 그것을 사용한 방열 부품
CN104858435B (zh) 一种三明治结构金刚石‑Al复合材料的制备方法
CN106796927A (zh) 散热基板及该散热基板的制造方法
JP2012158783A (ja) アルミニウム−ダイヤモンド系複合体及びその製造方法
TWI682026B (zh) 鋁－金剛石系複合體及使用其之散熱零件
JP6105262B2 (ja) アルミニウム−ダイヤモンド系複合体放熱部品
TW200811300A (en) A treatment method of metalization of metal or ceramic substrate
JP2024041251A (ja) 電子部品接合方法
WO2015186320A1 (ja) 半導体パッケージ及びその製造方法
CN114729440A (zh) 复合基板及其制造方法、以及电路基板及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant