CN103531485A - 基板结构的制作方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 title abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 148
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 64
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052802 copper Inorganic materials 0.000 claims abstract description 60
- 239000010949 copper Substances 0.000 claims abstract description 60
- 239000010931 gold Substances 0.000 claims abstract description 47
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052737 gold Inorganic materials 0.000 claims abstract description 45
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 32
- 239000012792 core layer Substances 0.000 claims abstract description 19
- 238000007747 plating Methods 0.000 claims description 31
- 238000003466 welding Methods 0.000 claims description 27
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- 239000000463 material Substances 0.000 claims description 11
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- 239000002184 metal Substances 0.000 claims description 6
- 238000006722 reduction reaction Methods 0.000 claims description 3
- 150000002815 nickel Chemical class 0.000 claims 3
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 238000004891 communication Methods 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical group [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
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- 238000000576 coating method Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910018104 Ni-P Inorganic materials 0.000 description 1
- 229910018536 Ni—P Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
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- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
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Abstract
本发明公开一种基板结构的制作方法。该制作方法提供一基材。基材具有一核心层、一第一图案化铜层、一第二图案化铜层以及至少一导电通孔。第一图案化铜层与第二图案化铜层分别位于核心层的一第一表面与一第二表面上。导电通孔贯穿核心层且连接第一图案化铜层与第二图案化铜层。分别形成一第一防焊层与一第二防焊层于第一表面与第二表面上。第一防焊层与第二防焊层分别暴露出部分第一图案化铜层与部分第二图案化铜层。形成一第一金层于第一防焊层与第二防焊层所暴露出的第一图案化铜层与第二图案化铜层上。形成一镍层于第一金层上。形成一第二金层于镍层上。
Description
技术领域
本发明涉及一种基板结构的制作方法,且特别是涉及一种具有较佳制作工艺良率的基板结构的制作方法。
背景技术
体电路的封装是半导体后段制作工艺中相当重要一部分,其目的是使加工完成后的每一颗芯片受到保护,并且使芯片上的焊垫与印刷电路板(printed circuit board,PCB)达成电连接。印刷电路板及芯片承载(chipcarrier)基板上有许多焊点(solder joints),且这些焊点与印刷电路板或芯片承载基板的线路层的接触面,在焊接前需经表面处理(surface finish)或金属化(Metallization)。一般来说,可在线路层的焊垫上形成镍-钯(Ni/Pd)或镍-金(Ni/Au)的双金属层或镍-钯-金(Ni/Pd/Au)的三金属层等表面处理方式。
目前的线路层的焊垫的材质大都为铜,而形成镍层于焊垫上时是采用无电电镀法(Electroless Plating),或称为化学镀(chemical plating)。由于镍层含有硼或磷的成分,意即Ni-P或Ni-B,因此会影响到微波通讯信号的完整性,尤其是在高频率时其影响相当明显。再者,由于是采用化学镀的方式来形成镍层,即采用还原型的镀镍方式,因此容易产生电镀液不稳定及镀层覆盖不完全的问题产生,进而导致后续化学镀钯时发生跳镀(skip plating)的现象。此外,由于无电电镀的初始过程中会产生气体(如氢气),如果初始形成的镍层的厚度较薄,则容易产生空洞(void)或形成金属氧化物或带有杂质的硬度较大的非纯金属物质在其表面。因此,化学镀所形成的镍层的厚度通常需累积至一定的厚度以上,例如1.5微米以上,然而这样的镍层厚度易导致线路间隙较小的产品造成间距(space)不足的现象。
发明内容
本发明的目的在于提供一种基板结构的制作方法,其图案化铜层上依序形成有第一金层、镍层以及第二金层,除了可具有较佳的制作工艺良率外,也可维持微波通讯信号的完整性。
为达上述目的,本发明提出一种基板结构的制作方法,其包括以下步骤。提供一基材。基材具有一核心层、一第一图案化铜层、一第二图案化铜层以及至少一导电通孔。核心层具有彼此相对的一第一表面与一第二表面。第一图案化铜层与第二图案化铜层分别位于第一表面与第二表面上。导电通孔贯穿核心层且连接第一图案化铜层与第二图案化铜层。分别形成一第一防焊层与一第二防焊层于核心层的第一表面与第二表面上。第一防焊层与第二防焊层分别暴露出部分第一图案化铜层与部分第二图案化铜层。形成一第一金层于第一防焊层与第二防焊层所暴露出的第一图案化铜层与第二图案化铜层上。形成一镍层于第一金层上。形成一第二金层于镍层上。
在本发明的一实施例中,上述形成第一金属的方法包括浸镀(immersionplating)。
在本发明的一实施例中,上述第一金层的厚度介于0.02微米至0.05微米之间。
在本发明的一实施例中,上述形成镍层的方法包括还原反应。
在本发明的一实施例中,上述镍层的厚度介于0.1微米至5微米之间。
在本发明的一实施例中,上述形成第二金属的方法包括浸镀(immersionplating)。
在本发明的一实施例中,上述第二金层的厚度介于0.02微米至0.2微米之间。
在本发明的一实施例中,上述基材还具有至少一贯孔。贯孔贯穿第一图案化铜层、核心层以及第二图案化铜层,且第一金层覆盖贯孔的内壁。
基于上述,本发明的基板结构是于其图案化铜层上依序形成有第一金层、镍层以及第二金层。相比较于现有于基板结构的图案化铜层上依序形成镍层、钯层与金层而言,本发明的基板结构的制作方法可具有较佳的制作工艺良率外,也可维持微波通讯信号的完整性。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1A至图1E为本发明的一实施例的一种基板结构的制作方法的剖面示意图。
主要元件符号说明
100:基板结构
110:基材
111:第一表面
112:核心层
113:第二表面
114:第一图案化铜层
116:第二图案化铜层
118:导电通孔
119:贯孔
120:第一防焊层
130:第二防焊层
140:第一金层
150:镍层
160:第二金层
具体实施方式
图1A至图1E为本发明的一实施例的一种基板结构的制作方法的剖面示意图。依照本实施例的基板结构的制作方法,首先,请参考图1A,提供一基材110。详细来说,基材110具有一核心层112、一第一图案化铜层114、一第二图案化铜层116以及至少一导电通孔118(图1A中仅示意地绘示一个)。核心层112具有彼此相对的一第一表面111与一第二表面113。第一图案化铜层114与第二图案化铜层116分别位于第一表面111与第二表面113上。导电通孔118贯穿核心层112且连接第一图案化铜层114与第二图案化铜层116。此外,本实施例的基材110还具有一至少一贯孔119(图1A中仅示意地绘示一个),其中贯孔119贯穿第一图案化铜层114、核心层223以及第二图案化铜层116。
接着,请参考图1B,分别形成一第一防焊层120与一第二防焊层130于核心层112的第一表面111与第二表面114上。于此,第一防焊层120与第二防焊层130分别暴露出部分第一图案化铜层114与部分第二图案化铜层116,其中第一防焊层120与第二防焊层130所暴露出的第一图案化铜层114与第二图案化铜层116可定义为多个接垫。
接着,请参考图1C,形成一第一金层140于第一防焊层120与第二防焊层130所暴露出的第一图案化铜层114与第二图案化铜层116上。其中,第一金层140完全包覆第一防焊层120与第二防焊层130所暴露出的第一图案化铜层114与第二图案化铜层116,且第一金层140覆盖贯孔119的内壁。于此,第一金层140为纯金层,且无含磷或硼的成分。本实施例形成第一金属140的方法例如是浸镀(immersion plating),或称为置换镀(displacementplating),而第一金层140的厚度例如是介于0.02微米至0.05微米之间。
之后,请参考图1D,形成一镍层150于第一金层140上,其中镍层150完全包覆第一金层140。在本实施例中,形成镍层150的方法例如是还原反应,而镍层150的厚度例如是介于0.1微米至5微米之间。
最后,请参考图1E,形成一第二金层160于镍层150上,其中第二金层160完全包覆镍层150。于此,第二金层160为纯金层,且无含磷或硼的成分。本实施例形成第二金属160的方法例如是浸镀(immersion plating),或称为置换镀(displacement plating),而第二金层160的厚度例如是介于0.02微米至0.2微米之间。至此,已完成基板结构100的制作。
由于本实施例是于第一防焊层120与第二防焊层130所暴露出的第一图案化铜层114与第二图案化铜层116上依序形成有第一金层140、镍层150以及第二金层160。相比较于现有于线路层的焊垫上依序形成镍层、钯层与金层而言,第一金层140为纯金层且无含磷或硼的成分,因此不会影响微波通讯信号的完整性,故可维持微波通讯信号的完整性。再者,由于本实施例是采用浸镀(immersion plating),或称为置换镀(displacement plating),来形成第一金层140,其中浸镀(immersion plating)相比较于无电电镀法(Electroless Plating)较为稳定且镀层的覆盖完整性较佳,有利于后续镀层的形成,因此具有较佳的制作工艺良率。此外,第一金层140的厚度相对小于现有的镍层的厚度,因此可应用于线路间距较小的产品上。
综上所述,本发明的基板结构是于其图案化铜层上依序形成有第一金层、镍层以及第二金层。相较于现有于基板结构的图案化铜层上依序形成镍层、钯层与金层而言,本发明的基板结构的制作方法可具有较佳的制作工艺良率外,也可维持微波通讯信号的完整性。
虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (8)
1.一种基板结构的制作方法,包括:
提供一基材,该基材具有核心层、第一图案化铜层、第二图案化铜层以及至少一导电通孔,其中该核心层具有彼此相对的第一表面与第二表面,该第一图案化铜层与该第二图案化铜层分别位于该第一表面与该第二表面上,而该导电通孔贯穿该核心层且连接该第一图案化铜层与该第二图案化铜层;
分别形成一第一防焊层与一第二防焊层于该核心层的该第一表面与该第二表面上,其中该第一防焊层与该第二防焊层分别暴露出部分该第一图案化铜层与部分该第二图案化铜层;
形成一第一金层于该第一防焊层与该第二防焊层所暴露出的该第一图案化铜层与该第二图案化铜层上;
形成一镍层于该第一金层上;以及
形成一第二金层于该镍层上。
2.如权利要求1所述的基板结构的制作方法,其中形成该第一金属的方法包括浸镀。
3.如权利要求1所述的基板结构的制作方法,其中该第一金层的厚度介于0.02微米至0.05微米之间。
4.如权利要求1所述的基板结构的制作方法,其中形成该镍层的方法包括还原反应。
5.如权利要求1所述的基板结构的制作方法,其中该镍层的厚度介于0.1微米至5微米之间。
6.如权利要求1所述的基板结构的制作方法,其中形成该第二金属的方法包括浸镀。
7.如权利要求1所述的基板结构的制作方法,其中该第二金层的厚度介于0.02微米至0.2微米之间。
8.如权利要求1所述的基板结构的制作方法,其中该基材还具有至少一贯孔,该贯孔贯穿该第一图案化铜层、该核心层以及该第二图案化铜层,且该第一金层覆盖该贯孔的内壁。
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TWI576033B (zh) * | 2016-05-06 | 2017-03-21 | 旭德科技股份有限公司 | 線路基板及其製作方法 |
WO2019051712A1 (en) * | 2017-09-14 | 2019-03-21 | Apply Card Technology Limited | METHODS OF MANUFACTURING INTEGRATED CIRCUIT BOARD CIRCUIT BOARD SUBSTRATES AND INTEGRATED CIRCUIT BOARDS |
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US8973258B2 (en) | 2015-03-10 |
TW201404264A (zh) | 2014-01-16 |
TWI442852B (zh) | 2014-06-21 |
CN103531485B (zh) | 2016-12-21 |
US20140000109A1 (en) | 2014-01-02 |
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