TWI442852B - 基板結構的製作方法 - Google Patents
基板結構的製作方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims description 167
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 65
- 239000010931 gold Substances 0.000 claims description 54
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 52
- 229910052802 copper Inorganic materials 0.000 claims description 52
- 239000010949 copper Substances 0.000 claims description 52
- 229910052737 gold Inorganic materials 0.000 claims description 52
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 51
- 229910052759 nickel Inorganic materials 0.000 claims description 31
- 229910000679 solder Inorganic materials 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 25
- 238000007747 plating Methods 0.000 claims description 18
- 239000012792 core layer Substances 0.000 claims description 17
- 238000007654 immersion Methods 0.000 claims description 9
- 238000006722 reduction reaction Methods 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 238000004891 communication Methods 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910018104 Ni-P Inorganic materials 0.000 description 1
- 229910018536 Ni—P Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明是有關於一種基板結構的製作方法，且特別是有關於一種具有較佳製程良率之基板結構的製作方法。
體電路之封裝是半導體後段製程中相當重要一部份，其目的是使加工完成後之每一顆晶片受到保護，並且使晶片上之銲墊與印刷電路板(printed circuit board,PCB)達成電性連接。印刷電路板及晶片承載(chip carrier)基板上有許多銲點(solder joints)，且這些銲點與印刷電路板或晶片承載基板的線路層的接觸面，在銲接前需經表面處理(surface finish)或金屬化(Metallization)。一般來說，可在線路層的銲墊上形成鎳-鈀(Ni/Pd)或鎳-金(Ni/Au)的雙金屬層或鎳-鈀-金(Ni/Pd/Au)的三金屬層等表面處理方式。
目前之線路層之銲墊的材質大都為銅，而形成鎳層於銲墊上時是採用無電電鍍法(Electroless Plating)，或稱為化學鍍(chemical plating)。由於鎳層含有硼或磷的成分，意即Ni-P或Ni-B，因此會影響到微波通訊訊號的完整性，尤其是在高頻率時其影響相當明顯。再者，由於是採用化學鍍的方式來形成鎳層，即採用還原型之鍍鎳方式，因此容易產生電鍍液不穩定及鍍層覆蓋不完全的問題產生，進而導致後續化學鍍鈀時發生跳鍍(skip plating)
的現象。此外，由於無電電鍍的初始過程中會產生氣體(如氫氣)，如果初始形成的鎳層的厚度較薄，則容易產生空洞(void)或形成金屬氧化物或帶有雜質的硬度較大的非純金屬物質在其表面。因此，化學鍍所形成之鎳層的厚度通常需累積至一定的厚度以上，例如1.5微米以上，然而這樣的鎳層厚度易導致線路間隙較小之產品造成間距(space)不足的現象。
本發明提供一種基板結構的製作方法，其圖案化銅層上依序形成有第一金層、鎳層以及第二金層，除了可具有較佳的製程良率外，亦可維持微波通訊訊號的完整性。
本發明提出一種基板結構的製作方法，其包括以下步驟。提供一基材。基材具有一核心層、一第一圖案化銅層、一第二圖案化銅層以及至少一導電通孔。核心層具有彼此相對之一第一表面與一第二表面。第一圖案化銅層與第二圖案化銅層分別位於第一表面與第二表面上。導電通孔貫穿核心層且連接第一圖案化銅層與第二圖案化銅層。分別形成一第一防焊層與一第二防焊層於核心層的第一表面與第二表面上。第一防焊層與第二防焊層分別暴露出部分第一圖案化銅層與部分第二圖案化銅層。形成一第一金層於第一防焊層與第二防焊層所暴露出之第一圖案化銅層與第二圖案化銅層上。形成一鎳層於第一金層上。形成一第二金層於鎳層上。
在本發明之一實施例中，上述形成第一金層的方法包括浸鍍(immersion plating)。
在本發明之一實施例中，上述第一金層的厚度介於0.02微米至0.05微米之間。
在本發明之一實施例中，上述形成鎳層的方法包括還原反應。
在本發明之一實施例中，上述鎳層的厚度介於0.1微米至5微米之間。
在本發明之一實施例中，上述形成第二金層的方法包括浸鍍(immersion plating)。
在本發明之一實施例中，上述第二金層的厚度介於0.02微米至0.2微米之間。
在本發明之一實施例中，上述基材更具有至少一貫孔。貫孔貫穿第一圖案化銅層、核心層以及第二圖案化銅層，且第一金層覆蓋貫孔的內壁。
基於上述，本發明之基板結構是於其圖案化銅層上依序形成有第一金層、鎳層以及第二金層。相較於習知於基板結構之圖案化銅層上依序形成鎳層、鈀層與金層而言，本發明之基板結構的製作方法可具有較佳的製程良率外，亦可維持微波通訊訊號的完整性。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1E為本發明之一實施例之一種基板結構的製作方法的剖面示意圖。依照本實施例的基板結構的製作方法，首先，請參考圖1A，提供一基材110。詳細來說，基材110具有一核心層112、一第一圖案化銅層114、一第二圖案化銅層116以及至少一導電通孔118(圖1A中僅示意地繪示一個)。核心層112具有彼此相對之一第一表面111與一第二表面113。第一圖案化銅層114與第二圖案化銅層116分別位於第一表面111與第二表面113上。導電通孔118貫穿核心層112且連接第一圖案化銅層114與第二圖案化銅層116。此外，本實施例之基材110更具有一至少一貫孔119(圖1A中僅示意地繪示一個)，其中貫孔119貫穿第一圖案化銅層114、核心層223以及第二圖案化銅層116。
接著，請參考圖1B，分別形成一第一防焊層120與一第二防焊層130於核心層112的第一表面111與第二表面114上。於此，第一防焊層120與第二防焊層130分別暴露出部分第一圖案化銅層114與部分第二圖案化銅層116，其中第一防焊層120與第二防焊層130所暴露出之第一圖案化銅層114與第二圖案化銅層116可定義為多個接墊。
接著，請參考圖1C，形成一第一金層140於第一防焊層120與第二防焊層130所暴露出之第一圖案化銅層114與第二圖案化銅層116上。其中，第一金層140完全包覆第一防焊層120與第二防焊層130所暴露出之第一圖
案化銅層114與第二圖案化銅層116，且第一金層140覆蓋貫孔119的內壁。於此，第一金層140為純金層，且無含磷或硼的成分。本實施例形成第一金層140的方法例如是浸鍍(immersion plating)，或稱為置換鍍(displacement plating)，而第一金層140的厚度例如是介於0.02微米至0.05微米之間。
之後，請參考圖1D，形成一鎳層150於第一金層140上，其中鎳層150完全包覆第一金層140。在本實施例中，形成鎳層150的方法例如是還原反應，而鎳層150的厚度例如是介於0.1微米至5微米之間。
最後，請參考圖1E，形成一第二金層160於鎳層150上，其中第二金層160完全包覆鎳層150。於此，第二金層160為純金層，且無含磷或硼的成分。本實施例形成第二金層160的方法例如是浸鍍(immersion plating)，或稱為置換鍍(displacement plating)，而第二金層160的厚度例如是介於0.02微米至0.2微米之間。至此，已完成基板結構100的製作。
由於本實施例是於第一防焊層120與第二防焊層130所暴露出之第一圖案化銅層114與第二圖案化銅層116上依序形成有第一金層140、鎳層150以及第二金層160。相較於習知於線路層之銲墊上依序形成鎳層、鈀層與金層而言，第一金層140為純金層且無含磷或硼的成分，因此不會影響微波通訊訊號的完整性，故可維持微波通訊訊號的完整性。再者，由於本實施例是採用浸鍍(immersion
plating)，或稱為置換鍍(displacement plating)，來形成第一金層140，其中浸鍍(immersion plating)相較於無電電鍍法(Electroless Plating)較為穩定且鍍層的覆蓋完整性較佳，有利於後續鍍層的形成，因此具有較佳的製程良率。此外，第一金層140的厚度相對小於習知之鎳層的厚度，因此可應用於線路間距較小的產品上。
綜上所述，本發明之基板結構是於其圖案化銅層上依序形成有第一金層、鎳層以及第二金層。相較於習知於基板結構之圖案化銅層上依序形成鎳層、鈀層與金層而言，本發明之基板結構的製作方法可具有較佳的製程良率外，亦可維持微波通訊訊號的完整性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基板結構
110‧‧‧基材
111‧‧‧第一表面
112‧‧‧核心層
113‧‧‧第二表面
114‧‧‧第一圖案化銅層
116‧‧‧第二圖案化銅層
118‧‧‧導電通孔
119‧‧‧貫孔
120‧‧‧第一防焊層
130‧‧‧第二防焊層
140‧‧‧第一金層
150‧‧‧鎳層
160‧‧‧第二金層
圖1A至圖1E為本發明之一實施例之一種基板結構的製作方法的剖面示意圖。
100‧‧‧基板結構
110‧‧‧基材
112‧‧‧核心層
114‧‧‧第一圖案化銅層
116‧‧‧第二圖案化銅層
118‧‧‧導電通孔
119‧‧‧貫孔
120‧‧‧第一防焊層
130‧‧‧第二防焊層
140‧‧‧第一金層
150‧‧‧鎳層
160‧‧‧第二金層
Claims (7)
- 一種基板結構的製作方法，包括：提供一基材，該基材具有一核心層、一第一圖案化銅層、一第二圖案化銅層以及至少一導電通孔，其中該核心層具有彼此相對之一第一表面與一第二表面，該第一圖案化銅層與該第二圖案化銅層分別位於該第一表面與該第二表面上，而該導電通孔貫穿該核心層且連接該第一圖案化銅層與該第二圖案化銅層；分別形成一第一防焊層與一第二防焊層於該核心層的該第一表面與該第二表面上，其中該第一防焊層與該第二防焊層分別暴露出部分該第一圖案化銅層與部分該第二圖案化銅層；形成一第一金層，該第一金層直接接觸於該第一防焊層與該第二防焊層所暴露出之該第一圖案化銅層與該第二圖案化銅層上，其中該第一金層的厚度介於0.02微米至0.05微米之間；形成一鎳層於該第一金層上；以及形成一第二金層於該鎳層上。
- 如申請專利範圍第1項所述之基板結構的製作方法，其中形成該第一金層的方法包括浸鍍。
- 如申請專利範圍第1項所述之基板結構的製作方法，其中形成該鎳層的方法包括還原反應。
- 如申請專利範圍第1項所述之基板結構的製作方法，其中該鎳層的厚度介於0.1微米至5微米之間。
- 如申請專利範圍第1項所述之基板結構的製作方法，其中形成該第二金層的方法包括浸鍍。
- 如申請專利範圍第1項所述之基板結構的製作方法，其中該第二金層的厚度介於0.02微米至0.2微米之間。
- 如申請專利範圍第1項所述之基板結構的製作方法，其中該基材更具有至少一貫孔，該貫孔貫穿該第一圖案化銅層、該核心層以及該第二圖案化銅層，且該第一金層覆蓋該貫孔的內壁。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101123724A TWI442852B (zh) | 2012-07-02 | 2012-07-02 | 基板結構的製作方法 |
| US13/600,222 US8973258B2 (en) | 2012-07-02 | 2012-08-31 | Manufacturing method of substrate structure |
| CN201210352995.9A CN103531485B (zh) | 2012-07-02 | 2012-09-20 | 基板结构的制作方法 |
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| Application Number | Priority Date | Filing Date | Title |
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| TW101123724A TWI442852B (zh) | 2012-07-02 | 2012-07-02 | 基板結構的製作方法 |
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| TW201404264A TW201404264A (zh) | 2014-01-16 |
| TWI442852B true TWI442852B (zh) | 2014-06-21 |
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| TW101123724A TWI442852B (zh) | 2012-07-02 | 2012-07-02 | 基板結構的製作方法 |
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| US (1) | US8973258B2 (zh) |
| CN (1) | CN103531485B (zh) |
| TW (1) | TWI442852B (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI558290B (zh) * | 2015-08-24 | 2016-11-11 | 欣興電子股份有限公司 | 線路板的製造方法 |
| US10080282B2 (en) * | 2016-02-16 | 2018-09-18 | Kabushiki Kaisha Toshiba | Flexible printed circuit and electronic apparatus |
| TWI576033B (zh) * | 2016-05-06 | 2017-03-21 | 旭德科技股份有限公司 | 線路基板及其製作方法 |
| WO2019051712A1 (en) * | 2017-09-14 | 2019-03-21 | Apply Card Technology Limited | METHODS OF MANUFACTURING INTEGRATED CIRCUIT BOARD CIRCUIT BOARD SUBSTRATES AND INTEGRATED CIRCUIT BOARDS |
| TWI740716B (zh) * | 2020-11-16 | 2021-09-21 | 旭德科技股份有限公司 | 基板結構 |
| CN115623660B (zh) * | 2021-07-20 | 2024-04-05 | 荣耀终端有限公司 | 电路板及电子设备 |
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| JP3677429B2 (ja) * | 2000-03-09 | 2005-08-03 | Ｎｅｃエレクトロニクス株式会社 | フリップチップ型半導体装置の製造方法 |
| US6709980B2 (en) * | 2002-05-24 | 2004-03-23 | Micron Technology, Inc. | Using stabilizers in electroless solutions to inhibit plating of fuses |
| US7316063B2 (en) * | 2004-01-12 | 2008-01-08 | Micron Technology, Inc. | Methods of fabricating substrates including at least one conductive via |
| WO2005073985A1 (ja) * | 2004-01-30 | 2005-08-11 | Sekisui Chemical Co., Ltd. | 導電性微粒子及び異方性導電材料 |
| US7622377B2 (en) * | 2005-09-01 | 2009-11-24 | Micron Technology, Inc. | Microfeature workpiece substrates having through-substrate vias, and associated methods of formation |
| TWI338942B (en) | 2007-06-13 | 2011-03-11 | Unimicron Technology Corp | Substrate for semiconductor package and method for fabricating the same |
| TW200910552A (en) | 2007-08-22 | 2009-03-01 | Phoenix Prec Technology Corp | Packaging substrate having conductive structure |
| CN101389184B (zh) * | 2007-09-10 | 2010-08-25 | 英业达股份有限公司 | 印刷电路板的组合式贯孔结构 |
| TW201017839A (en) * | 2008-10-24 | 2010-05-01 | Advanced Semiconductor Eng | Substrate for window ball grid array package and mehtod for making the same |
| TW201021183A (en) | 2008-11-20 | 2010-06-01 | Phoenix Prec Technology Corp | Packaging substrate and method for manufacturing the same |
| TW201230897A (en) * | 2011-01-14 | 2012-07-16 | Askey Computer Corp | Circuit board |
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2012
- 2012-07-02 TW TW101123724A patent/TWI442852B/zh not_active IP Right Cessation
- 2012-08-31 US US13/600,222 patent/US8973258B2/en not_active Expired - Fee Related
- 2012-09-20 CN CN201210352995.9A patent/CN103531485B/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN103531485B (zh) | 2016-12-21 |
| CN103531485A (zh) | 2014-01-22 |
| US20140000109A1 (en) | 2014-01-02 |
| US8973258B2 (en) | 2015-03-10 |
| TW201404264A (zh) | 2014-01-16 |
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