CN103378019B - 具有散热结构的半导体封装结构及其制造方法 - Google Patents

具有散热结构的半导体封装结构及其制造方法 Download PDF

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CN103378019B
CN103378019B CN201310110338.8A CN201310110338A CN103378019B CN 103378019 B CN103378019 B CN 103378019B CN 201310110338 A CN201310110338 A CN 201310110338A CN 103378019 B CN103378019 B CN 103378019B
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die pad
supporting part
connecting rod
semiconductor package
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蔡甫拥
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Advanced Semiconductor Engineering Inc
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Abstract

半导体封装结构包含一芯片承座、至少一连接杆、至少一支撑部、数个引脚、一半导体芯片、一散热片及一封胶材料。该连接杆连接该芯片承座及该支撑部。该等引脚彼此电性绝缘，且与该芯片承座电性绝缘。该半导体芯片位于该芯片承座上，且电性连接至该等引脚。该散热片被该支撑部所支撑。该封胶材料封装该半导体芯片及该散热片。该半导体芯片的热从该芯片承座经由该连接杆、经由该支撑部，经由该散热片有效地发散。

Description

具有散热结构的半导体封装结构及其制造方法
技术领域
本发明关于一种半导体封装结构及其制造方法，详言之，关于具有散热片的半导体封装结构及其制造方法
背景技术
扁平无接脚封装结构(Flat No leads packages)，例如四边扁平无接脚(Quad FlatNo leads，QFN)封装结构，操作上耦合集成电路至印刷电路板。传统四边扁平无接脚(QFN)封装结构包含一半导体芯片(Semiconductor Chip)、该芯片所在的一芯片承座(Die Pad)、数个条接合导线(Bonding Wires)、数个引脚(Leads)及一封装体(PackageBody)。该等接合导线电性连接该芯片至该等引脚的上表面。该等引脚的下表面显露于该封装体之外且作为该四边扁平无接脚(QFN)封装结构的外部接点。该等引脚大致上排列成一周围阵列(Perimeter Array)而围绕该芯片，以增加引脚密度。然而，该芯片被该封装体所包覆，该封装体通常为不易导热的材料。但是，该芯片在运作时会产生热，且这些热必须被排除掉，以避免降低该芯片的效能。因此，对传统四边扁平无接脚(QFN)封装结构而言，散热是一项重要的课题。
发明内容
本发明的一实施例包括一种半导体封装结构，其包含一芯片承座及至少一连接杆，该连接杆从该芯片承座向外延伸。至少一支撑部从该至少一连接杆延伸至一与该芯片承座间隔的位置，且包含一上表面，其高于该芯片承座的一上表面。数个引脚围绕该芯片承座，彼此电性绝缘，且与该芯片承座电性绝缘。一半导体芯片位于该芯片承座上，且电性连接至该等引脚。一散热片附着至该至少一支撑部的上表面。一封胶材料封装该半导体芯片、该散热片的至少一部份、该芯片承座的至少一部份、该连接杆的至少一部份、该支撑部的至少一部份及每一该等引脚的至少一部份。
本发明的另一实施例包括一种半导体封装结构，其包含一芯片承座及至少一连接杆，该连接杆从该芯片承座向外延伸。至少一支撑部从该至少一连接杆延伸，且位于与该芯片承座间隔的一末梢端。数个引脚围绕该芯片承座，彼此电性绝缘，且与该芯片承座电性绝缘。一半导体芯片位于该芯片承座上，且电性连接至该等引脚。一散热片附着至该至少一支撑部的上表面。该散热片包含一主体及至少一支脚。一封胶材料封装该半导体芯片、该散热片的至少一部份、该芯片承座的至少一部份、该连接杆的至少一部份、该支撑部的至少一部份及每一该等引脚的至少一部份。该半导体芯片的散热路径包括从该芯片承座经由该至少一连接杆，经由该至少一支撑部，经由该至少一支脚，及经由该主体。
本发明的另一实施例包括一种半导体封装结构的制造方法。该方法包括提供一金属板，其包含一基材、一中心突部、数个周围突部、数个支撑突部、一第一金属层及一第二金属层。该基材具有数个连接部，连接该中心突部及该等支撑突部。该中心突部具有一上表面且从该基材向上延伸以定义出一空腔。每一该等周围突部具有一上表面且从该基材向上延伸，且围绕该中心突部。每一该等支撑突部具有一上表面且从该基材向上延伸，且围绕该中心突部。该第一金属层位于该中心突部的上表面、该等周围突部的上表面及该等支撑突部的上表面。该第二金属层形成于该金属板的下表面，且位于该空腔、该中心突部、该等连接部、该等支撑突部及该等周围突部的下方。该方法更包括固设一半导体芯片于该空腔中。该方法更包括电性连接该半导体芯片至该等周围突部。该方法更包括固设一散热片至该金属板。该散热片包含一主体及数个支脚。该主体位于该半导体芯片上方，且该等支脚从该主体延伸且被该等支撑突部所支撑。该方法更包括形成一封胶材料于该金属板上，以包覆该半导体芯片、该散热片、该中心突部、该等周围突部、该等支撑突部及该第一金属层。该方法更包括蚀刻该金属板的下表面，以形成一芯片承座、数个连接杆、数个支撑部及数个引脚。该等连接杆连接该芯片承座及该等支撑部，且该等引脚围绕该芯片承座，彼此电性绝缘，且与该芯片承座电性绝缘。
附图说明
图1显示本发明半导体封装结构的一实施例的俯视示意图；
图2显示图1中沿着线2-2的剖视示意图；
图3显示图1的半导体封装结构的仰视示意图；及
图4至17显示本发明半导体封装结构的制造方法的一实施例的步骤示意图。
具体实施方式
参考图1-3，分别显示本发明半导体封装结构1的一实施例的俯视、剖视及仰视示意图。图2所示的半导体封装结构1的剖视示意图沿着图1的线2-2。该半导体封装结构1包括一芯片承座12(Die Pad)、至少一连接杆(Connecting Bar)14、至少一支撑部(Supporting Portion)16、数个引脚(Leads)18、一半导体芯片(SemiconductorChip)20、一封胶材料(Molding Compound)22、数个条接合导线(Bonding Wires)28及一散热片(Heat Sink)3。为了便于说明，图1省略了图2的该等接合导线28及该封胶材料22。
参考图1，该芯片承座12包括一外缘区域121，其定义出该半导体芯片20所在的一空腔126。该等引脚18围绕该芯片承座12，且彼此电性绝缘，且与该芯片承座12电性绝缘。该支撑部16位于该半导体封装结构1的角落。该连接杆14从该芯片承座12向外延伸，因此，该连接杆14连接该芯片承座12及该支撑部16。
该散热片3包含一主体31及至少一支脚32。该主体31位于该半导体芯片20上方。该支脚32从该主体31延伸，且位于该半导体封装结构1的角落，且被该等支撑部16所支撑。
参考图2，该芯片承座12包括一外缘区域121，其定义出该半导体芯片20所在的一空腔126。该外缘区域121可以完全围绕该空腔126，或者，在其他实施例中，可以仅部分围绕该空腔126。该芯片承座12更包含一外上侧壁122、一下侧壁123、一位于该等侧壁122，123的接合处的尖端(Peak)127、一下表面128、一上表面124及一内上侧壁125。该内上侧壁125邻接该上表面124，且面朝向(Face Toward)该空腔126。该外上侧壁122邻接该上表面124，且面反向(Face Away)该空腔126。该下侧壁123邻接该外上侧壁122，且面反向(Face Away)该空腔126。该等侧壁122，123，125可以是直线状或弧状，且通常不垂直于该外缘区域121的上表面124。该外上侧壁122及该下侧壁123相交于该尖端127。
如上所述，该连接杆14连接该芯片承座12及该支撑部16。该连接杆14包含一上表面142及一下表面141，该上表面142及该下表面141彼此相对。该上表面142的水平位置低于该外缘区域121的上表面124，且和该芯片承座12的空腔126的底部共平面。该下表面141和该芯片承座12的下表面128共平面。
该支撑部16从该连接杆14延伸至一与该芯片承座12间隔的位置，且包含一上表面161、一上侧壁162、一下侧壁163、一位于该等侧壁162，163的接合处的尖端164及一下表面165。较佳地，该支撑部16从该连接杆14延伸，且位于与该芯片承座12间隔的一末梢端。该上表面161高于该芯片承座12的一上表面。该上侧壁162邻接该上表面161，且面反向该芯片承座12。该下侧壁163邻接该该上侧壁162，且面反向该芯片承座12。该等侧壁162，163可以是直线状或弧状，且通常不垂直于该上表面161。该上侧壁162及该下侧壁163相交于该尖端164。该下表面165和该芯片承座12的下表面128及该连接杆14的下表面141共平面。在本实施例中，该芯片承座12、该连接杆14及该支撑部16一体成型，然而，在其他实施例中，它们可以分别形成。该连接杆14的宽度和该支撑部16的宽度相同。或者，该连接杆14的宽度小于该支撑部16的宽度。
每一该等引脚18更包括一上表面181、一上侧壁182、一下侧壁183、一位于该等侧壁182，183的接合处的尖端184及一下表面185。该上侧壁182邻接于该上表面181，且可以是直线状或弧状，且通常不垂直于该上表面181。该下侧壁183邻接于该下表面185，且可以是直线状或弧状，且通常不垂直于该下表面185。该上侧壁182及该下侧壁183相交于该尖端184。在本实施例中，该支撑部16的表面积大于每一该等引脚18的表面积。然而，在其他实施例中，该支撑部16的表面积等于或小于每一该等引脚18的表面积。
一第一金属层24分别位于该支撑部16、该等引脚18及该外缘区域121的上表面161，181，124。该第一金属层24可以利用任何技术施加，例如电解电镀(ElectrolyticPlating)或无电电镀(Electroless Plating)。该第一金属层24可以包括，例如：一接触该等上表面161，181，124的镍层，及一覆盖该镍层的金层或钯层。或者，该第一金属层24可以包括一合金层，该合金层为镍及金与钯二者或二者其中之一。理想的情况是，该第一金属层24黏紧且可以供该等接合导线28有效地打线接合。
一第二金属层26分别位于该芯片承座12、该连接杆14、该支撑部16及该等引脚18的下表面128，141，165，185。在本实施例中，该等下表面128，141，165为共平面，且形成一整体下表面以供该第二金属层26形成于其上。该第二金属层26可以包括和上述该第一金属层24相同的材料，且可以利用相同的技术施加。该第二金属层26黏紧且保护该等下表面128，141，165，185以避免氧化及其他环境条件。
一黏胶层201固设该半导体芯片20于该芯片承座12的空腔126的底部。该黏胶层201可以是一导电或不导电黏性材料，例如银膏或不导电环氧树脂。该半导体芯片20的主动面利用该等接合导线28电性连接至该等引脚18，且可以利用该等接合导线28电性连接至该外缘区域121用以接地。
该散热片3包含该主体31及该等支脚32。该主体31及该等支脚32定义出一空间以容纳该半导体芯片20，且该等支脚32被该等支撑部16所支撑。在本实施例中，该等支脚32包含一弯曲部320以形成一第一部份321及一第二部份322。该第一部份321从该主体31延伸，且该第二部份322被该支撑部16所支撑而在该弯曲部320形成一夹角。
该封胶材料22封装该半导体芯片20、该散热片3、该芯片承座12的至少一部份、该连接杆14的至少一部份、该支撑部16的至少一部份及每一该等引脚18的至少一部份。该引脚18的下侧壁183、该芯片承座12的下侧壁123、该支撑部16的下侧壁163及该连接杆14从该封胶材料22的下表面221向外延伸。在本实施例中，该散热片3的主体31的上表面311未被该封胶材料22所覆盖，而显露至空气中。
参考图3，在本实施例中，该半导体封装结构1包含四根连接杆14及四个支撑部16，且该芯片承座12大致为矩形。图3的剖面线表示该金属层26显露于该封胶材料22之外。
在该半导体封装结构1，从该半导体芯片20散热的路径包括：从该芯片承座12经由该连接杆14，经由该支撑部16，经由该散热片3的支脚32，且经由该散热片3的主体31，上述元件的材料皆为热的良导体，例如金属。因此，该半导体芯片20的热可以有效地向外发散。再者，每一该等支撑部16的垂直厚度大于该等连接杆14的垂直厚度，使得每一支撑部16的上表面161高于该等连接杆14。这样的高度可减少该等支脚32从该主体31向下延伸的长度，使得该散热片3在该等支脚32的区域不需要弯折出锐角，藉此可减少制造成本。
在本实施例中，该等支撑部16其中之一可以和其他支撑部16具有不同的形状及/或尺寸。此一支撑部16可以做为最终封装结构的辨别标志以便于在表面黏着(Surface Mounting)时正确的定位。
参考图4至17，显示本发明半导体封装结构的制造方法的一实施例的步骤示意图。参考图4，该工艺由一板体40开始，该板体40具有一上表面401及一下表面402。该板体40的材质可以是金属，例如铜、铜合金、或其他任何材质。
参考图5，施加一第一光阻层42于该板体40的上表面401上，且施加一第二光阻层44于该板体40的下表面402上。该等光阻层42，44可以利用涂布、印刷或其他适当技术以形成。该等光阻层42，44被图案化，使得该第一光阻层42具有数个第一开口421以显露该板体40的上表面401的部分，且该第二光阻层44具有数个第二开口441以显露该板体40的下表面402的部分。该图案化可以利用例如微影(Photolithography)或其他适当技术来达成。
参考图6，该第一金属层24形成于该等第一开口421，且该第二金属层26形成于该等第二开口441。参考图7，移除该第一光阻层42。参考图8及图9，图9显示图8中沿着线9-9的剖视图。利用该金属层24作为遮罩，于该板体40的上表面401进行半蚀刻(Half Etching)工艺，以形成一基材46、一中心突部48、数个周围突部50及数个支撑突部52。图8的剖面线表示该板体40已被半蚀刻。
参考图9，该基材46具有数个连接部14，用以连接该中心突部48及该等支撑突部52。每一该等连接部14包含一上表面142及一下表面141，该上表面142及该下表面141彼此相对。该中心突部48具有一上表面481及一下表面482，且从该基材46向上延伸以定义出一空腔126。该连接部14的上表面142低于该中心突部48的上表面481，且和该空腔126的底部共平面。该连接部14的下表面141与该中心突部48的下表面482共平面。该中心突部48更具有一上侧壁125，邻接该上表面481，且面朝向该空腔126。每一该等周围突部50具有一上表面501及一下表面502，从该基材46向上延伸，且围绕该中心突部48。每一该等支撑突部52具有一上表面521及一下表面522，从该基材46向上延伸，且围绕该中心突部48。该第一金属层24保留在该中心突部48的上表面481、该等周围突部50的上表面501及该等支撑突部52的上表面521。该第二金属层26保留在该金属板40的下表面402，且位于该空腔126、该中心突部48的下表面482、该等连接部14下表面141、该等支撑突部52的下表面522及该等周围突部50的下表面502的下方。接着，移除该第二光阻层44。
参考图10，利用该黏胶层201附着该半导体芯片20于该空腔126的底部。参考图11，该半导体芯片20的主动面202利用该等接合导线28电性连接至该等周围突部50及该中心突部48。
参考图12至图15，图13显示图12中沿着线13-13的剖视图，且图15显示图14中沿着线15-15的剖视图。该散热片3被置放于该板体40上，使得该主体31位于该半导体芯片20上方，且该等支脚32的第二部份322被该等支撑突部52所支撑。该半导体芯片20容置于该主体31及该支脚32所定义出的空间。该等支脚32的第二部份322黏附至该等支撑突部52。
参考图16，形成一封胶材料22于该板体40上，以包覆该半导体芯片20、该散热片3、该中心突部48、该等周围突部50、该等支撑突部52及该第一金属层24。在本实施例中，在本实施例中，该散热片3的主体31的上表面311未被该封胶材料22所覆盖，而显露至空气中。
参考图17，利用该第二金属层26作为遮罩，蚀刻该板体40的下表面402，以形成该芯片承座12、该等连接杆14、该等支撑部16及该等引脚18。在该蚀刻工艺后，该等连接杆14连接该芯片承座12及该等支撑部16，且该等引脚18围绕该芯片承座12，彼此电性绝缘，且与该芯片承座12电性绝缘。接着，进行单体化工艺(SingulationProcess)，例如切割(Sawing)，以制得如图1所示的半导体封装结构1。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。

Claims (20)

1.一种半导体封装结构，其特征在于，包括：
一芯片承座；
至少一连接杆，从该芯片承座向外延伸，该至少一连接杆与该芯片承座一体成形；
至少一支撑部，从该至少一连接杆延伸至一与该芯片承座间隔的位置，且包含一上表面，其高于该芯片承座的一上表面；
数个引脚，围绕该芯片承座，彼此电性绝缘，且与该芯片承座电性绝缘；
一半导体芯片，位于该芯片承座上，且电性连接至所述引脚；
一散热片，附着至该至少一支撑部的上表面；及
一封胶材料，封装该半导体芯片、该散热片的至少一部份、该芯片承座的至少一部份、该连接杆的至少一部份、该支撑部的至少一部份及每一所述引脚的至少一部份，其中该芯片承座、该至少一连接杆及该至少一支撑部由金属组成。
2.如权利要求1的半导体封装结构，其特征在于，该芯片承座包括一外缘区域，定义出该半导体芯片所在的一空腔。
3.如权利要求1的半导体封装结构，其特征在于，每一所述引脚包括：
一上表面；
一下表面；
一上侧壁，邻接于该上表面：及
一下侧壁，邻接于该下表面；
其中该封胶材料封装该上侧壁，且显露该下侧壁。
4.如权利要求1的半导体封装结构，其特征在于，该至少一连接杆的一下表面与该至少一支撑部的一下表面共平面。
5.如权利要求1的半导体封装结构，其特征在于，该至少一连接杆从该封胶材料的一下表面向外延伸。
6.如权利要求1的半导体封装结构，其特征在于，该至少一支撑部的表面积大于每一所述引脚的表面积。
7.如权利要求1的半导体封装结构，其特征在于，该散热片的一上表面显露于该封胶材料之外。
8.如权利要求1的半导体封装结构，其特征在于，该至少一支撑部包括数个支撑部，位于该半导体封装结构的角落。
9.如权利要求8的半导体封装结构，其特征在于，该散热片包含一主体及数个支脚，且所述支脚附着至所述支撑部的上表面。
10.一种半导体封装结构，其特征在于，包括：
一芯片承座；
至少一连接杆，从该芯片承座向外延伸；
至少一支撑部，从该至少一连接杆延伸，且位于与该芯片承座间隔的一末梢端；
数个引脚，围绕该芯片承座，彼此电性绝缘，且与该芯片承座电性绝缘；
一半导体芯片，位于该芯片承座上，且电性连接至所述引脚；
一散热片，附着至该至少一支撑部的上表面，该散热片包含一主体及至少一支脚；及
一封胶材料，封装该半导体芯片、该散热片的至少一部份、该芯片承座的至少一部份、该连接杆的至少一部份、该支撑部的至少一部份及每一所述引脚的至少一部份；
其中该半导体芯片的散热路径包括从该芯片承座经由该至少一连接杆，经由该至少一支撑部，经由该至少一支脚，及经由该主体，其中该芯片承座、该至少一连接杆及该至少一支撑部由金属组成。
11.如权利要求10的半导体封装结构，其特征在于，该芯片承座包括一外缘区域，定义出该半导体芯片所在的一空腔。
12.如权利要求10的半导体封装结构，其特征在于，每一所述引脚更包括一上表面及一下表面，一邻接于该上表面的上侧壁，及一邻接于该下表面的下侧壁，其中该封胶材料封装该上侧壁，且显露该下侧壁。
13.如权利要求10的半导体封装结构，其特征在于，该至少一连接杆的一下表面与该至少一支撑部的一下表面共平面。
14.如权利要求10的半导体封装结构，其特征在于，该至少一连接杆从该封胶材料的一下表面向外延伸。
15.如权利要求10的半导体封装结构，其特征在于，该至少一支撑部的表面积大于每一所述引脚的表面积。
16.如权利要求10的半导体封装结构，其特征在于，该散热片的主体的一上表面显露于该封胶材料之外。
17.如权利要求10的半导体封装结构，其特征在于，该至少一支撑部包含一上表面，其高于该芯片承座的一上表面。
18.一种半导体封装结构的制造方法，其特征在于，包括以下步骤：
(a)提供一金属板，其包含一基材、一中心突部、数个周围突部、数个支撑突部、一第一金属层及一第二金属层，其中该基材具有数个连接部，连接该中心突部及所述支撑突部，该中心突部具有一上表面且从该基材向上延伸以定义出一空腔，每一所述周围突部具有一上表面且从该基材向上延伸，且围绕该中心突部，每一所述支撑突部具有一上表面且从该基材向上延伸，且围绕该中心突部，该第一金属层位于该中心突部的上表面、所述周围突部的上表面及所述支撑突部的上表面，且该第二金属层形成于该金属板的下表面，且位于该空腔、该中心突部、所述连接部、所述支撑突部及所述周围突部的下方；
(b)固设一半导体芯片于该空腔中；
(c)电性连接该半导体芯片至所述周围突部；
(d)固设一散热片至该金属板，其中该散热片包含一主体及数个支脚，该主体位于该半导体芯片上方，且所述支脚从该主体延伸且被所述支撑突部所支撑；
(e)形成一封胶材料于该金属板上，以包覆该半导体芯片、该散热片、该中心突部、所述周围突部、所述支撑突部及该第一金属层；及
(f)蚀刻该金属板的下表面，以形成一芯片承座、数个连接杆、数个支撑部及数个引脚，其中所述连接杆连接该芯片承座及所述支撑部，且所述引脚围绕该芯片承座，彼此电性绝缘，且与该芯片承座电性绝缘。
19.如权利要求18的方法，其特征在于，该步骤(b)中，该半导体芯片黏附于该空腔中，且该步骤(c)中，该半导体芯片利用数条接合导线电性连接至所述周围突部。
20.如权利要求18的方法，其特征在于，该步骤(e)中，该散热片的主体的一上表面显露。
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