CN103377958B - 半导体芯片的热压缩键合 - Google Patents

半导体芯片的热压缩键合 Download PDF

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CN103377958B
CN103377958B CN201310115912.9A CN201310115912A CN103377958B CN 103377958 B CN103377958 B CN 103377958B CN 201310115912 A CN201310115912 A CN 201310115912A CN 103377958 B CN103377958 B CN 103377958B
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crystal grain
hot compression
solder
substrate
bonding
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CN103377958A (zh
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张耀明
卢灿然
李明
麦易康
林嘉燊
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ASMPT Singapore Pte Ltd
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ASM Technology Singapore Pte Ltd
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Abstract

本发明公开了一种热压缩键合,准备晶粒进行热压缩键合,首先将晶粒上的电气触点和衬底上的键合盘对齐定位,该晶粒将被安装至该衬底上;在对齐定位晶粒之后,使用键合工具将晶粒上的电气触点抵靠于衬底上的键合盘固定;通过提供热量至晶粒的局部以将晶粒的局部处的温度提升至电气触点所包含的焊料的熔点之上以致于熔融设置在晶粒所述局部的电气触点的至少部分焊料的方式,将晶粒部分键合至衬底上;其后将整个晶粒热压缩,和加热至电气触点的焊料的熔点之上,以便于位于晶粒所述局部之外的电气触点的焊料也被熔融而将晶粒键合至衬底上。

Description

半导体芯片的热压缩键合
技术领域
本发明涉及将半导体芯片安装于衬底上,更具体地是通过焊料互联的方式。
背景技术
在倒装芯片(flip-chip)封装件的装配过程中的焊料回流(solderreflow)被广泛地采用在电子封装工业中。倒装芯片的硅晶粒互连通常是由面阵(area-array)布置形式的焊球(solderballs)或凸点(bumps)制作而成。晶粒被对齐定位和精确地放置在衬底如印刷线路板(“PWB”:printedwiringboard)上,以便于焊球降落于衬底的焊盘(solderpads)上,从此处晶粒互连被连接于衬底的电气回路。该焊盘包括铜引线(coppertrace)电路(厚度大约为18微米),其镀覆有镍(厚度大约为6微米)和金(厚度小于0.1微米)。在晶粒放置处理以前,合适数量的助焊剂(solderflux)将会施加在焊接表面。助焊剂的应用能够促进回流处理过程中焊球和衬底的焊盘之间的润湿(wetting)。回流炉(reflowoven)提供了良好可控的加热和冷却曲线,以便于确保在回流和焊点(solderjoint)的固化过程中焊点可靠地形成。焊料回流的自我定位特性使得更少精确的和更快速的拾取和放置机器能够被使用于装配处理中。
以上批量的装配处理被证明是富有成效的,并被广泛地采用于各种倒装芯片封装件的制造中。如果焊球的间距足够大,如超过150-200微米,那么焊料回流工序是可应用的。在这样的焊球间距的情形下,由于焊料回流的自我定位特性能够有助于修正任何的晶粒放置错误,所以相当精确但高产能的倒装芯片键合机能够被使用来实现拾取和放置处理。但是,当互连的间距被进一步减少到小于150微米时,回流处理过程中焊点的桥接故障(bridgingfailure)可能发生。
图1所示为具有键合在衬底14上的头部带焊料的铜柱12(solder-cappedcopperpillar)互连的倒装晶粒10的侧视示意图。倒装晶粒10的电气互连通过其重布层(redistributionlayer)再次分布。该互连被再次分布至具有间距P1的铜柱12的面阵(areaarray),其和位于高密度互连衬底14的焊盘16的盘间距的相匹配。倒装晶粒10的互连包括铜柱12,在其端部具有焊帽(soldercap)18。在焊接过程中,焊帽18的基于锡的焊料(锡Sn,锡金SnAg,锡金铜SnAgCu)熔融并润湿衬底14的焊盘16至焊点(solderjoints)。用于时兴的微细间距的倒装芯片在衬底(其可能从BT树脂或其他叠层材料中制造)上的键合的凸点间距P1大约为120-150微米。
如果微细间距的倒装晶粒10被键合在重布的中介层(interposers)20(其可能从硅、玻璃或陶瓷中制造),那么焊盘间距P2可以降低至40-60微米,如图2所示,其是当头部带焊料的铜柱12互连被键合至具有的重布的中介层20的衬底14A时微细间距的倒装晶粒10的侧视示意图。包含有电气线路和通孔(electricalroutingsandthrough-vias)28的重布的中介层20将焊帽18的微细间距P2互连重新分布至衬底14A上焊球26的面阵的更大得多的间距P3(超过200微米)。所以,朝向微细间距的倒装晶粒10的、重布的中介层20的焊盘22的焊盘间距P2能够小至40-60微米,但是位于重布的中介层20的底面上的焊盘24的焊盘间距P3大于200微米,这匹配于衬底14A上的焊盘16A的焊盘间距。
减少焊球26桥接概率的一种方法是通过使用头部带焊料的铜柱12来取代焊球26作为互连的方式减小焊料的体积,如图1和图2所示。铜柱12的尺寸(高度和宽度)以及焊帽18的厚度在可靠节点的设计中扮演了重要的角色。即使这种设计对于微细间距的倒装芯片封装件而言减少了焊料桥接的故障,但是它对于制造工艺而言引入了新的难题。首先,由于焊料体积大为减少,所以在回流处理过程中焊点的自我定位处理可能不会发生。从而,更为精确的倒装芯片拾取和放置机器被需要用为该装配处理。第二,这些头部带的焊料的体积控制将会非常重要。为了保证当焊点形成之时所有的焊帽18和衬底14上的焊盘16完全接触,在键合周期的初始阶段,足够大的压力应该被施加于倒装晶粒10上。在头部带焊料的铜柱12互连在具有细微间距的焊盘16的衬底14的情形下,热压缩(TC:ThermalCompression)键合工序取代焊料回流工序必须被使用来键合微细间距的倒装晶粒10。
用于具有头部带焊料的铜柱12互连的微细间距的倒装晶粒10的传统的热压缩(TC)工序的处理流程包括两个主要装配流程,即:精度定位流程(precisealignmentprocess),接着热压缩键合。在传统的配置中,由于任意的干扰可能将倒装晶粒10自同衬底14上的微细间距的焊盘16或重布的中介层20上的焊盘22精确定位中移动,所以这两个流程必须一个接着另一个连续地执行。该流程随着将衬底14传送在键合平台的输入位置处开始,该键合平台被维持在低于焊料的熔融温度Tm以下的预热温度T1。键合工具从晶圆平台处拾取微细间距的倒装晶粒10。微细间距的倒装晶粒10的精确定位在仰视和俯视视角定位系统的帮助下得以完成。微细间距的倒装晶粒10将会以如此方式被定位,以致于其焊帽18将会随同衬底14上的焊盘16或重布的中介层20上的焊盘22的位置和方位被对齐定位。在定位流程的末期,倒装晶粒10由键合工具所固定以保持其定位位置,然后通过应用合适的压力F1被放置在衬底14(或重布的中介层20)上,这样确保了焊帽18和焊盘16、22的良好接触。
对于高达+/-1微米的定位精度而言,用于精度定位流程的处理时间t1大约为几秒钟(2-3秒)。在热压缩键合流程开始时,由键合工具所固定的倒装晶粒10被提升至温度T2,其超过了铜柱12上焊料的熔融温度Tm。这能够通过安装在键合工具上的脉冲加热器(pulsedheater)得以实现。当铜柱12上的焊料达到其熔融温度Tm时,作用在倒装晶粒10上的压力将会减小至力F2,以防止回流过程中焊点的塌陷(collapsing)。其后,位于铜柱12的顶部的焊料润湿衬底14的焊盘16(或者重布的中介层20的焊盘22)。键合工具开始冷却,并且其温度下落至焊料将会固化的温度Ts以下。焊点将会形成在倒装晶粒10的铜柱12和衬底14的焊盘16(或者重布的中介层20的焊盘22)之间。在这个热压缩键合周期的末期,位于衬底14上(或者重布的中介层20上)的键合后的倒装晶粒10将会被传送至键合机的输出平台上。用于这个热压缩键合周期的处理时间t2大约为3-8秒钟,其实际上依赖于键合工具如何能够被快速地加热和冷却。
传统的热压缩键合流程的一个主要不足是其低的整体产能。该拾取和放置机器应该能够根据衬底14上焊点的焊盘开口的位置准确地定位倒装晶粒10。这个流程的定位精度要求在6西格玛(6-sigma)下必须好于+/-2微米。最高级的热压缩键合机能够在几秒钟(2-3秒钟)以内实现+/-1微米的定位精度。在这个精确定位之后,固定有倒装晶粒10的键合工具然后根据预定的温度曲线被脉冲加热器加热和冷却,在此过程中铜柱12端部处的焊料熔融然后固化以在衬底的焊盘上形成焊点。作用在倒装晶粒10上的压力必须被如此控制以便于焊点的期望互连高度(stand-offheight)能够得以保持。由于键合工具的加热和冷却花费时间,所以这个热压缩键合周期花费至少3-8秒钟。从而,用于整个定位和键合流程的周期时间大约为5-10秒钟,该流程的产能大约为每个小时500个单位。这个流程的产能必须提高,以为它获得通用便于量产。
发明内容
所以,本发明的目的在于寻求提供一种键合装置,和现有技术中使用的键合装置相比,其提高了用于半导体器件的热压缩键合流程的产能。
于是,本发明一方面提供一种热压缩键合方法,该方法包含有以下步骤:将晶粒上的电气触点和衬底上的键合盘对齐定位,该晶粒将被安装至该衬底上;在对齐定位晶粒之后,使用键合工具将晶粒上的电气触点抵靠于衬底上的键合盘固定;通过提供热量至晶粒的局部以将晶粒的局部处的温度提升至电气触点所包含的焊料的熔点之上以致于熔融设置在晶粒所述局部的电气触点的至少部分焊料的方式,将晶粒部分键合至衬底上;其后将整个晶粒加热至电气触点的焊料的熔点之上,以便于位于晶粒所述局部之外的电气触点的焊料也被熔融而将晶粒键合至衬底上。
本发明另一方面提供一种热压缩装置,该装置包含有:精度定位平台,其用于将包含有电气触点的晶粒和衬底上的键合盘对齐定位,该晶粒将被安装至该衬底上;键合工具,其用于将晶粒上的电气触点抵靠于衬底上的键合盘固定;加热设备,其被操作来通过提供热量至晶粒的局部以将晶粒的局部处的温度提升至电气触点所包含的焊料的熔点之上以致于熔融设置在晶粒所述局部的电气触点的至少部分焊料的方式,将晶粒部分键合至衬底上;以及热压缩平台,其用于将整个晶粒加热至电气触点的焊料的熔点之上,以便于位于晶粒所述局部之外的电气触点的焊料也被熔融而将晶粒键合至衬底上。
参阅后附的描述本发明实施例的附图,随后来详细描述本发明是很方便的。附图和相关的描述不能理解成是对本发明的限制,本发明的特点限定在权利要求书中。
附图说明
通过参考根据本发明较佳实施例具体实施方式的详细介绍,并参考附图很容易理解本发明,其中。
图1所示为具有键合在衬底上的头部带焊料的铜柱互连的倒装晶粒的侧视示意图。
图2所示为具有键合在带有重布中介层的衬底上的头部带焊料的铜柱互连的倒装晶粒的侧视示意图。
图3是根据本发明较佳实施例所述的键合流程的整体示意图。
图4是根据本发明较佳实施例所述的、用于键合半导体芯片的键合装置的立体示意图。
图5表明了根据本发明较佳实施例所述的精度定位处理流程。
图6是已经部分键合在衬底上的倒装芯片的立体示意图;以及。
图7是根据图5所述精度定位处理之后所完成的热压缩处理流程。
具体实施方式
图3是根据本发明较佳实施例所述的键合工序的整体示意图。该工序使得两个主要的装配流程,即精度定位流程和热压缩流程的并行处理成为可能。热压缩键合机包含有精度定位平台32、热压缩键合平台38和缓冲平台36。缓冲平台36被用作为缓冲,以便于均衡处理流程和预热部分键合的单元。
在精度定位平台32处,精度定位处理和激光焊接处理34二者均被完成。所有这些处理平台可以驻留在热压缩键合机的不同部件中,机器臂(roboticarm)可以被使用来从一个处理平台传送处理中的倒装芯片到另一个处理平台。该系统的物质流向描述如下:
衬底14由输入装载器从输入口30被装载,而倒装晶粒10从晶圆平台处被拾取。它们被放置在精度定位平台32处以便于灵活定位和激光焊接34。定位后的倒装晶粒10通过激光焊接34被部分地键合在衬底14上,其后被传送到缓冲平台36处进行预热。在部分键合后的倒装晶粒10被传送至缓冲平台36之后,精度定位平台32立即在下一个单元上工作。一旦位于缓冲平台36中的键合后的倒装晶粒10达到期望的预热温度并且热压缩键合平台38是可用的,那么键合后的倒装晶粒10被传送到热压缩键合平台38以执行热压缩键合。在热压缩键合处理的末期,完全键合后的倒装晶粒10被传送到热压缩键合机的输出口40。
所以,激光焊接34形成了部分的键合,以将定位后的倒装晶粒10固定定位在衬底14上,同时允许精度定位和热压缩键合处理能够于各自的处理平台处在不同单元上并行地完成,而不是于同一个平台处在同一个单元上顺序地完成。
图4是根据本发明较佳实施例所述的、用于键合倒装晶粒10的键合装置的立体示意图。键合工具44被操作来固定倒装晶粒10和抵靠衬底14的焊盘16压紧铜柱12和焊帽18。键合期间衬底14由平台42所支撑和锁固至平台42。一对激光头46、48设置在倒装晶粒10的相对的斜对角处。激光头46、48连接至光纤线缆、光纤准直器和聚焦光学器件上。来自光纤线缆的激光束被校准,然后较佳地在倒装晶粒10背面的两个相对的斜对角处聚焦为直径大约为1mm的激光点45、47上。
激光头46、48被操作来投射激光束于倒装晶粒10的角落处,以加热倒装晶粒10,并促进倒装晶粒10部分键合至衬底14上,这将会进一步详细描述如下。
现在描述在不同处理平台处的详细操作。图5表明了根据本发明较佳实施例所述的精度定位处理流程。衬底14从输入口30被装载至精度定位平台32,并放置在位于精度定位平台32的真空台顶部的定位预热平台42上。倒装晶粒10由键合工具44固定,并从键合机的晶圆平台处被拾取。使用预热处理,精度定位平台的定位预热平台42保持在温度T1',其预热衬底14至高于室温的温度50。为了保证视觉定位系统的良好图像质量和定位机构的最小化的热机械形变,精度定位平台的预热温度T1'被设定在低于100oC的温度。在这个温度下,热气流对视觉定位系统的成像光学器件的冲击得以最小化。后续的激光焊接处理所需的额外温度同样也能够得以减小。
倒装晶粒10由键合工具44固定,以便于以铜柱12和焊帽18形式存在的其电气触点在精度定位平台32处和衬底14上的焊料键合盘16准确地对齐定位,其在精度定位流程中由自动视觉定位机构实施52。倒装晶粒10与头部带焊料的铜柱12精确定位的定位精度大约为+/-1微米。在固定有倒装晶粒10的被精确控制的键合工具44和校准视觉定位光学器件以及摄像机的帮助下,花费定位时间t1'来实现这个定位精度。其后,在放置流程中,通过应用合适的压力F1,在将头部带焊料的铜柱12与键合盘16对齐定位的情形下,键合工具44抵靠衬底14放置倒装晶粒10(54)。然后,键合工具44固定定位倒装晶粒10。
在临时的激光键合流程56中,一旦完成精度定位,由键合工具44固定的倒装晶粒10然后被来自激光头46、48的两个激光束临时地在衬底14上进行激光焊接持续一段处理时间t2',每个激光束具有能量P1。激光束在倒装晶粒10的局部完成激光焊接,以在衬底14上为倒装晶粒10形成临时性的键合,其中,一个激光束指向倒装晶粒10的一个角落而另一个激光束指向倒装晶粒10斜对面的另一个角落。当激光束正被发射之时,一个合适的压力通过键合工具44被施加在倒装晶粒10上。
大多数半导体倒装芯片10是由硅制成。从而,激光束的波长被选定在700-980nm的范围以内,在该范围内激光束被硅的吸收很高。倒装硅晶粒10几乎能吸收所有的激光能量。然后,在倒装晶粒10被激光束对准的角落处围绕激光点45、47产生了发热区域。热量通过倒装晶粒10的主体被传导至铜柱12和焊帽18上。作用在倒装晶粒10上的压力保证焊帽18和衬底14的焊盘16具有良好的接触。当衬底14位于预热平台42的同时,衬底14被预热至温度T1'。激光束的能量P1被优化来加热倒装晶粒10的角落处的热作用区域至一个高于焊料熔融温度Tm的温度持续一段处理时间t2'以内,t2'小于1秒。在位于激光点45、47处的倒装晶粒10的加热局部的头部带焊料的铜柱12的至少一部分被熔融在键合盘16上。然后,在缓冲预热流程58中,部分键合的倒装晶粒10和衬底14被传送至预热缓冲平台36处,预热缓冲平台36被保持在预热温度T2'。
图6是已经部分地键合在衬底14上的倒装晶粒10的立体示意图。在激光加热区域下方,当位于激光加热区域之内的铜柱12的焊帽18熔融并润湿衬底14的相应的焊盘16的时候,焊点60得以形成。围绕在焊盘16的阻焊层(soldermask)防止焊盘16上熔融的焊料桥接。当激光脉冲被关闭时,由激光光源所产生的热量被迅速地引导离开激光加热区域。这些区域处的温度迅速地降落至焊料固化温度Ts以下,从而键合后的焊点60得以形成。对于位于激光加热区域以外的那些焊帽18,焊帽18依然没有键合到焊盘16上。如图6所示,基于焊帽18熔融所形成的焊点60仅仅在倒装晶粒10的两个角落处被发现。
在预热缓冲平台36处,部分键合的倒装晶粒10被加热至预热温度T2'持续一段停留时间(dwelltime)t3'。缓冲平台36处的预热温度T2'高于精度定位平台32处的预热温度T1',但是低于焊料的熔融温度Tm。当热压缩键合平台38可用的时候,温度T2'下的部分键合的倒装晶粒10被传送至热压缩键合平台38进行最后的键合。
图7是根据图5所述精度定位处理之后所完成的热压缩处理流程。部分键合的倒装晶粒10从预热缓冲平台36处被传送至热压缩键合平台38。在这个阶段,热压缩键合平台中的键合平台温度处于待命温度T3'下,在热压缩预热流程62中待命温度T3'低于焊料的熔融温度Tm。在压力应用处理64中,在不需要对部分键合的倒装晶粒10进行任何进一步的校正定位的情形下,热压缩键合平台38处的键合工具被降低,并使用压力F1压靠在倒装晶粒10上。部分键合的倒装晶粒10被这个热压缩键合工具紧紧地固定。然后,在热压缩加热处理66中,热压缩键合工具的温度被提升至温度T4',温度T4'高于铜柱12上焊料的熔融温度Tm。
当由键合工具固定的部分键合的倒装晶粒10被加热并达到焊料的熔融温度Tm时,位于已经熔融过的激光点45、47之外的铜柱12的焊帽18将会熔融,并润湿衬底14的焊盘16。而且,位于倒装晶粒10的角落处的焊点将会再次熔融,并润湿相应的焊盘16。在热压缩润湿处理68中,键合工具的压力从力F1降低至力F2,以防止熔融的焊帽塌陷。一旦铜柱12上的所有焊帽18熔融且润湿了焊盘16,那么然后热压缩键合工具的温度被降低至焊料的固化温度Ts以下。当在热压缩冷却处理70中倒装晶粒10的温度降落至焊料的固化温度Ts以下时,在倒装晶粒10的铜柱12和衬底14的键合盘16之间形成有焊点。现在,热压缩键合工序得以完成。然后,在输出传送处理72中,完全键合后的倒装晶粒10被键合工具从键合平台处提升,并传送至热压缩键合机的输出口40。整个热压缩键合周期花费时间t4'完成。
为了优化整个处理时间,均衡各个处理平台即精度定位平台32、预热缓冲平台36和热压缩键合平台38的产能,用于精度定位流程的处理时间t1'和用于激光焊接34的处理时间t2'的和应该大约等于t4'。在预热缓冲平台36中用于预热的停留时间t3'应该小于处理时间t1'与t2'的和。所以,为了产能均衡,处理时间应该满足:t3'<(t1'+t2')和t1'+t2'≈t4'。
热压缩键合机的产能(术语为单位每小时,或UPH)能够从(1/t4')x3600得以计算出,并基本上由热压缩键合处理时间t4'所决定。和带有顺序完成的精度定位和热压缩的、具有的整体处理时间等于t1+t2的传统热压缩键合处理相比,这个热压缩键合处理时间t4'仍然短暂得多。
在本发明的另一个实施例中,可能存在多个热压缩键合平台38用于键合多个晶粒,和/或热压缩键合可能通过使用一套键合工具(agangbondingtool)完成以在同一个热压缩键合平台38处同时固定多个单元进行加热。如果n为热压缩键合平台38上的位置数和为由该套键合工具处理的单元数,那么用于均衡的处理平台的处理时间应被视作为:
(n-1)x(t1'+t2')+t3'<nx(t1'+t2'),以及
nx(t1'+t2')≈t4'
带有一套键合工具处理n个单元的热压缩键合机的产能(UPH)被减少到(n/t4')x3600。
在本发明的其他实施例中,用于倒装晶粒10的铜柱12的焊料层和衬底14的焊盘16的构造可包括:(i)仅仅位于铜柱12上的焊帽,(ii)仅仅位于焊盘16上的焊料,或者(iii)位于铜柱12和焊盘16二者上的焊料。
而且,对于某些倒装芯片封装件结构,在放置和键合倒装晶粒10以前,非流动性底部填充胶(No-FlowUnderfill)或者非导电性黏着剂(Non-ConductivePaste:NCP)被滴注在衬底14上以覆盖焊盘16。甚至出现了这些热固化物质(thermalcurematerials)的情形下,激光焊接流程34能够得以完成。可是,需要合适的压力来从键合界面的接触中挤出这些物质。
值得欣赏的是,根据本发明较佳实施例所述的键合装置能够提高用于倒装芯片键合流程的热压缩键合机的整体产能。由于精度定位处理和热压缩处理能够并行地完成,所以产能能够通过至少两个理由而得以提高。
精度定位平台32保留在相对低和不变的、小于100oC的预热温度下,而在这个平台上精度定位处理能够在较少受由现有技术所遭遇的、键合平台的加热和冷却所引入的热膨胀和形变的影响的情形下而得以完成。
正好在精度定位平台32上进行定位处理之后,用于部分键合的激光焊接处理34通过在倒装晶粒10的两个角落处发射两个激光束而得以完成。用于这个激光焊接处理的处理时间大约为500-800ms(其小于1秒)。由于在晶粒10的角落处附近仅仅形成有临时的焊点,所以不需要考虑倒装晶粒10的大小,只需要相对较小功率的激光光源。
而且,由于仅仅只有倒装晶粒10的两个成斜对角的角落被激光焊接,所以只有两个相对低成本的激光光源被用于激光焊接处理,不需要在配置中使用昂贵的高功率激光器和激光束均匀化器(laserbeamhomogenizeroptics)。在使用激光焊接34完成部分键合之后,倒装晶粒10被粘着于衬底14上。倒装晶粒10固定在衬底14上,并能够在不引入任何的移动或错位的情形下被传送至其他的处理平台。
预热缓冲平台36被引入在精度定位平台32和热压缩键合平台38之间。这个预热缓冲平台36从它们在先60-80oC的预热温度加热衬底上的倒装晶粒10至130-180oC。在这个预热温度(130-180oC)下,热压缩键合平台38仅仅需要提升另一个大约∽100oC以达到的焊接温度而便于焊接处理发生。这样能够有助于减少热压缩处理的加热时间。
由于倒装晶粒10已经固定在衬底14上,所以在同一个热压缩键合平台38处,热压缩键合能够在一套压具(agangpress)的帮助下针对单个单元或多个单元得以完成。如果该套压具被用作为多个单元的热压缩键合,那么产能能够得到进一步的改善。
用于热压缩键合头的冷却需要要求得更少,因为它仅仅必须从大约240-260oC的焊接温度冷却至200oC(热压缩键合平台38的待命温度),以在热压缩键合周期的末期进行焊点的固化。当单元被冷却至200oC以下时,它能被传送至键合机的输出口。用于这个热压缩平台的温度操作范围是从200oC至260oC。这个温度操作范围与传统配置中从150oC以下和高达260oC操作相比小得多。所以,用于加热和冷却的周期时间能够得以缩短。
此处描述的本发明在所具体描述的内容基础上很容易产生变化、修正和/或补充,可以理解的是所有这些变化、修正和/或补充都包括在本发明的上述描述的精神和范围内。

Claims (20)

1.一种热压缩键合方法,该方法包含有以下步骤:
将晶粒上的电气触点和衬底上的键合盘对齐定位,该晶粒将被安装至该衬底上;
在对齐定位晶粒之后,使用键合工具将晶粒上的电气触点抵靠于衬底上的键合盘固定;
通过提供热量至晶粒的局部以将晶粒的局部处的温度提升至电气触点所包含的焊料的熔点之上以致于熔融设置在晶粒所述局部的电气触点的至少部分焊料的方式,将晶粒部分键合至衬底上;
将整个晶粒加热至电气触点的焊料的熔点之上,以便于位于晶粒所述局部之外的电气触点的焊料也被熔融而将晶粒键合至衬底上。
2.如权利要求1所述的热压缩键合方法,其中提供热量至晶粒的所述局部的步骤包括下面的步骤:
将激光束发射在晶粒的所述局部上。
3.如权利要求2所述的热压缩键合方法,其中晶粒的所述局部包括两个单独的局部化的加热区域,其设置在晶粒的斜对角的角落处。
4.如权利要求2所述的热压缩键合方法,其中激光束产生直径大约为1毫米的激光点。
5.如权利要求2所述的热压缩键合方法,其中激光束的波长在700-980纳米的范围以内。
6.如权利要求1所述的热压缩键合方法,其中,在将晶粒上的电气触点对齐定位的过程中,晶粒被加热至大体高于室温但小于100oC的温度。
7.如权利要求1所述的热压缩键合方法,该方法还包含有以下的步骤:
在接着于热压缩键合平台处将整个晶粒加热至焊料的熔点以上之前,将部分键合的晶粒和衬底传送至加热至预热温度的缓冲平台,该预热温度高于晶粒被对齐定位时晶粒的温度但小于焊料的熔点。
8.如权利要求1所述的热压缩键合方法,其中,将整个晶粒加热至焊料的熔点之上的过程中,固定有晶粒的键合工具的温度被提升至高于焊料的熔点之上的温度,然后将键合工具的温度降低至焊料的固化温度以下,以便于在晶粒和衬底之间形成有导电的节点。
9.如权利要求1所述的热压缩键合方法,其中,当一个晶粒在第二平台处被并行地加热至焊料的熔点之上以熔融晶粒的所述局部之外的焊料的同时,另一个晶粒在第一平台处被对齐定位,第一平台与第二平台相互分开。
10.如权利要求1所述的热压缩键合方法,其中每个电气触点包含有铜柱,该铜柱顶部具有焊帽。
11.如权利要求1所述的热压缩键合方法,其中,在多个热压缩平台处同时将多个晶粒加热至焊料的熔点之上。
12.如权利要求1所述的热压缩键合方法,其中在同一个热压缩平台处,多个晶粒被键合工具固定,该多个晶粒被同时加热至焊料的熔点之上。
13.一种热压缩装置,该装置包含有:
精度定位平台,其用于将包含有电气触点的晶粒和衬底上的键合盘对齐定位,该晶粒将被安装至该衬底上;
键合工具,其用于将晶粒上的电气触点抵靠于衬底上的键合盘固定;
加热设备,其被操作来通过提供热量至晶粒的局部以将晶粒的局部处的温度提升至电气触点所包含的焊料的熔点之上以致于熔融设置在晶粒所述局部的电气触点的至少部分焊料的方式,将晶粒部分键合至衬底上;以及
热压缩平台,其用于将整个晶粒加热至电气触点的焊料的熔点之上,以便于位于晶粒所述局部之外的电气触点的焊料也被熔融而将晶粒键合至衬底上。
14.如权利要求13所述的热压缩装置,该装置还包含有:预热缓冲平台,其被操作来将部分键合的晶粒加热至预热温度,该预热温度高于晶粒在精度定位平台处被加热到的温度但小于焊料的熔点。
15.如权利要求13所述的热压缩装置,其中该加热设备包括至少一个激光设备,该激光设备被操作来将激光束发射以将热量提供在晶粒的所述局部上。
16.如权利要求15所述的热压缩装置,其中,加热设备包括两个激光设备,该两个激光设备被操作来发射各自的激光束至设置于晶粒斜对角的角落处的两个独立的局部化的加热区域。
17.如权利要求15所述的热压缩装置,其中,激光束产生直径大约为1毫米的激光点。
18.如权利要求15所述的热压缩装置,其中,激光束的波长在700-980纳米的范围以内。
19.如权利要求13所述的热压缩装置,其中,在精度定位平台处的处理和在热压缩平台处的处理是在不同的晶粒上并行地同步进行的。
20.如权利要求19所述的热压缩装置,其中,热压缩平台还包括多个单独的平台,在这些平台处同时将多个晶粒加热至焊料的熔点之上。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11134598B2 (en) * 2009-07-20 2021-09-28 Set North America, Llc 3D packaging with low-force thermocompression bonding of oxidizable materials
JP2013236039A (ja) * 2012-05-11 2013-11-21 Renesas Electronics Corp 半導体装置
US9331032B2 (en) * 2013-03-06 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding and apparatus for performing the same
US9524958B2 (en) * 2013-06-27 2016-12-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding
US9093549B2 (en) 2013-07-02 2015-07-28 Kulicke And Soffa Industries, Inc. Bond heads for thermocompression bonders, thermocompression bonders, and methods of operating the same
DE102013114907A1 (de) * 2013-12-27 2015-07-02 Pac Tech-Packaging Technologies Gmbh Verfahren zur Herstellung eines Chipmoduls
KR20160113690A (ko) * 2014-03-29 2016-09-30 인텔 코포레이션 국소 열원을 이용한 집적 회로 칩 부착
US9426898B2 (en) * 2014-06-30 2016-08-23 Kulicke And Soffa Industries, Inc. Thermocompression bonders, methods of operating thermocompression bonders, and interconnect methods for fine pitch flip chip assembly
TWI610411B (zh) * 2014-08-14 2018-01-01 艾馬克科技公司 用於半導體晶粒互連的雷射輔助接合
EP3218923A4 (en) 2014-11-12 2018-07-25 Ontos Equipment Systems Simultaneous hydrophilization of photoresist surface and metal surface preparation: methods, systems, and products
JP6510837B2 (ja) * 2015-03-11 2019-05-08 ファスフォードテクノロジ株式会社 ボンディング装置及びボンディング方法
US9515108B2 (en) 2015-03-11 2016-12-06 Semiconductor Components Industries, Llc Image sensors with contamination barrier structures
US10014272B2 (en) * 2015-05-11 2018-07-03 Asm Technology Singapore Pte Ltd Die bonding with liquid phase solder
CN106206365B (zh) * 2015-05-26 2019-04-30 先进科技新加坡有限公司 具有惰性气体环境的模片键合装置
KR101923659B1 (ko) * 2015-08-31 2019-02-22 삼성전자주식회사 반도체 패키지 구조체, 및 그 제조 방법
WO2017039275A1 (ko) 2015-08-31 2017-03-09 한양대학교 산학협력단 반도체 패키지 구조체, 및 그 제조 방법
CN105772120A (zh) * 2016-03-07 2016-07-20 北京同方生物芯片技术有限公司 一种聚合物生物芯片的批量键合封装方法及定位装置
US9916989B2 (en) * 2016-04-15 2018-03-13 Amkor Technology, Inc. System and method for laser assisted bonding of semiconductor die
EP3276655A1 (en) * 2016-07-26 2018-01-31 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Method and system for bonding a chip to a substrate
US10103095B2 (en) 2016-10-06 2018-10-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US11069606B2 (en) 2016-10-06 2021-07-20 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US10923449B2 (en) 2016-10-06 2021-02-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
WO2018117361A1 (ko) * 2016-12-23 2018-06-28 주식회사 루멘스 마이크로 엘이디 모듈 및 그 제조방법
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
JP6366799B1 (ja) * 2017-02-10 2018-08-01 ルーメンス カンパニー リミテッド マイクロledモジュール及びその製造方法
US11024595B2 (en) 2017-06-16 2021-06-01 Micron Technology, Inc. Thermocompression bond tips and related apparatus and methods
KR101975103B1 (ko) 2017-06-20 2019-05-03 주식회사 프로텍 플립칩 레이저 본딩 장치 및 플립칩 레이저 본딩 방법
EP3738146A4 (en) * 2018-01-12 2021-08-25 INTEL Corporation PROCESS OF A FIRST LAYER JOIN FIRST ON CARRIER FOR EMIB PATCH
US10636734B2 (en) 2018-02-02 2020-04-28 Compass Technology Company, Ltd. Formation of fine pitch traces using ultra-thin PAA modified fully additive process
US10468342B2 (en) 2018-02-02 2019-11-05 Compass Technology Company, Ltd. Formation of fine pitch traces using ultra-thin PAA modified fully additive process
CN108538737B (zh) * 2018-03-22 2019-12-24 江西芯创光电有限公司 载板的压合方法
CN109262376B (zh) * 2018-10-19 2024-02-27 四川联合晶体新材料有限公司 一种用于降低薄板形材料离子束抛光时热应力的装置和方法
US10971471B2 (en) * 2018-12-29 2021-04-06 Micron Technology, Inc. Methods and systems for manufacturing semiconductor devices
JP7287647B2 (ja) * 2019-03-05 2023-06-06 株式会社新川 接合条件評価装置
US10756041B1 (en) 2019-03-14 2020-08-25 International Business Machines Corporation Finned contact
KR102252552B1 (ko) * 2019-05-03 2021-05-17 주식회사 프로텍 플립칩 레이저 본딩 시스템
KR20210030016A (ko) 2019-09-09 2021-03-17 한철희 반도체 칩 열압착 본딩 장치
WO2021047737A1 (de) * 2019-09-11 2021-03-18 Hesse Gmbh Ultraschallwerkzeug und ultraschallverbindungsvorrichtung hierfür
DE102019124335A1 (de) * 2019-09-11 2021-03-11 Hesse Gmbh Bondvorrichtung
KR20210037431A (ko) 2019-09-27 2021-04-06 삼성전자주식회사 본딩 헤드, 이를 포함하는 다이 본딩 장치 및 이를 이용한 반도체 패키지의 제조 방법
US11424214B1 (en) * 2019-10-10 2022-08-23 Meta Platforms Technologies, Llc Hybrid interconnect for laser bonding using nanoporous metal tips
US11410961B2 (en) * 2020-03-17 2022-08-09 Micron Technology, Inc. Methods and apparatus for temperature modification in bonding stacked microelectronic components and related substrates and assemblies
KR102394825B1 (ko) 2020-04-23 2022-05-06 주식회사 프로텍 빅셀 소자를 이용한 플립칩 본딩 장치
US11183438B1 (en) 2020-05-14 2021-11-23 Google Llc Compression-loaded printed circuit assembly for solder defect mitigation
TWI760230B (zh) * 2020-06-09 2022-04-01 台灣愛司帝科技股份有限公司 晶片檢測方法、晶片檢測結構以及晶片承載結構
CN111653494B (zh) * 2020-06-16 2021-10-15 中国电子科技集团公司第二十四研究所 非接触式加热的倒装焊工艺方法
CN112802766A (zh) * 2021-01-04 2021-05-14 上海易卜半导体有限公司 半导体组件组装方法、半导体组件和电子设备
US11688718B2 (en) 2021-09-07 2023-06-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage during LAB
CN114466526A (zh) * 2021-11-02 2022-05-10 深圳市智链信息技术有限公司 一种无线接收信号放大器的芯片固定装置
CN117655622B (zh) * 2024-01-31 2024-06-18 宁波尚进自动化科技有限公司 焊台

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1205927A (zh) * 1997-07-22 1999-01-27 国际商业机器公司 用于增强抗疲劳性的Pb-In-Sn高C-4
CN1611317A (zh) * 2003-09-26 2005-05-04 Tdk株式会社 焊料接合方法和焊料接合装置
CN101120441A (zh) * 2005-09-30 2008-02-06 松下电器产业株式会社 安装电子元件的方法
CN101623786A (zh) * 2008-07-10 2010-01-13 株式会社日立制作所 软钎焊方法及软钎焊装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2697865B2 (ja) * 1988-07-15 1998-01-14 ローム株式会社 電子部品の実装方法
JPH05329931A (ja) * 1992-05-29 1993-12-14 Nec Home Electron Ltd 熱圧着装置
US5495089A (en) * 1993-06-04 1996-02-27 Digital Equipment Corporation Laser soldering surface mount components of a printed circuit board
JPH0737911A (ja) * 1993-07-19 1995-02-07 Mitsubishi Electric Corp 半導体素子のダイボンド装置、及びダイボンド方法
US5341979A (en) * 1993-09-03 1994-08-30 Motorola, Inc. Method of bonding a semiconductor substrate to a support substrate and structure therefore
JP3331570B2 (ja) * 1993-09-08 2002-10-07 ソニー株式会社 熱圧着装置と熱圧着方法および液晶表示装置の生産方法
US5904868A (en) * 1994-06-16 1999-05-18 International Business Machines Corporation Mounting and/or removing of components using optical fiber tools
JP3842362B2 (ja) * 1996-02-28 2006-11-08 株式会社東芝 熱圧着方法および熱圧着装置
JP3176580B2 (ja) * 1998-04-09 2001-06-18 太陽誘電株式会社 電子部品の実装方法及び実装装置
JP2000036501A (ja) * 1998-05-12 2000-02-02 Sharp Corp ダイボンド装置
US6495397B2 (en) * 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection
US6713318B2 (en) * 2001-03-28 2004-03-30 Intel Corporation Flip chip interconnection using no-clean flux
TW559963B (en) * 2001-06-08 2003-11-01 Shibaura Mechatronics Corp Pressuring apparatus of electronic device and its method
US6593545B1 (en) * 2001-08-13 2003-07-15 Amkor Technology, Inc. Laser defined pads for flip chip on leadframe package fabrication method
JP2004111601A (ja) * 2002-09-18 2004-04-08 Tokyo Seimitsu Co Ltd ダイボンダ
US6768083B2 (en) * 2002-09-19 2004-07-27 Speedline Technologies, Inc. Reflow soldering apparatus and method for selective infrared heating
KR101165029B1 (ko) * 2007-04-24 2012-07-13 삼성테크윈 주식회사 칩 가열장치, 이를 구비한 플립 칩 본더 및 이를 이용한플립 칩 본딩 방법
US20090155958A1 (en) * 2007-12-13 2009-06-18 Boris Kolodin Robust die bonding process for led dies
JP2009186707A (ja) * 2008-02-06 2009-08-20 Seiko Epson Corp 電気光学装置の製造方法、電気光学装置
US7854365B2 (en) * 2008-10-27 2010-12-21 Asm Assembly Automation Ltd Direct die attach utilizing heated bond head
JP2010245412A (ja) * 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体集積回路装置の製造方法
KR101114180B1 (ko) * 2009-07-14 2012-02-22 (주)창조엔지니어링 평탄도 유지 장치
US8381965B2 (en) * 2010-07-22 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compress bonding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1205927A (zh) * 1997-07-22 1999-01-27 国际商业机器公司 用于增强抗疲劳性的Pb-In-Sn高C-4
CN1611317A (zh) * 2003-09-26 2005-05-04 Tdk株式会社 焊料接合方法和焊料接合装置
CN101120441A (zh) * 2005-09-30 2008-02-06 松下电器产业株式会社 安装电子元件的方法
CN101623786A (zh) * 2008-07-10 2010-01-13 株式会社日立制作所 软钎焊方法及软钎焊装置

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