CN103247603A - 半导体装置、制造半导体装置的方法以及电子设备 - Google Patents

半导体装置、制造半导体装置的方法以及电子设备 Download PDF

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CN103247603A
CN103247603A CN2013100492425A CN201310049242A CN103247603A CN 103247603 A CN103247603 A CN 103247603A CN 2013100492425 A CN2013100492425 A CN 2013100492425A CN 201310049242 A CN201310049242 A CN 201310049242A CN 103247603 A CN103247603 A CN 103247603A
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interlayer insulating
insulating film
semiconductor device
semiconductor substrate
bonding electrodes
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CN103247603B (zh
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萩本贤哉
藤井宣年
青柳健一
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Sony Corp
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Sony Corp
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Abstract

提供半导体装置、制造半导体装置的方法以及电子设备。所提供的半导体装置包括半导体基板、形成在半导体基板上的层间绝缘层、形成在层间绝缘层的表面上的接合电极以及覆盖包括层间绝缘层和接合电极的接合表面的整个表面的金属膜。

Description

半导体装置、制造半导体装置的方法以及电子设备
技术领域
本公开涉及通过层叠基板来进行配线接合的半导体装置、制造该半导体装置的方法以及电子设备。
背景技术
通过精细工艺的引进以及封装密度的改进，在二维LSI中已经实现了半导体装置的高集成。近年来，已经开始看到微细化的物理限制，并且三维LSI技术已经引起了关注。
接合技术在三维LSI中是基本技术。接合技术中存在多种方式，并且已考虑了将芯片彼此接合的技术和将晶片彼此接合的技术。当三维LSI通过将装置晶片层叠在一起来制造时，存在将装置侧的形成在晶片表面上的Cu电极彼此直接接合的方式。在该方式中，存在这样的方法，其平坦化Cu电极和层间电介质（ILD）以使它们位于相同的平面上并进行Cu/ILD的混合接合（hybrid bonding）（参照JP2006-191081A和JP H1-205465A）。在这样的接合工艺中，可能需要接合表面是非常平坦的表面，以改进接合强度并且控制接合缺陷。
发明内容
在上述的半导体基板直接彼此接合的半导体装置中，需要改进接合的可靠性。
本公开提供可靠性高的半导体装置、制造半导体装置的方法以及电子设备。
根据本公开的实施例，所提供的半导体装置包括半导体基板、形成在半导体基板上的层间绝缘层、形成在层间绝缘层表面上的接合电极以及覆盖包括层间绝缘层和接合电极的接合表面的整个表面的金属膜。
此外，本公开实施例的电子设备包括上述半导体装置和处理半导体装置的输出信号的信号输出电路。
根据本公开的实施例，所提供的制造半导体装置的方法包括：在半导体基板上形成层间绝缘层；在层间绝缘层的表面上形成接合电极；以及在层间绝缘层和接合电极的整个表面上形成金属膜。
根据本公开的实施例，所提供的半导体装置包括第一半导体基板和第二半导体基板，该半导体装置通过隔着金属膜层叠接合电极的表面而形成，该半导体装置包括：第一半导体基板；第一层间绝缘层，形成在第一半导体基板上；第一接合电极，形成在第一层间绝缘层的表面上；第二半导体基板，接合到第一半导体基板；第二层间绝缘层，形成在第二半导体基板上；第二接合电极，形成在第二层间绝缘层的表面上；金属膜，形成在第一半导体基板和第二半导体基板之间的接合表面上并位于第一接合电极和第二接合电极之间；以及绝缘膜，形成在第一半导体基板和第二半导体基板之间的接合表面上并位于与第一层间绝缘层或第二层间绝缘层接触的部分上，该绝缘膜包括金属膜和第一层间绝缘层或金属膜与第二层间绝缘层之间的反应产物。
根据本公开实施例的上述半导体装置以及通过上述制造方法制造的半导体装置，在形成有半导体基板的层间绝缘层和接合电极的表面上形成金属膜。当半导体基板在形成有接合电极的表面处接合到另一个半导体基板时，层间绝缘层和金属膜由于加热接合表面而发生反应，并且形成绝缘膜。此外，形成在接合电极上的金属膜保持为加热之前的状态而不发生反应。
此外，通过接合电极上的金属膜保证了接合电极之间的电连接。由于作为金属膜的反应产物的绝缘层，可以防止层间绝缘层和接合电极之间的接触，并且可以控制诸如由接合缺陷或泄漏路径引起的可靠性降低。
另外，应用该半导体装置的电子设备的可靠性可得到提高。
根据本公开的实施例，提供了可靠性高的半导体装置、制造半导体装置的方法和电子设备。
附图说明
图1是示出接合电极的示意性构造的截面图；
图2是示出接合电极的示意性构造的截面图；
图3是示出实施例的包括接合电极的半导体装置的示意性构造的截面图；
图4是示出实施例的包括接合电极的半导体装置的示意性构造的截面图；
图5A-5C是实施例的包括接合电极的半导体装置的制造工艺流程图；
图6D-6F是实施例的包括接合电极的半导体装置的制造工艺流程图；
图7G-7H是实施例的包括接合电极的半导体装置制造工艺流程图；
图8是示出包括接合电极的半导体装置的修改示例的示意性构造的截面图；
图9是示出固态成像设备的构造的示意图；以及
图10是示出电子设备的构造的示意图。
具体实施方式
在下文，将参照附图详细描述本公开的优选实施例。应注意，在说明书和附图中，实质上具有相同的功能和结构的结构要素用相同的参考标记表示，并且省略了这些结构要素的重复解释。
在下文，尽管将描述实施本公开的示例性实施例，但本公开不限于这些示例。
应注意描述将按以下顺序给出。
1.半导体装置的概要
2.半导体装置的实施例
3.制造实施例的半导体装置的方法
4.半导体装置的修改示例
5.电子设备的实施例
<1.半导体装置的概要>
[构造]
将描述半导体装置的接合电极的构造概要。
图1示出了相关领域的常规半导体装置的接合部分的构造截面图。对于该接合部分，具有多个半导体基板的构造，其中形成在每个表面上的配线层彼此相对并且形成在配线层的表面上的接合电极彼此接合。
图1中所示的接合部分表示了第一接合部分10和第二接合部分20接合在一起的状态。
第一接合部分10形成在图中未示出的半导体基板上。此外，第一接合部分10包括第一层间绝缘层11和第一接合电极12。第一接合电极12形成在第一层间绝缘层11内，并且在接合表面上第一接合电极12的表面从第一层间绝缘层11的表面露出。用于防止电极材料扩散到绝缘层的阻挡金属表面13设置在第一接合电极12和第一层间绝缘层11相接触的表面上。
第二接合部分20形成在图中未示出的半导体基板上，第二接合部分20不同于上述的第一接合部分10。此外，第二接合部分20包括第二层间绝缘层21和第二接合电极22。第二接合电极22形成在第二层间绝缘层21内，并且在接合表面上第二接合电极22的表面从第二层间绝缘层21的表面露出。此外，防止电极材料扩散到绝缘层的阻挡金属表面23设置在第二层间绝缘层21和第二接合电极22相接触的表面上。
[问题]
如上所述，在其上形成有第一接合电极12的表面和其上形成有第二接合电极22的表面形成为彼此相对的状态下，第一接合电极12和第二接合电极22彼此接合，第一接合部分10和第二接合部分20层叠在一起。这里，在接合表面和其上形成有电极的表面不完全匹配的偏离状态下第一接合电极12和第二接合电极22彼此接合。
此外，即使在偏离接合位置的情况下，通过电极之一形成大的面积，也可将第一接合电极12和第二接合电极22设计为不产生接合面积上的差异以确保接合的可靠性。
因此，在接合表面上，具有接合电极相接触的部分，也具有接合电极和层间绝缘层相接触的部分。就是说，在半导体装置的接合表面处，具有第一接合电极12和第二层间绝缘层21相接触的接触部分14。另外，具有第二接合电极22和第一层间绝缘层11相接触的接触部分24。
在接触部分14和24处，由于不同的材料（诸如构成接合电极的金属材料和构成层间绝缘层的无机氧化物等）彼此接触，所以接合性能降低。当接合性能降低时，存在于第一接合电极12和第二层间绝缘层21之间的界面中并于第二接合电极22和第一层间绝缘层11之间的界面中产生空隙（孔）的情况。在这种情况下，半导体装置的接合性能可能会发生问题，诸如接合性能劣化。
此外，如图2所示，由于构成接合电极的例如Cu的金属扩散到层间绝缘层中，所以可能会形成泄露路径15。这导致了半导体装置在绝缘性能上的缺陷并导致了阻挡性能上的问题。
在半导体基板的接合中，如果过通过精确匹配并接合接合界面处的接合电极而具有接合电极和层间绝缘层不彼此接触的构造，则不会发生上述问题。然而，接合时很难消除非常微小的偏离的发生。因此，难以通过防止接合的位置偏离来改进接合性能。
另外，由于各垂直接合电极的接合区域在结构上可能不相同，所以将不可避免地具有接合电极和层间绝缘层接触的表面。
因此，在通过接合电极接合的半导体装置中，需要即使在发生位置偏离的状态下也能防止接合性能劣化和阻挡性能劣化的构造。
<2.半导体装置的实施例>
[半导体装置的构造]
在下文，将描述包括接合电极的半导体装置的实施例。
图3示出了本公开实施例的包括接合电极的半导体装置的示意性构造。图3是本公开实施例的半导体装置的接合部分附近的截面图。应注意，在如图3所示的上述半导体装置30中，将从本实施例的描述中省略不必要的配线层等的描述。
如图3所示，半导体装置30包括形成在半导体基板31上的层间绝缘层32和形成在层间绝缘层32的表面上的接合电极33。另外，半导体装置30包括金属膜35，该金属膜35覆盖层间绝缘层32并覆盖接合电极33的表面。
在图中未示出的诸如电子电路和配线的多种元件形成在半导体基板31上。
例如，形成在层间绝缘层32的最外表面上的层由诸如SiO、HfO、GeO、GaO或SiON的氧化物形成，或由氮化物绝缘层和金属氧化物形成。其它层可采用相关领域已知的用于半导体装置的层间绝缘层的材料。接合电极33由相关领域已知的用于半导体装置的电极的材料（例如，Cu）形成。
阻挡表面层34由通常用于半导体装置中的阻挡金属层的例如Ta、Ti、Ru、TaN、TiN等的材料形成。
金属膜35通过覆盖半导体装置30的整个表面而形成。
此外，可通过热处理将金属膜35接合到半导体基板，并且可使用具有高导电率的金属。另外，金属膜35所采用的金属通过热处理在与层间绝缘层32接触的部分中与层间绝缘层32反应。所采用的金属使金属膜35的反应产物成为绝缘体，该绝缘体在与层间绝缘层32接触的部分上通过上述反应产生。例如，Ti、Ta等用作金属膜35中的金属。
此外，金属膜35形成为具有一定的厚度以使得与层间绝缘层32接触的所有部分由于上述的反应而成为反应产物。该厚度使得在热处理之后没有导电层保留在与层间绝缘层32接触的部分的表面上。如果导电层保留在上述表面上，则将引起相邻电极之间短路和漏电的增加。因此，尽管由于材料和热处理条件的组合而会存在差异，但可通过使金属膜35的厚度等于或小于100nm而实现直至表面的全部反应。此外，可通过使膜厚度等于或小于20nm而有利地展现上述特性。
此外，金属膜35形成为具有一定的厚度以使得与层间绝缘层32的反应产物具有足够的阻挡性能，该厚度例如为等于或大于5个分子层的厚度。
[半导体装置的接合]
接下来，图4示出了两个上述半导体装置30层叠在一起的构造。图4示出了具有相同构造的半导体装置30A和30B。半导体装置30A和30B构造为与图3中所示的上述半导体装置30相同，并且通过将A和B附加至各参考标记而示出。此外，由于半导体装置30A和30B的每一个部分与图3中所示的上述半导体装置30具有相同的构造，所以省略了它们的描述。
通过设置在配线形成侧的表面上的金属膜35A和35B，半导体装置30A和半导体装置30B之间的接合在形成有接合电极33A和33B的表面上进行。半导体基板通过上述接合并通过接合电极33A和33B而层叠在一起。此外，在接合电极33A和接合电极33B之间的平面位置偏离的状态下半导体装置30A和半导体装置30B被接合。
半导体基板31A的配线形成表面和半导体基板31B的配线形成表面彼此相对，并且之后半导体装置30A和半导体装置30B之间的上述接合使它们二者接触。此外，在金属膜35A和金属膜35B彼此接触的状态下进行热处理，金属膜35A和金属膜35B彼此接合。半导体基板31A和31B在金属膜35A和35B彼此接触的状态下通过热处理而层叠在一起。
此外，通过接合期间施加的热，在金属膜35A和35B与层间绝缘层32A和32B接触的部分中发生反应。当发生该反应时，作为金属膜和层间绝缘层之间的反应产物的绝缘体产生在金属膜35A和35B与层间绝缘层32A和32B接触的部分中。因此，金属膜35A和35B的形成在层间绝缘层32A和32B上的部分将由于反应产物而形成绝缘膜36A和36B。
此外，热处理之后，形成在接合电极33A和33B上的金属膜35A和35B保持了所形成的膜不发生变化的状态。
例如，在SiO2用于层间绝缘层32A并且Ti用于金属膜35A的情况下，由于上述反应包括TiO2的金属氧化物层将作为绝缘膜36A形成在层间绝缘层32A上。TiO2具有高阻挡特性或者高绝缘特性以用作常规的阻挡材料。
由于层间绝缘层32A和32B被绝缘膜36A和36B覆盖，所以接触不发生在接合性低的接合电极33A和33B与层间绝缘层32A和32B之间。因此，在接合界面中不产生空隙。因此，提高了接合半导体装置的可靠性。另外，可防止构成接合电极33A和33B的金属（例如Cu）扩散到层间绝缘层32A和32B中。因此，控制了泄露路径的形成，并且提高了半导体装置的可靠性。
应注意金属膜35A和35B可通过采用相同的金属材料或者采用诸如Ti和Ta的不同材料而被接合到接合的半导体装置30A和30B二者。即使在采用不同材料进行接合的情况下，也可使金属膜35A和35B彼此接合，并且当与层间绝缘层32接触的金属膜35变成绝缘层36时，可获得上述效果。
<3.制造半导体装置的方法>
接下来，将描述实施例的制造半导体装置的方法示例。应注意以下对制造方法的描述将仅示出图3所示的上述半导体装置30的接合部分附近的制造方法，并且用于制造形成在半导体基板31上的各种元件、配线等的构造的其他方法的描述将被省略。半导体基板、配线层、其他各种晶体管和各种元件的制造方法的描述也将省略。这些部分可通过相关领域中已知的方法来制造。此外，相同的参考标记附加到与如图3和4所示的上述实施例半导体装置的构造相同的构造，并且省略这些构造的每一个的详细描述。
首先，如图5A所示，层间绝缘层32形成在其上形成有各种元件的半导体基板31上。层间绝缘层32由多个层间绝缘层、配线等形成。所示的图中省略了层间绝缘层、配线层等的堆叠。
然后，如图5B所示，抗蚀剂层41形成在层间绝缘层32上。抗蚀剂层41形成为图案以露出用于形成半导体装置的接合电极的位置。
如图5C所示，通过自抗蚀剂层41上方进行采用常规磁控系统的蚀刻装置的干蚀刻，层间绝缘层32被蚀刻到预定的深度，开口部分42形成在层间绝缘层32的表面上。在蚀刻工艺之后，根据需要，施加基于例如氧（O2）等离子的灰化工艺和有机胺系统的化学工艺，并且清洗层间绝缘层32的表面。
接下来，如图6D所示，形成阻挡材料层43和电极材料层44，以形成阻挡金属层和接合电极。阻挡材料层43通过RF溅射工艺在Ar/N2环境下采用Ta、Ti、Ru、TaN等形成为5-50nm。电极材料层44通过采用电镀方法或溅射方法由Cu等形成在阻挡材料层43上。通过填埋已形成的开口部分42来形成电极材料层44。然后，在形成电极材料层44之后，通过采用热板或烧结退火装置，在100°C至400°C的温度下进行约1-60分钟的热处理。
接下来，通过化学机械平坦化（CMP）方法从已沉积的阻挡材料层43和电极材料层44中去除作为配线图案所不需要的部分。通过该工艺，如图6E所示，形成阻挡金属层34和接合电极33。
然后，如图6F所示，金属膜35通过覆盖接合电极33和层间绝缘层32的表面而形成在整个表面上。金属膜35通过采用ALD（原子层沉积）方法或CVD（化学气相沉积）方法，将诸如Ti或Ta的材料形成为10-100nm的厚度。
在形成金属膜35之后，根据需要通过采用CMP方法等在表面上进行平坦化工艺。
根据上述工艺，可形成半导体装置30。
此外，重复与图5A至6F中的上述方法相似的工艺，准备一对半导体装置30。
然后，例如，采用蚁酸（formic acid）的湿工艺或采用诸如Ar、NH3或H2的等离子的干工艺被施加到通过上述方法形成的两个半导体装置30的接合表面。通过该工艺，接合电极33表面上的氧化物膜被去除，并且露出干净的金属表面。
然后，如图7G所示，两个半导体装置的表面设置成彼此相对。然后，两个半导体装置彼此接触。在这种状态下，两个金属膜35不改变膜形成时的材料，并且两个半导体装置30的整个表面被覆盖。
此时，例如，通过诸如热板或RTA的退火装置，在大气压强的N2环境下或真空环境下，以100°C至400°C进行热处理约5分钟至2小时。
通过这样的热处理，与层间绝缘层32接触的部分处的金属膜35发生反应。这样，包括反应产物的绝缘膜36形成在两个半导体装置30的接合表面上。这样，在接合半导体装置30的同时，金属膜35和层间绝缘层32发生反应，并且可形成绝缘膜36。
根据上述工艺，可制造如图7H所示的本实施例的半导体装置。
应注意绝缘膜36的形成可在不同于半导体装置30的接合工艺的工艺中进行。例如，在图6F中形成金属膜35之后，对半导体装置30进行热处理，并且可形成绝缘膜36。
<4.半导体装置的修改示例>
接下来，将描述上述实施例的半导体装置的修改示例。
图8示出了修改示例的半导体装置的构造。除了形成在接合表面上的金属膜的构造，图8中所示的半导体装置的构造与图4中所示的上述半导体装置的构造相似。因此，相同参考标记附加到与图4中所示的半导体装置的构造相同的构造，并且将省略其描述。
对于图8所示的半导体装置50，一层金属膜35形成在接合表面上。这样，本实施例的半导体装置可具有这样的构造：仅在一个半导体装置的接合表面上形成金属膜，并且金属膜不形成在另一半导体装置的接合表面上。例如，具有图8所示构造的半导体装置具有这样的构造：金属膜35A形成在半导体装置30A的接合表面上，并且金属膜不形成在半导体装置30B的接合表面上。
然后，在半导体装置30A和半导体装置30B层叠在一起之后，与层间绝缘层32A和32B接触的部分处的金属膜35A由于进行热处理而发生反应，并且成为绝缘膜36A。
在具有图8所示构造的半导体装置50中，尽管与层间绝缘层32A和32B接触的部分处的金属膜35A成为绝缘膜36A，但是在接合电极33A和接合电极33B之间的位置处的金属膜35A不变成绝缘膜。因此，接合电极33A和接合电极33B之间的导通可由金属膜35A来保证。
此外，由于与层间绝缘层32A和32B接触的部分处的金属膜35A成为绝缘膜36A，所以层间绝缘层32A和32B的顶部被绝缘膜36A覆盖。结果，接触不发生在接合性低的接合电极33A和33B与层间绝缘层32A和32B之间，并且由于在接合表面中产生空隙而引起的半导体装置的接合可靠性的降低能够被控制。
另外，通过覆盖绝缘层32A和32B的顶部的绝缘膜36A，可防止构成接合电极33A和33B的金属（例如Cu）扩散到层间绝缘层32A和32B中。因此，控制了泄露路径的形成，并且提高了半导体装置的可靠性。
<5.电子设备的实施例>
可将上述实施例的半导体装置应用到通过将两个半导体构件层叠在一起来进行配线接合的任意的电子设备，例如固态成像设备、半导体存储器或者半导体逻辑装置（诸如IC）。
[固态成像设备]
在下文，将描述将上述实施例的电极接合的构造应用到固态成像设备的示例。
图9示出了根据本公开实施例的固态成像设备的主要部分的示意性截面图。应注意为了简化图9的描述，将省略示出电极接合部分之间形成的阻挡金属层、通孔和层间绝缘层的部分。
本实施例的固态成像设备200包括：具有光电转换部分210的第一半导体构件201、具有构成操作电路的各MOS（金属氧化物半导体）晶体管220的第二半导体构件202。此外，固态成像设备200包括彩色滤光片203和芯片上微透镜204。
在本实施例的固态成像设备200中，第一半导体构件201和第二半导体构件202在接合表面处接合在一起。此外，在本实施例中，彩色滤光片203和芯片上微透镜204依序堆叠在第一半导体构件201的与第二半导体构件202侧相反的顶表面上（依序堆叠在光电转换层211上）。
第一半导体构件201包括光电转换层211和第一多层配线部分212，光电转换层211具有光电转换部分210，第一多层配线部分212设置在光电转换层211的与彩色滤光片203相反的一侧。
第一多层配线部分212通过堆叠多个配线层213来构造。配线层213的每一个具有层间绝缘层214、第一接合部分215以及通孔216，第一接合部分215嵌设在层间绝缘层214内，通孔216设置为获得自层本身到彩色滤光片203侧的各层（各配线层213或光电转换层211）之间的电连接。此外，在本实施例中，中间层217设置在相互邻接的配线层213之间，并且设置在配线层213和光电转换层211之间。
另一方面，第二半导体构件202包括晶体管部分221和第二多层配线部分222，在晶体管部分221中形成构成操作电路的各MOS晶体管220，第二多层配线部分222设置在晶体管部分221的朝着第一半导体构件201的一侧。
第二多层配线部分222通过堆叠多个配线层223来构造。配线层223的每一个具有层间绝缘层224、第二接合部分225和通孔226，第二接合部分225嵌设在层间绝缘层224内，通孔226设置为获得自层本身到晶体管部分221侧的各层（各配线层223或晶体管部分221）之间的电连接。此外，在本实施例中，中间层227设置在相互邻接的配线层223之间，并且设置在配线层223和晶体管部分221之间。
在具有上述构造的固态成像设备200中，上述实施例1-3的任一个中的第一接合部分和第二接合部分的构造可分别应用于遍及接合表面被接合的第一接合部分215和第二接合部分225。在这种情况下，可获得具有更可靠的接合表面的固态成像设备200。
[照相机]
上述固态成像设备可应用到电子设备，诸如数字照相机、摄像机等的照相系统、具有成像功能的移动电话或者包括成像功能的其他设备。在下文，例如将描述照相机以作为电子设备的示例性构造。
图10示出了可拍摄静止图像或运动图像的摄像机的示例性构造。该示例的照相机300包括固态成像设备301、将入射光引入到固态成像设备301的光接收传感器部分的光学系统302、设置在固态成像设备301和光学系统302之间的快门装置303以及驱动固态成像设备301的驱动电路304。另外，照相机300包括对固态成像设备301的输出信号进行处理的信号处理电路305。
固态成像设备301可采用根据本公开上述实施例的实施例和修改示例的金属电极接合技术来制造。以下是其他每个部分的构造和功能。
光学系统（光学镜头）302将来自拍摄物体的图像光（入射光）形成在固态成像设备301的成像表面（图中未示出）上。这样，信号负荷以固定的时间被存储在固态成像设备301中。应注意光学系统302可由包括多个光学透镜的光学透镜组来构造。此外，快门装置303为固态成像设备301的入射光控制光照射时间和光屏蔽时间。
驱动电路304将驱动信号提供到固态成像设备301和快门装置303。此外，驱动电路304根据所提供的驱动信号控制固态成像设备301到信号处理电路305的信号输出操作和快门装置303的快门操作。就是说，在该示例中，根据从驱动电路304提供的驱动信号（定时信号），从固态成像设备301到信号处理电路305进行信号传输操作。
信号处理电路305将各种信号处理施加到自固态成像设备301传输的信号。此外，已经被施加各种信号处理的信号（视频信号）存储在诸如存储器（图中未示出）的存储介质中，或者输出到监视器（图中未示出）。
此外，本公开也可如下构造。
（1）一种半导体装置，包括：
半导体基板；
层间绝缘层，形成在该半导体基板上；
接合电极，形成在该层间绝缘层的表面上；以及
金属膜，覆盖包括该层间绝缘层和该接合电极的接合表面的整个表面。
（2）根据（1）的半导体装置，
其中该金属膜包括由于与该层间绝缘层的反应而变为绝缘体的金属材料。
（3）根据（1）或（2）的半导体装置，
其中该金属膜包括从Ta或Ti选择的至少一种。
（4）一种包括第一半导体基板和第二半导体基板的半导体装置，该半导体装置通过隔着金属膜层叠接合电极的表面而形成，该半导体装置包括：
第一半导体基板；
第一层间绝缘层，形成在该第一半导体基板上；
第一接合电极，形成在该第一层间绝缘层的表面上；
第二半导体基板，接合到该第一半导体基板；
第二层间绝缘层，形成在该第二半导体基板上；
第二接合电极，形成在该第二层间绝缘层的表面上；
金属膜，形成在该第一半导体基板和该第二半导体基板之间的接合表面上并位于该第一接合电极和该第二接合电极之间；以及
绝缘膜，形成在该第一半导体基板和该第二半导体基板之间的该接合表面上并位于与该第一层间绝缘层或该第二层间绝缘层接触的部分上，该绝缘膜包括该金属膜和该第一层间绝缘层或该金属膜与该第二层间绝缘层之间的反应产物。
（5）根据（4）的半导体装置，还包括：
第一金属膜，形成在该第一半导体基板的该第一接合电极上；
第一绝缘膜，形成在该第一层间绝缘层上，并且包括该第一金属膜与该第一层间绝缘层或该第一金属膜与该第二层间绝缘层之间的反应产物；
第二金属膜，形成在该第二半导体基板的该第二接合电极上；以及
第二绝缘膜，形成在该第二层间绝缘层上，并且包括该第二金属膜与该第一层间绝缘层或该第二金属膜与该第二层间绝缘层之间的反应产物。
（6）一种制造半导体装置的方法，包括：
在半导体基板上形成层间绝缘层；
在该层间绝缘层的表面上形成接合电极；以及
在该层间绝缘层和该接合电极的整个表面上形成金属膜。
（7）一种电子设备，包括：
根据（1）至（5）中任一项的半导体装置；以及
处理该半导体装置的输出信号的信号处理电路。
本领域的技术人员应当理解的是，在所附权利要求或其等同方案的范围内，根据设计需要和其他因素，可以进行各种修改、结合、部分结合和替换。
本申请包含2012年2月14日提交至日本专利局的日本优先权专利申请JP2012-029429中公开的相关主题事项，其全部内容通过引用结合于此。

Claims (7)

1.一种半导体装置，包括：
半导体基板；
层间绝缘层，形成在该半导体基板上；
接合电极，形成在该层间绝缘层的表面上；以及
金属膜，覆盖包括该层间绝缘层和该接合电极的接合表面的整个表面。
2.根据权利要求1所述的半导体装置，
其中该金属膜包括由于与该层间绝缘层的反应而变为绝缘体的金属材料。
3.根据权利要求1所述的半导体装置，
其中该金属膜包括从Ta或Ti选择的至少一种。
4.一种包括第一半导体基板和第二半导体基板的半导体装置，该半导体装置通过隔着金属膜层叠接合电极的表面而形成，该半导体装置包括：
该第一半导体基板；
第一层间绝缘层，形成在该第一半导体基板上；
第一接合电极，形成在该第一层间绝缘层的表面上；
该第二半导体基板，接合到该第一半导体基板；
第二层间绝缘层，形成在该第二半导体基板上；
第二接合电极，形成在该第二层间绝缘层的表面上；
金属膜，形成在该第一半导体基板和该第二半导体基板之间的接合表面上并位于该第一接合电极和该第二接合电极之间；以及
绝缘膜，形成在该第一半导体基板和该第二半导体基板之间的该接合表面上并位于与该第一层间绝缘层或该第二层间绝缘层接触的部分上，该绝缘膜包括该金属膜和该第一层间绝缘层或该金属膜与该第二层间绝缘层之间的反应产物。
5.根据权利要求4所述的半导体装置，还包括：
第一金属膜，形成在该第一半导体基板的该第一接合电极上；
第一绝缘膜，形成在该第一层间绝缘层上，并且包括该第一金属膜与该第一层间绝缘层或该第一金属膜与该第二层间绝缘层之间的反应产物；
第二金属膜，形成在该第二半导体基板的该第二接合电极上；以及
第二绝缘膜，形成在该第二层间绝缘层上，并且包括该第二金属膜与该第一层间绝缘层或该第二金属膜与该第二层间绝缘层之间的反应产物。
6.一种制造半导体装置的方法，包括：
在半导体基板上形成层间绝缘层；
在该层间绝缘层的表面上形成接合电极；以及
在该层间绝缘层和该接合电极的整个表面上形成金属膜。
7.一种电子设备，包括：
半导体装置，该半导体装置包括：
半导体基板，
层间绝缘层，形成在该半导体基板上，
接合电极，形成在该层间绝缘层的表面上，以及
金属膜，覆盖包括该层间绝缘层和该接合电极的接合表面的整个表面；以及
信号处理电路，处理该半导体装置的输出信号。
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