CN107534014A - 半导体装置、制造方法、固态成像元件和电子设备 - Google Patents

半导体装置、制造方法、固态成像元件和电子设备 Download PDF

Info

Publication number
CN107534014A
CN107534014A CN201680023993.1A CN201680023993A CN107534014A CN 107534014 A CN107534014 A CN 107534014A CN 201680023993 A CN201680023993 A CN 201680023993A CN 107534014 A CN107534014 A CN 107534014A
Authority
CN
China
Prior art keywords
film
interlayer film
semiconductor substrate
base plate
connection pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201680023993.1A
Other languages
English (en)
Other versions
CN107534014B (zh
Inventor
羽根田雅希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to CN202111127348.3A priority Critical patent/CN113990839B/zh
Priority to CN202111127293.6A priority patent/CN113990838B/zh
Priority to CN202210389474.4A priority patent/CN114899201A/zh
Priority to CN202210388793.3A priority patent/CN114899200A/zh
Publication of CN107534014A publication Critical patent/CN107534014A/zh
Application granted granted Critical
Publication of CN107534014B publication Critical patent/CN107534014B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05007—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05618—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/0566—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0801—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

本公开涉及一种进一步提高了可靠性的半导体装置、制造方法、固态成像元件和电子设备。在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内形成有用于使所述传感器基板和所述信号处理基板彼此电气连接的连接焊盘，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板对所述传感器基板进行信号处理。然后，在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的连接焊盘和所述信号处理基板侧的层间膜之间以及在所述信号处理基板侧形成的连接焊盘和在所述传感器基板侧的层间膜之间形成有金属氧化膜。本技术可以适用于例如层叠型CMOS图像传感器。

Description

半导体装置、制造方法、固态成像元件和电子设备
技术领域
本公开涉及一种半导体装置、制造方法、固态成像元件和电子设备，更具体地，涉及一种可以实现可靠性的进一步提高的半导体装置、制造方法、固态成像元件和电子设备。
背景技术
通常，例如，诸如电荷耦合器件(CCD)或互补金属氧化物半导体(CMOS)图像传感器等固态成像元件用在诸如数码相机或数码摄像机等设有成像功能的电子设备中。固态成像元件具有其中组合了进行光电转换的光电二极管和多个晶体管的像素，并且基于从多个像素输出的像素信号来创建图像，所述多个像素配置在其上产生被摄体的图像的像平面上。
此外，近年来，为了实现固态成像元件的小型化和高性能，已经开发了一种层叠型固态成像元件，其中在传感器基板(其上形成有像素)上层叠有对从传感器基板输出的图像信号进行信号处理的信号处理基板。在这种层叠型固态成像元件中，执行诸如对晶片的接合面进行物理连接以及对形成在接合面上的连接焊盘进行电连接等复合接合。
例如，专利文献1公开了一种半导体装置，其中通过在两个半导体基板的整个接合面上形成金属膜并在金属膜彼此接触的状态下进行热处理，与层间绝缘层接触的一部分金属膜发生反应而形成绝缘膜。
[引用文献列表]
[专利文献]
专利文献1：JP2013-168419A
发明内容
[发明所要解决的技术问题]
另一方面，通常，当接合晶片时可能发生未对准，从而导致其中一个晶片的连接焊盘(Cu)的一部分被接合到另一个晶片的绝缘层(SiO2)上的结构。在这种结构中，在连接焊盘与绝缘层之间的界面处没有设置阻挡金属。这引起了以下担忧：在进行加热的后续处理(例如，诸如接合后退火(post bond anneal)或ILD沉积等)中构成连接焊盘的铜从连接焊盘与绝缘层之间的界面扩散到绝缘层中，从而造成泄漏。
此外，连接焊盘(Cu)和绝缘层(SiO2)之间的低粘合强度引起了整体接合强度(晶片接合强度)降低的担忧。因此，降低了电迁移(Electro Migration)阻力和应力诱生空洞(Stress Induced Voiding)阻力等，从而导致整体上可靠性的下降。
鉴于这些情况而完成了本公开，并且本公开可以实现可靠性的进一步提高。
[解决问题的方案]
本公开一个方面的半导体装置包括：连接焊盘，所述连接焊盘形成在分别设置于第一半导体基板的配线层中和第二半导体基板的配线层中的层间膜内，以在所述第一半导体基板和所述第二半导体基板之间形成电连接；和金属氧化膜，所述金属氧化膜形成在所述第一半导体基板的层间膜和所述第二半导体基板的层间膜之间、在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧的所述层间膜之间以及在所述第二半导体基板侧形成的所述连接焊盘和在所述第一半导体基板侧的所述层间膜之间。
在本公开一个方面的半导体装置的制造方法中，所述半导体装置包括：连接焊盘，所述连接焊盘形成在分别设置于第一半导体基板的配线层中和第二半导体基板的配线层中的层间膜内，以在所述第一半导体基板和所述第二半导体基板之间形成电连接；和金属氧化膜，所述金属氧化膜形成在所述第一半导体基板的层间膜和所述第二半导体基板的层间膜之间、在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧的所述层间膜之间以及在所述第二半导体基板侧形成的所述连接焊盘和在所述第一半导体基板侧的所述层间膜之间。所述方法包括以下步骤：在包括在所述第一半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面以及包括在所述第二半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面中的至少一个接合面上形成金属膜；和通过在其中以所述金属膜介于所述第一半导体基板和所述第二半导体基板之间的方式使所述第一半导体基板和所述第二半导体基板彼此紧密接触的状态下进行热处理，自发形成由所述金属膜和所述层间膜之间的反应产生的所述金属氧化膜。
本公开一个方面的固态成像元件包括：连接焊盘，所述连接焊盘形成在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内，以在所述传感器基板和所述信号处理基板之间形成电连接，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板构造成对所述传感器基板进行信号处理；和金属氧化膜，所述金属氧化膜形成在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的所述连接焊盘和在所述信号处理基板侧的所述层间膜之间以及在所述信号处理基板侧形成的所述连接焊盘和在所述传感器基板侧的所述层间膜之间。
本公开一个方面的电子设备包括固态成像元件，所述固态成像元件包括：连接焊盘，所述连接焊盘形成在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内，以在所述传感器基板和所述信号处理基板之间形成电连接，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板构造成对所述传感器基板进行信号处理；和金属氧化膜，所述金属氧化膜形成在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的所述连接焊盘和在所述信号处理基板侧的所述层间膜之间以及在所述信号处理基板侧形成的所述连接焊盘和在所述传感器基板侧的所述层间膜之间。
在本公开的一个方面中，连接焊盘形成在分别设置于第一半导体基板(传感器基板)的配线层中和第二半导体基板(信号处理基板)的配线层中的层间膜内，以在第一半导体基板和第二半导体基板之间形成电连接。另外，金属氧化膜形成在第一半导体基板的层间膜和第二半导体基板的层间膜之间、在第一半导体基板侧形成的连接焊盘和在第二半导体基板侧的层间膜之间以及在第二半导体基板侧形成的连接焊盘和在第一半导体基板侧的层间膜之间。
[本发明的有益效果]
根据本公开的一个方面，可以实现可靠性的进一步提高。
附图说明
图1是示出了本技术适用的固态成像元件的实施方案的构成例的图。
图2是说明固态成像元件的制造方法的图。
图3是示出了安装在电子设备上的成像装置的构成例的框图。
图4是示出了使用图像传感器的使用例的图。
具体实施方式
在下文中，参照附图对本技术适用的具体实施方案进行详细说明。
图1是示出了作为本技术适用的半导体装置的固态成像元件的实施方案的构成例的图。
在图1中，示出了固态成像元件11的断面构成例及其放大部分。
如图1所示，固态成像元件11通过使其上形成有传感器表面12的传感器基板13和以支撑传感器基板13的方式连接的信号处理基板14层叠来构成，传感器表面12配置在像平面上，通过未示出的光学系统在该像平面上产生被摄体的图像。
在传感器表面12中，作为接收光并将其转换为电荷的光电转换部的光电二极管配置成矩阵形式，并且当其像素接收光时进行成像。
例如，传感器基板13通过使其中形成有构成像素的光电二极管和晶体管等的硅层以及其中形成有待与像素连接的配线的配线层层叠来构成，并输出在传感器表面12上成像的图像的图像信号。例如，配线层通过在由二氧化硅(SiO2)制成的层间膜15内形成具有导电性的金属配线来构成。
信号处理基板14对从传感器基板13输出的图像信号进行各种类型的信号处理，然后，将图像信号输出到后级图像处理电路(later-stage image processing circuit)。此外，信号处理基板14设有其中形成有用于捕获从传感器基板13输出的图像信号的配线的配线层，并且该配线层设有与传感器基板13的层间膜15类似的层间膜16。
以这种方式，固态成像元件11通过层叠传感器基板13和信号处理基板14来构成，并且传感器基板13和信号处理基板14进行物理和电接合。例如，在图1的右侧，以放大方式示出了在传感器基板13和信号处理基板14之间形成电连接的两个接合端子部21-1和21-2附近的断面构成例。
在传感器基板13和信号处理基板14的接合面中，在整个表面上除了形成接合端子部21-1,21-2的位置以外的所有位置都形成有金属氧化膜22。
此外，在接合端子部21-1中形成有其中在传感器基板13的层间膜15侧形成的连接焊盘和在信号处理基板14的层间膜16侧形成的连接焊盘接合成一体的连接焊盘23-1，并且形成电连接。连接焊盘23-1的在层间膜15的那侧由阻挡金属24a-1覆盖，并且连接焊盘23-1的在层间膜16的那侧由阻挡金属24b-1覆盖。类似地，对于形成在接合端子部21-2中的连接焊盘23-2，连接焊盘23-2的在层间膜15的那侧由阻挡金属24a-2覆盖，并且连接焊盘23-2的在层间膜16的那侧由阻挡金属24b-2覆盖。
需要指出的是，接合端子部21-1,21-2具有类似的构造，并且在下文中，根据需要，在不需要区分接合端子部21-1,21-2的情况下，它们将被简单地称为接合端子部21。类似地，连接焊盘23-1,23-2将被称为连接焊盘23，阻挡金属24a-1,24a-2将被称为阻挡金属24a，阻挡金属24b-1,24b-2将被称为阻挡金属24b。
这里，当接合传感器基板13和信号处理基板14时，进行用于使形成在传感器基板13的层间膜15中的连接焊盘与形成在信号处理基板14的层间膜16中的连接焊盘对准的调整。此时，如果可以将它们的位置完全匹配，则连接焊盘23可以由阻挡金属24a,24b覆盖。然而，实际上，会发生略微的未对准。因此，如图1所示，连接焊盘23形成为其中在层间膜15侧的部分和在层间膜16侧的部分未对准的形状。
固态成像元件11构造成使得即使发生这种未对准，通过形成金属氧化膜22也会使连接焊盘23不与层间膜15,16直接接触。即，在固态成像元件11中，在传感器基板13的层间膜15和信号处理基板14的层间膜16之间、在传感器基板13侧形成的连接焊盘23和信号处理基板14的层间膜16之间以及在信号处理基板14侧形成的连接焊盘23和传感器基板13的层间膜15之间形成有金属氧化膜22。
由于以这种方式形成的金属氧化膜22用作扩散阻挡层的事实，所以可以防止构成连接焊盘23的铜扩散到层间膜15或层间膜16中，并且可以抑制泄漏的发生(配线间的短路)。
此外，已知的是，构成连接焊盘23的铜与构成层间膜15,16的SiO2之间的粘合强度较低。在这方面，在固态成像元件11中，如稍后参照图2所说明的，可以在连接焊盘23和层间膜15,16之间的界面处自发形成金属氧化膜22，从而可以确保粘合强度。因此，固态成像元件11可以具有较高的电迁移阻力和较高的应力迁移阻力，并且可以获得比常规更高的可靠性。
接着，参照图2对固态成像元件11的制造方法中的传感器基板13和信号处理基板14的接合步骤进行说明。
首先，在进行传感器基板13和信号处理基板14的接合步骤之前，通过镶嵌工艺分别在传感器基板13和信号处理基板14上形成连接焊盘23a,23b。
这里，对在传感器基板13的层间膜15中形成连接焊盘23a的步骤进行说明。首先，通过光刻和干蚀刻在用作层间膜15的二氧化硅(SiO2)或等同绝缘膜中形成配线沟槽，并且在该配线沟槽中形成用作连接焊盘23a和层间膜15之间的扩散阻挡层的阻挡金属24a。例如，阻挡金属24a可以通过使钽(Ta)进行物理气相沉积(PVD)来形成。
此后，例如，通过物理气相沉积形成在后续处理的电镀工艺中用作电极的铜(铜合金)晶种层，然后，通过电镀工艺填充铜，并通过化学机械抛光(CMP)来去除过量的铜，以在配线沟槽中填充铜。通过这样的步骤，形成连接焊盘23a。另外，通过相似的步骤，在信号处理基板14的层间膜16中以阻挡金属24b用作扩散阻挡层而形成连接焊盘23b。
然后，在层间膜15和连接焊盘23a的整个表面上形成金属膜31a。类似地，在层间膜16和连接焊盘23b的整个表面上形成金属膜31b。此时，金属膜31a,31b包含锰(Mn)、钒(V)、铝(Al)、镁(Mg)、锆(Zr)中的至少一种或多种元素，并且通过使其沉积成具有约0.1～10nm的厚度来构成。
例如，作为这种金属膜31a,31b采用的金属，选择具有在后续的热处理中与构成层间膜15,16的SiO2反应以产生氧化物的性质的金属。因此，可以抑制在连接焊盘23之间发生泄漏。即，期望使用具有用作防止铜扩散的阻挡层的绝缘性质以及熔融进入构成连接焊盘23的铜中(其不妨碍连接焊盘23的界面的导通)的性质的氧化物。
因此，如图2的上部所示，在传感器基板13中，在层间膜15和连接焊盘23a的整个表面上形成有金属膜31a，并且在信号处理基板14中，在层间膜16和连接焊盘23b的整个表面上形成有金属膜31b。然后，使传感器基板13的金属膜31a和信号处理基板14的金属膜31b彼此面对，调整对准使得连接焊盘23a,23b的位置匹配。
然后，如图2的中部所示，进行如下步骤：使传感器基板13的金属膜31a的整个表面和信号处理基板14的金属膜31b的整个表面紧密接触并将它们接合，使得不存在它们未彼此接合的区域。此时，例如，在传感器基板13的接合面和信号处理基板14的接合面中的任一方的整个表面上形成有金属膜31的状态下进行接合。需要指出的是，优选在进行该步骤之前，通过使用含氢的液体或气体来对金属膜31a和金属膜31b进行预处理，以通过氢键来提高接合强度。
此后，例如，在传感器基板13和信号处理基板14保持紧密接触的情况下，进行施加400度以下的热负荷的步骤。
因此，如图2的下部所示，金属膜31a,31b熔融进入构成连接焊盘23a,23b的铜中，并且自发形成由金属和氧化膜之间的反应产生的金属氧化膜22。即，作为最终结构，在连接焊盘23和层间膜15,16之间形成有金属氧化膜22，连接焊盘23a,23b形成一体，并且在其界面处不存在金属膜31。需要指出的是，通常已知的是许多金属容易发生氧化，而在将用作常规扩散阻挡层的金属(例如，钽)用于金属膜31a,31b的情况下，钽的扩散阻挡功能将因氧化而失去，因此元素选择很重要。
通过如上所述的步骤，对传感器基板13和信号处理基板14进行物理和电接合。
通过这种制造方法制造的固态成像元件11由于金属氧化膜22用作扩散阻挡层的事实而可以抑制连接焊盘23之间发生泄漏(配线间的短路)。此外，由于可以通过自发形成金属氧化膜22来确保粘合强度，所以可以实现可靠性的进一步提高。
此外，如上所述，固态成像元件11可以获得良好的传导特性，原因是在连接焊盘23a,23b之间的界面处不存在金属膜31。例如，在使用即使在热处理之后仍使金属膜31保持在连接焊盘23a,23b之间的界面处的金属元素(例如，钛)的情况下，电阻值会增大。与此相反，在固态成像元件11中，可以避免电阻值的这种增大。需要指出的是，在连接焊盘23中检测到构成存在于连接焊盘23a,23b之间的金属膜31的元素。
另外，固态成像元件11通过使金属膜31a,31b具有约0.1～10nm的厚度以使金属氧化膜22形成为较薄可以有利地抑制泄漏的发生。
需要指出的是，如参照图2所说明的，不必在传感器基板13的层间膜15和信号处理基板14的层间膜16上都形成金属膜31，而是金属膜31应该仅形成在它们中的至少一个上，并且其仅应该构造成可靠地形成金属氧化膜22。
此外，作为可以用于金属膜31的元素，除了上述那些元素以外，还可以使用镍(Ni)、钴(Co)、铁(Fe)、锌(Zn)或银(Ag)。例如，虽然专利文献1公开了其中钛(Ti)用于金属膜的构成例，但是钛会容易发生氧化，同时易于形成其中正常状态下显示的反应性丧失的钝化状态，从而会发生不能使整个薄膜氧化的状态。将易于形成钝化状态的这种金属用于固态成像元件11的金属膜31是不合适的，但是将诸如锰等不形成钝化状态的金属用于固态成像元件11的金属膜31是合适的。
需要指出的是，例如，除了如上所述的固态成像元件11之外，本技术还可以适用于通过接合晶片构成的各种层叠型半导体装置(例如，存储器)。
需要指出的是，例如，如上所述的各实施方案的固态成像元件11可以适用于诸如成像系统(例如，数字静态相机或数码摄像机等)、具有成像功能的移动电话或具有成像功能的其他设备等各种类型的电子设备。
图3是示出了安装在电子设备上的成像装置的构成例的框图。
如图3所示，成像装置101包括光学系统102、成像元件103、信号处理电路104、显示器105和存储器106，并且能够拍摄静止图像和运动图像。
光学系统102具有一个或多个透镜，并且将来自被摄体的图像光(入射光)引导到成像元件103，以在成像元件103的光接收面(传感器部分)上产生图像。
作为成像元件103，适用上述实施方案的固态成像元件11。在成像元件103中，根据经由光学系统102在光接收面上产生的图像而蓄积一定时间段的电子。然后，将与成像元件103中蓄积的电子相对应的信号供给到信号处理电路104。
信号处理电路104对从成像元件103输出的像素信号进行各种类型的信号处理。通过进行信号处理的信号处理电路104获得的图像(图像数据)被供给到用于显示的显示器105，或被供给到用于存储(记录)的存储器106。
例如，以这种方式构造的成像装置101通过应用上述实施方案的固态成像元件11可以进一步提高耐久性，并且可以可靠地进行成像。
图4是示出了使用上述固态成像元件11(图像传感器)的使用例的图。
例如，上述图像传感器可以用于以下检测诸如可见光、红外光、紫外光或X-射线等光的各种情况：
-用于拍摄鉴赏用的图像的装置，诸如数码相机和具有相机功能的便携设备等
-用于交通用途的装置，用于诸如自动停车等安全驾驶以及识别驾驶员的状态等的拍摄汽车的前方、后方、周围和车辆内部等的图像的车载相机、监视行进车辆和道路的监视相机和测量车辆等之间的距离的距离测量传感器等
-用于诸如TV、冰箱、空调等家用电器中的装置，用以拍摄使用者的手势并根据该手势进行设备操作
-用于医疗和保健用途的装置，诸如内窥镜和通过接收红外光进行进行血管造影的装置等
-用于安保用途的装置，诸如用于预防犯罪用途的监视相机和用于个人认证用途的相机等，
-用于美容用途的装置，诸如拍摄皮肤图像的皮肤测量仪器和拍摄头皮图像的显微镜等，
-用于运动用途的装置，诸如用于运动用途的动作相机和可穿戴相机等，
-用于农业用途的装置，诸如用于监测田地和农作物状态的相机等。
另外，本技术还可以具有以下构成。
(1)一种半导体装置，包括：
连接焊盘，所述连接焊盘形成在分别设置于第一半导体基板的配线层中和第二半导体基板的配线层中的层间膜内，以在所述第一半导体基板和所述第二半导体基板之间形成电连接；和
金属氧化膜，所述金属氧化膜形成在所述第一半导体基板的层间膜和所述第二半导体基板的层间膜之间、在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧的所述层间膜之间以及在所述第二半导体基板侧形成的所述连接焊盘和在所述第一半导体基板侧的所述层间膜之间。
(2)根据(1)所述的半导体装置，其中
在包括在所述第一半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面以及包括在所述第二半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面中的至少一个接合面上形成有金属膜，和
通过在其中以所述金属膜介于所述第一半导体基板和所述第二半导体基板之间的方式使所述第一半导体基板和所述第二半导体基板彼此紧密接触的状态下进行热处理，自发形成由所述金属膜和所述层间膜之间的反应产生的所述金属氧化膜。
(3)根据(2)所述的半导体装置，其中
所述金属膜由具有以下性质的金属构成：在所述热处理中，介于在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧形成的所述连接焊盘之间的部分所述金属膜熔融进入所述连接焊盘中。
(4)根据(2)或(3)所述的半导体装置，其中
所述金属膜由具有在所述热处理中与所述层间膜反应以形成具有绝缘性的氧化物的性质的金属构成。
(5)根据(2)～(4)中任一项所述的半导体装置，其中
所述金属膜包含锰、钒、铝、镁和锆中的至少一种或多种的元素。
(6)根据(2)～(5)中任一项所述的半导体装置，其中
所述金属膜形成为具有0.1nm～10nm的厚度。
(7)根据(2)～(6)中任一项所述的半导体装置，其中
在所述金属膜已经形成在所述层间膜和所述连接焊盘的整个表面上的状态下，通过使用含氢的液体或气体对所述金属膜进行预处理。
(8)根据(2)～(7)中任一项所述的半导体装置，其中
当接合所述第一半导体基板和所述第二半导体基板时，在所述金属膜已经形成在所述接合面中的至少一个的整个表面上的状态下进行接合。
(9)一种半导体装置的制造方法，其中
所述半导体装置包括：
连接焊盘，所述连接焊盘形成在分别设置于第一半导体基板的配线层中和第二半导体基板的配线层中的层间膜内，以在所述第一半导体基板和所述第二半导体基板之间形成电连接；和
金属氧化膜，所述金属氧化膜形成在所述第一半导体基板的层间膜和所述第二半导体基板的层间膜之间、在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧的所述层间膜之间以及在所述第二半导体基板侧形成的所述连接焊盘和在所述第一半导体基板侧的所述层间膜之间，
所述方法包括以下步骤：
在包括在所述第一半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面以及包括在所述第二半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面中的至少一个接合面上形成金属膜；和
通过在其中以所述金属膜介于所述第一半导体基板和所述第二半导体基板之间的方式使所述第一半导体基板和所述第二半导体基板彼此紧密接触的状态下进行热处理，自发形成由所述金属膜和所述层间膜之间的反应产生的所述金属氧化膜。
(10)一种固态成像元件，包括：
连接焊盘，所述连接焊盘形成在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内，以在所述传感器基板和所述信号处理基板之间形成电连接，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板构造成对所述传感器基板进行信号处理；和
金属氧化膜，所述金属氧化膜形成在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的所述连接焊盘和在所述信号处理基板侧的所述层间膜之间以及在所述信号处理基板侧形成的所述连接焊盘和在所述传感器基板侧的所述层间膜之间。
(11)一种电子设备，包括：
固态成像元件，所述固态成像元件包括：
连接焊盘，所述连接焊盘形成在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内，以在所述传感器基板和所述信号处理基板之间形成电连接，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板构造成对所述传感器基板进行信号处理；和
金属氧化膜，所述金属氧化膜形成在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的所述连接焊盘和在所述信号处理基板侧的所述层间膜之间以及在所述信号处理基板侧形成的所述连接焊盘和在所述传感器基板侧的所述层间膜之间。
另外，本公开的实施方案不限于上述实施方案，并且可以在本公开的范围内进行各种修改。
附图标记列表
11 固态成像元件
12 传感器表面
13 传感器基板
14 信号处理基板
15,16 层间膜
21 接合端子部
22 金属氧化膜
23 连接焊盘
24 阻挡金属
31 金属膜

Claims (11)

1.一种半导体装置，包括：
连接焊盘，所述连接焊盘形成在分别设置于第一半导体基板的配线层中和第二半导体基板的配线层中的层间膜内，以在所述第一半导体基板和所述第二半导体基板之间形成电连接；和
金属氧化膜，所述金属氧化膜形成在所述第一半导体基板的层间膜和所述第二半导体基板的层间膜之间、在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧的所述层间膜之间以及在所述第二半导体基板侧形成的所述连接焊盘和在所述第一半导体基板侧的所述层间膜之间。
2.根据权利要求1所述的半导体装置，其中
在包括在所述第一半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面以及包括在所述第二半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面中的至少一个接合面上形成有金属膜，和
通过在其中以所述金属膜介于所述第一半导体基板和所述第二半导体基板之间的方式使所述第一半导体基板和所述第二半导体基板彼此紧密接触的状态下进行热处理，自发形成由所述金属膜和所述层间膜之间的反应产生的所述金属氧化膜。
3.根据权利要求2所述的半导体装置，其中
所述金属膜由具有以下性质的金属构成：在所述热处理中，介于在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧形成的所述连接焊盘之间的部分所述金属膜熔融进入所述连接焊盘中。
4.根据权利要求2所述的半导体装置，其中
所述金属膜由具有在所述热处理中与所述层间膜反应以形成具有绝缘性的氧化物的性质的金属构成。
5.根据权利要求2所述的半导体装置，其中
所述金属膜包含锰、钒、铝、镁和锆中的至少一种或多种的元素。
6.根据权利要求2所述的半导体装置，其中
所述金属膜形成为具有0.1nm～10nm的厚度。
7.根据权利要求2所述的半导体装置，其中
在所述金属膜已经形成在所述层间膜和所述连接焊盘的整个表面上的状态下，通过使用含氢的液体或气体对所述金属膜进行预处理。
8.根据权利要求2所述的半导体装置，其中
当接合所述第一半导体基板和所述第二半导体基板时，在所述金属膜已经形成在所述接合面中的至少一个的整个表面上的状态下进行接合。
9.一种半导体装置的制造方法，其中
所述半导体装置包括：
连接焊盘，所述连接焊盘形成在分别设置于第一半导体基板的配线层中和第二半导体基板的配线层中的层间膜内，以在所述第一半导体基板和所述第二半导体基板之间形成电连接；和
金属氧化膜，所述金属氧化膜形成在所述第一半导体基板的层间膜和所述第二半导体基板的层间膜之间、在所述第一半导体基板侧形成的所述连接焊盘和在所述第二半导体基板侧的所述层间膜之间以及在所述第二半导体基板侧形成的所述连接焊盘和在所述第一半导体基板侧的所述层间膜之间，
所述方法包括以下步骤：
在包括在所述第一半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面以及包括在所述第二半导体基板侧的所述层间膜和形成在所述层间膜中的所述连接焊盘的接合面中的至少一个接合面上形成金属膜；和
通过在其中以所述金属膜介于所述第一半导体基板和所述第二半导体基板之间的方式使所述第一半导体基板和所述第二半导体基板彼此紧密接触的状态下进行热处理，自发形成由所述金属膜和所述层间膜之间的反应产生的所述金属氧化膜。
10.一种固态成像元件，包括：
连接焊盘，所述连接焊盘形成在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内，以在所述传感器基板和所述信号处理基板之间形成电连接，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板构造成对所述传感器基板进行信号处理；和
金属氧化膜，所述金属氧化膜形成在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的所述连接焊盘和在所述信号处理基板侧的所述层间膜之间以及在所述信号处理基板侧形成的所述连接焊盘和在所述传感器基板侧的所述层间膜之间。
11.一种电子设备，包括：
固态成像元件，所述固态成像元件包括：
连接焊盘，所述连接焊盘形成在分别设置于传感器基板的配线层中和信号处理基板的配线层中的层间膜内，以在所述传感器基板和所述信号处理基板之间形成电连接，所述传感器基板上形成有具有像素的传感器表面，所述信号处理基板构造成对所述传感器基板进行信号处理；和
金属氧化膜，所述金属氧化膜形成在所述传感器基板的层间膜和所述信号处理基板的层间膜之间、在所述传感器基板侧形成的所述连接焊盘和在所述信号处理基板侧的所述层间膜之间以及在所述信号处理基板侧形成的所述连接焊盘和在所述传感器基板侧的所述层间膜之间。
CN201680023993.1A 2015-05-22 2016-05-06 半导体装置、制造方法、固态成像元件和电子设备 Active CN107534014B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202111127348.3A CN113990839B (zh) 2015-05-22 2016-05-06 半导体装置和光检测装置
CN202111127293.6A CN113990838B (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器
CN202210389474.4A CN114899201A (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器
CN202210388793.3A CN114899200A (zh) 2015-05-22 2016-05-06 半导体装置、制造方法和固态成像元件

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2015-104705 2015-05-22
JP2015104705A JP2016219660A (ja) 2015-05-22 2015-05-22 半導体装置、製造方法、固体撮像素子、および電子機器
PCT/JP2016/063630 WO2016190059A1 (ja) 2015-05-22 2016-05-06 半導体装置、製造方法、固体撮像素子、および電子機器

Related Child Applications (4)

Application Number Title Priority Date Filing Date
CN202210389474.4A Division CN114899201A (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器
CN202111127293.6A Division CN113990838B (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器
CN202210388793.3A Division CN114899200A (zh) 2015-05-22 2016-05-06 半导体装置、制造方法和固态成像元件
CN202111127348.3A Division CN113990839B (zh) 2015-05-22 2016-05-06 半导体装置和光检测装置

Publications (2)

Publication Number Publication Date
CN107534014A true CN107534014A (zh) 2018-01-02
CN107534014B CN107534014B (zh) 2022-04-12

Family

ID=57392730

Family Applications (5)

Application Number Title Priority Date Filing Date
CN202111127293.6A Active CN113990838B (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器
CN202111127348.3A Active CN113990839B (zh) 2015-05-22 2016-05-06 半导体装置和光检测装置
CN201680023993.1A Active CN107534014B (zh) 2015-05-22 2016-05-06 半导体装置、制造方法、固态成像元件和电子设备
CN202210388793.3A Pending CN114899200A (zh) 2015-05-22 2016-05-06 半导体装置、制造方法和固态成像元件
CN202210389474.4A Pending CN114899201A (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器

Family Applications Before (2)

Application Number Title Priority Date Filing Date
CN202111127293.6A Active CN113990838B (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器
CN202111127348.3A Active CN113990839B (zh) 2015-05-22 2016-05-06 半导体装置和光检测装置

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN202210388793.3A Pending CN114899200A (zh) 2015-05-22 2016-05-06 半导体装置、制造方法和固态成像元件
CN202210389474.4A Pending CN114899201A (zh) 2015-05-22 2016-05-06 半导体装置、光检测装置和车辆传感器

Country Status (4)

Country Link
US (5) US10332927B2 (zh)
JP (1) JP2016219660A (zh)
CN (5) CN113990838B (zh)
WO (1) WO2016190059A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110880452A (zh) * 2018-09-06 2020-03-13 株式会社东芝 半导体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016219660A (ja) 2015-05-22 2016-12-22 ソニー株式会社 半導体装置、製造方法、固体撮像素子、および電子機器
JP2019054153A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置の製造方法
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10685935B2 (en) * 2017-11-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses
DE102018124337A1 (de) * 2017-11-21 2019-05-23 Taiwan Semiconductor Manufacturing Co. Ltd. Ankerstrukturen und verfahren zur gleichmässigen waferplanarisierung und -bondung
US11152417B2 (en) 2017-11-21 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Anchor structures and methods for uniform wafer planarization and bonding
TW202118028A (zh) * 2019-06-26 2021-05-01 日商索尼半導體解決方案公司 攝像裝置

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5990537A (en) * 1991-09-04 1999-11-23 Fujitsu Limited Semiconductor device with fuse
JP2001015792A (ja) * 1999-04-28 2001-01-19 Denso Corp 光センサ
CN1839473A (zh) * 2003-08-28 2006-09-27 株式会社藤仓 半导体封装体及其制造方法
CN1973367A (zh) * 2004-06-30 2007-05-30 松下电器产业株式会社 半导体装置及其制造方法
CN101794800A (zh) * 2009-01-15 2010-08-04 索尼公司 固态成像装置及电子设备
WO2011050073A1 (en) * 2009-10-23 2011-04-28 President And Fellows Of Harvard College Self-aligned barrier and capping layers for interconnects
CN102082157A (zh) * 2009-11-30 2011-06-01 索尼公司 结合基板及制造方法、固体摄像装置及制造方法、照相机
US20130009321A1 (en) * 2011-07-05 2013-01-10 Sony Corporation Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US20130105924A1 (en) * 2010-06-30 2013-05-02 Canon Kabushiki Kaisha Solid-state imaging apparatus and manufacturing method of solid-state imaging apparatus
CN103247603A (zh) * 2012-02-14 2013-08-14 索尼公司 半导体装置、制造半导体装置的方法以及电子设备
CN103367375A (zh) * 2012-04-04 2013-10-23 索尼公司 固体摄像装置及其制造方法以及电子设备
US20140045329A1 (en) * 2012-08-08 2014-02-13 Tokyo Electron Limited Method for forming cu wiring
TW201517233A (zh) * 2013-10-18 2015-05-01 Toshiba Kk 半導體裝置及半導體裝置的製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482132B2 (en) * 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
JP6031765B2 (ja) 2011-07-05 2016-11-24 ソニー株式会社 半導体装置、電子機器、及び、半導体装置の製造方法
CN103367374B (zh) * 2012-04-02 2017-06-09 索尼公司 固体摄像装置及其制造方法、半导体器件的制造装置和方法、电子设备
NL2012891B1 (en) * 2013-06-05 2016-06-21 Apple Inc Biometric sensor chip having distributed sensor and control circuitry.
TWI676279B (zh) * 2013-10-04 2019-11-01 新力股份有限公司 半導體裝置及固體攝像元件
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
JP2016219660A (ja) 2015-05-22 2016-12-22 ソニー株式会社 半導体装置、製造方法、固体撮像素子、および電子機器
US9691733B1 (en) * 2016-07-28 2017-06-27 United Microelectronics Corp. Bonded semiconductor structure and method for forming the same
US10685935B2 (en) * 2017-11-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses
JP2022528073A (ja) * 2020-02-17 2022-06-08 長江存儲科技有限責任公司 ハイブリッドウェハ接合方法およびその構造

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5990537A (en) * 1991-09-04 1999-11-23 Fujitsu Limited Semiconductor device with fuse
JP2001015792A (ja) * 1999-04-28 2001-01-19 Denso Corp 光センサ
CN1839473A (zh) * 2003-08-28 2006-09-27 株式会社藤仓 半导体封装体及其制造方法
CN1973367A (zh) * 2004-06-30 2007-05-30 松下电器产业株式会社 半导体装置及其制造方法
CN101794800A (zh) * 2009-01-15 2010-08-04 索尼公司 固态成像装置及电子设备
WO2011050073A1 (en) * 2009-10-23 2011-04-28 President And Fellows Of Harvard College Self-aligned barrier and capping layers for interconnects
CN102082157A (zh) * 2009-11-30 2011-06-01 索尼公司 结合基板及制造方法、固体摄像装置及制造方法、照相机
US20130105924A1 (en) * 2010-06-30 2013-05-02 Canon Kabushiki Kaisha Solid-state imaging apparatus and manufacturing method of solid-state imaging apparatus
US20130009321A1 (en) * 2011-07-05 2013-01-10 Sony Corporation Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
CN103247603A (zh) * 2012-02-14 2013-08-14 索尼公司 半导体装置、制造半导体装置的方法以及电子设备
CN103367375A (zh) * 2012-04-04 2013-10-23 索尼公司 固体摄像装置及其制造方法以及电子设备
US20140045329A1 (en) * 2012-08-08 2014-02-13 Tokyo Electron Limited Method for forming cu wiring
TW201517233A (zh) * 2013-10-18 2015-05-01 Toshiba Kk 半導體裝置及半導體裝置的製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110880452A (zh) * 2018-09-06 2020-03-13 株式会社东芝 半导体装置

Also Published As

Publication number Publication date
US10615210B2 (en) 2020-04-07
US10332927B2 (en) 2019-06-25
US10950637B2 (en) 2021-03-16
US20190206919A1 (en) 2019-07-04
US11776923B2 (en) 2023-10-03
CN113990839A (zh) 2022-01-28
CN114899200A (zh) 2022-08-12
US20230402411A1 (en) 2023-12-14
US20200227462A1 (en) 2020-07-16
CN113990839B (zh) 2023-01-17
CN113990838B (zh) 2023-07-18
CN114899201A (zh) 2022-08-12
WO2016190059A1 (ja) 2016-12-01
US20180138224A1 (en) 2018-05-17
US20210183661A1 (en) 2021-06-17
CN113990838A (zh) 2022-01-28
JP2016219660A (ja) 2016-12-22
CN107534014B (zh) 2022-04-12

Similar Documents

Publication Publication Date Title
CN107534014A (zh) 半导体装置、制造方法、固态成像元件和电子设备
JP6693068B2 (ja) 固体撮像装置および製造方法、並びに電子機器
US12046621B2 (en) Solid-state imaging device and electronic apparatus to enhance image quality
US11924557B2 (en) Pinhole camera, electronic apparatus and manufacturing method
US11923395B2 (en) Semiconductor device, solid-state image pickup element, image pickup device, and electronic apparatus
US12119366B2 (en) Solid state imaging device, solid state imaging device manufacturing method, and electronic apparatus
US20230015360A1 (en) Imaging device, manufacturing method, and electronic device
WO2022054501A1 (ja) 固体撮像装置及びその製造方法、並びに電子機器
US11482557B2 (en) Solid-state image-capturing device, semiconductor apparatus, electronic apparatus, and manufacturing method
KR102720747B1 (ko) 촬상 장치, 제조 방법 및 전자 기기
WO2022107621A1 (ja) 固体撮像素子、製造方法、および電子機器

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant