JP2013168419A - 半導体装置、半導体装置の製造方法、及び、電子機器 - Google Patents
半導体装置、半導体装置の製造方法、及び、電子機器 Download PDFInfo
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- JP2013168419A JP2013168419A JP2012029429A JP2012029429A JP2013168419A JP 2013168419 A JP2013168419 A JP 2013168419A JP 2012029429 A JP2012029429 A JP 2012029429A JP 2012029429 A JP2012029429 A JP 2012029429A JP 2013168419 A JP2013168419 A JP 2013168419A
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Abstract
【解決手段】半導体基体31と、半導体基体31上に形成された層間絶縁層32と、層間絶縁層32の表面に形成された接合電極33と、層間絶縁層32と接合電極33とからなる接合面の全面を被覆する金属膜35とを備える半導体装置30を構成する。
【選択図】図3
Description
3次元LSIにおける基盤技術として、接合技術がある。接合技術の中にも様々な方式が有り、チップ同士を接合する技術やウェハ同士を接合する技術が検討されている。デバイスウェハ同士を貼りあわせて3次元LSIを作製する際、ウェハ表面に形成されたデバイス面のCu電極同士を直接接合する方式がある。この方式において、Cu電極と層間絶縁膜(ILD)を同一平面に平坦化し、Cu/ILDのハイブリッド接合を行う方法がある(特許文献1、特許文献2参照)。このような接合プロセスでは、接合強度の向上や接合不良を抑制するために、接合面を極めて平坦な面とすることが必要となる。
また、本発明の電子機器は、上述の半導体装置と、半導体装置の出力信号を処理する信号処理回路とを備える。
接合電極上の金属膜により、接合電極の電気的接続を確保する。また、金属膜の反応生成物の絶縁膜により、層間絶縁層と接合電極との接触を防ぎ、接合不良及びリークパス等の信頼性の低下を抑制する。
さらに、この半導体装置が適用された電子機器の信頼性を向上させることができる。
なお、説明は以下の順序で行う。
1.半導体装置の概要
2.半導体装置の実施形態
3.実施形態の半導体装置の製造方法
4.半導体装置の変形例
5.電子機器の実施形態
[構成]
半導体装置の接合電極の構成の概要について説明する。
図1に、従来の一般的な半導体装置の接合部の構成の断面図を示す。この接合部は、複数枚の半導体基体が、その一方の面に形成された配線層同士を対向させ、配線層表面に形成された接合電極同士を接合させた構成である。
第1接合部10は、図示しない半導体基体上に形成されている。そして、第1接合部10は、第1層間絶縁層11と、第1接合電極12とを備える。第1接合電極12は、第1層間絶縁層11内に形成され、第1接合電極12の表面が第1層間絶縁層11の表面から接合面に露出している。第1接合電極12と第1層間絶縁層11との接触面には、電極材料の絶縁層への拡散を防ぐためのバリアメタル層13が設けられている。
上述のように、第1接合電極12を形成した面と、第2接合電極22を形成した面とを対向させた状態で、第1接合電極12と第2接合電極22とが接合して、第1接合部10と第2接合部20とが貼り合わされている。ここで、第1接合電極12と第2接合電極22とは、接合面と電極形成面が完全に一致せず、ずれた状態で接合されている。
また、第1接合電極12と第2接合電極22とは、接合信頼性を確保するため、一方の電極の面積を大きく形成することで、接合位置がずれた場合にも、接合面積に差が発生しないように設計される。
従って、接合面には、接合電極同士が接触する部分と、接合電極と層間絶縁層とが接触する部分とが存在する。つまり、この半導体装置の接合面では、第1接合電極12と第2層間絶縁層21とが接触する接触部14が存在する。さらに、第2接合電極22と第1層間絶縁層11とが接触する接触部24が存在する。
また、図2に示すように、接合電極を構成する金属、例えばCuが、接触する層間絶縁層内に拡散することにより、リークパス15が形成される可能性がある。これは、半導体装置の絶縁性の不良、バリア性の問題を発生させる。
さらに、構造的に、上下の接合電極の接合面積は同一にはならないため、必然的に接合電極と層間絶縁層との接触面が存在することになる。
従って、接合電極により接合された半導体装置では、位置ずれが発生した状態であっても、接合性の悪化、バリア性の悪化を防ぐ構成が求められている。
[半導体装置の構成]
以下、接合電極を備える半導体装置の実施形態について説明する。
図3に、本実施形態の接合電極を備える半導体装置の概略構成を示す。図3は、本実施形態の半導体装置の接合部付近の断面図である。なお、上述の図3に示す半導体装置30では、本実施形態の説明に不要な配線層等の記載を省略している。
半導体基体31には、図示しない電子回路や配線等の各種素子が形成されている。
接合電極33は、従来公知の半導体装置の電極に適用されている材料、例えばCuから形成される。
バリアメタル層34は、半導体装置にバリアメタル層として一般的に適用される材料、例えば、Ta、Ti、Ru、TaN、TiN等から形成される。
また、金属膜35は、加熱処理より半導体基体の接合が可能であり、導電性が高い金属が用いられる。さらに、金属膜35は、加熱処理により層間絶縁層32と接触する部分において、層間絶縁層32と反応する金属を用いる。そして、この反応により、層間絶縁層32と接触した部分に生成する金属膜35の反応生成物が絶縁体となる金属を用いる。このような金属として、金属膜35には、例えばTi、Ta等を用いる。
また、金属膜35は、層間絶縁層32との反応生成物が充分な バリア性を有する厚さ、例えば、5分子層以上の厚さに形成する。
次に、図4に上述の半導体装置30同士を貼り合わせた構成を示す。図4では、それぞれ同じ構成の半導体装置30A,30Bを示している。半導体装置30A,30Bは、上述の図3に示す半導体装置30と同じ構成であり、それぞれ符号にA,Bを付して示している。また、半導体装置30A,30Bは、上述の図3に示す半導体装置30と同じ構成であるため各部の説明は省略する。
また、接合電極33A,33B上に形成された金属膜35A,35Bは、加熱処理後も変化せず、成膜された状態を保つ。
次に、実施形態の半導体装置の製造方法の一例を説明する。なお、以下の製造方法の説明では、上述の図3に示す半導体装置30の接合部付近の製造方法のみを示し、その他、半導体基体31上に形成される各種素子や配線等の構成の製造方法は説明を省略する。半導体基体、配線層、他の各種トランジスタ、各種素子の作製方法については説明を省略する。これらは従来公知の方法により作製することができる。また、上述の図3及び図4に示す本実施形態の半導体装置の構成と同様の構成には、同じ符号を付して各構成の詳細な説明は省略する。
そして、図5Bに示すように、層間絶縁層32上にレジスト層41を形成する。レジスト層41は、半導体装置の接合電極の形成位置を開口するパターンに形成する。
そして、図6Fに示すように、接合電極33及び層間絶縁層32の表面を覆って、全面に金属膜35を形成する。金属膜35は、ALD(atomic layer deposition)法やCVD(Chemical Vapor Deposition)法等を用いて、Ti、Ta等の材料を、10〜100nmの厚さに形成する。
金属膜35の形成後、必要に応じてCMP法等を用いて表面の平坦化処理を行う。
以上の工程により半導体装置30を形成することができる。
そして、上述の方法により形成した二枚の半導体装置30の接合面に、例えば蟻酸を用いたWet処理、或いは、Ar、NH3、H2等のプラズマを用いたDry処理を施す。この処理により、接合電極33の表面の酸化膜を除去し、清浄な金属面を露出させる。
そして、図7Gに示すように、二枚の半導体基体の表面同士を対向させる。そして、両者を接触させる。この状態では、金属膜35は成膜時の材料から変化なく、半導体装置30の全面を覆っている。
この加熱処理により、層間絶縁層32と接触する部分の金属膜35とが反応する。これにより、半導体装置30の接合面に、反応生成物からなる絶縁膜36が形成される。このように、半導体装置30の接合と同時に、金属膜35と層間絶縁層32とを反応させ、絶縁膜36を形成することが可能である。
以上の工程により、図7Hに示す本実施形態の半導体装置を製造することができる。
次に、上述の実施の形態の半導体装置の変形例について説明する。
図8に変形例の半導体装置の構成を示す。図8に示す半導体装置は、接合面に形成される金属膜の構成を除き、上述の図4に示す半導体装置と同様の構成である。このため、図4に示す半導体装置と同様の構成には、同じ符号を符して説明を省略する。
また、層間絶縁層32A,32Bと接する部分の金属膜35Aが、絶縁膜36Aとなるため、層間絶縁層32A,32B上が絶縁膜36Aにより被覆される。この結果、接合性の低い接合電極33A,33Bと層間絶縁層32A,32Bとの接触が起こらず、接合界面のボイドの発生による半導体装置の接合の信頼性の低下を抑制することができる。
さらに、層間絶縁層32A,32B上を絶縁膜36Aが覆うことにより、接合電極33A,33Bを構成する金属、例えばCuの層間絶縁層32A,32B内への拡散を防ぐことができる。このため、リークパスの形成が抑制され、半導体装置の信頼性が向上する。
上述の実施形態の半導体装置は、2つの半導体部材を貼り合わせて配線接合を行う任意の電子機器、例えば、固体撮像装置、半導体メモリ、半導体ロジックデバイス(IC等)に適用可能である。
以下、上述の実施形態における電極接合の構成を固体撮像装置に適用した例を説明する。
図9に、本実施形態に係る固体撮像装置の要部の概略断面図を示す。なお、図9では、説明を簡略化するため、電極接合部、ビア及び層間絶縁層との間に形成されるバリアメタル層の図示は省略する。
上述の固体撮像装置は、例えば、デジタルカメラやビデオカメラ等のカメラシステム、撮像機能を有する携帯電話、又は、撮像機能を備えた他の機器などの電子機器に適用することができる。以下、電子機器の一構成例として、カメラを例に挙げ説明する。
この例のカメラ300は、固体撮像装置301と、固体撮像装置301の受光センサ部に入射光を導く光学系302と、固体撮像装置301及び光学系302間に設けられたシャッタ装置303と、固体撮像装置301を駆動する駆動回路304とを備える。さらに、カメラ300は、固体撮像装置301の出力信号を処理する信号処理回路305を備える。
(1)半導体基体と、前記半導体基体上に形成された層間絶縁層と、前記層間絶縁層の表面に形成された接合電極と、前記層間絶縁層と前記接合電極とからなる接合面の全面を被覆する金属膜と、を備える半導体装置。
(2)前記金属膜が、前記層間絶縁層との反応により絶縁体となる金属材料から構成される(1)に記載の半導体装置。
(3)前記金属膜が、Ta、及び、Tiから選ばれる少なくとも1種を含んで構成されている(1)又は(2)に記載の半導体装置。
(4)金属膜を介して接合電極の形成面同士が貼り合わされた第1の半導体基体と第2の半導体基体とからなる半導体装置であって、第1の半導体基体と、前記第1の半導体基体上に形成された第1の層間絶縁層と、前記第1の層間絶縁層の表面に形成された第1の接合電極と、前記第1の半導体基体と接合された第2の半導体基体と、前記第2の半導体基体上に形成された第2の層間絶縁層と、前記第2の層間絶縁層の表面に形成された第2の接合電極と、前記第1の半導体基体と前記第2の半導体基体との接合面において、前記第1の接合電極と前記第2の接合電極との間に形成された金属膜と、前記第1の半導体基体と前記第2の半導体基体との接合面において、前記第1の層間絶縁層又は前記第2の層間絶縁層と接触する部分に形成された、前記金属膜と前記第1の層間絶縁層又は前記第2の層間絶縁層との反応生成物からなる絶縁膜と、を備える半導体装置。
(5)前記第1の半導体基体の前記第1の接合電極上に形成された第1の金属膜と、前記第1の層間絶縁層上に形成された前記第1の金属膜と前記第1の層間絶縁層又は前記第2の層間絶縁層との反応生成物からなる第1の絶縁膜と、前記第2の半導体基体の前記第2の接合電極上に形成された第2の金属膜と、前記第2の層間絶縁層上に形成された前記第2の金属膜と前記第1の層間絶縁層又は前記第2の層間絶縁層との反応生成物からなる第2の絶縁膜とを備える(4)に記載の半導体装置。
(6)半導体基体上に層間絶縁層を形成する工程と、前記層間絶縁層の表面に接合電極を形成する工程と、前記層間絶縁層及び前記接合電極の表面の全面に金属膜を形成する工程と、を有する半導体装置の製造方法。
(7)(1)から(5)のいずれかに記載の半導体装置と、前記半導体装置の出力信号を処理する信号処理回路と、を備える電子機器。
Claims (7)
- 半導体基体と、
前記半導体基体上に形成された層間絶縁層と、
前記層間絶縁層の表面に形成された接合電極と、
前記層間絶縁層と前記接合電極とからなる接合面の全面を被覆する金属膜と、を備える
半導体装置。 - 前記金属膜が、前記層間絶縁層との反応により絶縁体となる金属材料から構成される請求項1に記載の半導体装置。
- 前記金属膜が、Ta、及び、Tiから選ばれる少なくとも1種を含んで構成されている請求項1に記載の半導体装置。
- 金属膜を介して接合電極の形成面同士が貼り合わされた第1の半導体基体と第2の半導体基体とからなる半導体装置であって、
前記第1の半導体基体と、
前記第1の半導体基体上に形成された第1の層間絶縁層と、
前記第1の層間絶縁層の表面に形成された第1の接合電極と、
前記第1の半導体基体と接合された第2の半導体基体と、
前記第2の半導体基体上に形成された第2の層間絶縁層と、
前記第2の層間絶縁層の表面に形成された第2の接合電極と、
前記第1の半導体基体と前記第2の半導体基体との接合面において、前記第1の接合電極と前記第2の接合電極との間に形成された金属膜と、
前記第1の半導体基体と前記第2の半導体基体との接合面において、前記第1の層間絶縁層又は前記第2の層間絶縁層と接触する部分に形成された、前記金属膜と前記第1の層間絶縁層又は前記第2の層間絶縁層との反応生成物からなる絶縁膜と、を備える
半導体装置。 - 前記第1の半導体基体の前記第1の接合電極上に形成された第1の金属膜と、前記第1の層間絶縁層上に形成された前記第1の金属膜と前記第1の層間絶縁層又は前記第2の層間絶縁層との反応生成物からなる第1の絶縁膜と、前記第2の半導体基体の前記第2の接合電極上に形成された第2の金属膜と、前記第2の層間絶縁層上に形成された前記第2の金属膜と前記第1の層間絶縁層又は前記第2の層間絶縁層との反応生成物からなる第2の絶縁膜とを備える請求項4に記載の半導体装置。
- 半導体基体上に層間絶縁層を形成する工程と、
前記層間絶縁層の表面に接合電極を形成する工程と、
前記層間絶縁層及び前記接合電極の表面の全面に金属膜を形成する工程と、を有する
半導体装置の製造方法。 - 半導体基体と、前記半導体基体上に形成された層間絶縁層と、前記層間絶縁層の表面に形成された接合電極と、前記層間絶縁層と前記接合電極とからなる接合面の全面を被覆する金属膜とを備える半導体装置と、
前記半導体装置の出力信号を処理する信号処理回路と、を備える
電子機器。
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US9716076B2 (en) | 2017-07-25 |
US20130207271A1 (en) | 2013-08-15 |
US20170354199A1 (en) | 2017-12-14 |
CN103247603A (zh) | 2013-08-14 |
CN103247603B (zh) | 2017-08-11 |
US20160141267A1 (en) | 2016-05-19 |
US10485293B2 (en) | 2019-11-26 |
US9147650B2 (en) | 2015-09-29 |
JP5994274B2 (ja) | 2016-09-21 |
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