CN103187304A - 制造半导体器件和晶体管的方法 - Google Patents
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
Abstract
本发明公开了半导体器件和晶体管的制造方法。在一个实施例中,一种制造半导体器件的方法包括提供包括多个鳍的工件,以及在多个鳍的顶面上方形成半导体材料。在半导体材料上方形成蚀刻停止层,以及在蚀刻停止层上方设置绝缘材料。从多个鳍的上方去除该绝缘材料和蚀刻停止层的部分。对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除部分蚀刻停止层时不会去除位于多个鳍上方的半导体材料的最宽部分之间的蚀刻停止层。
Description
技术领域
本发明涉及半导体领域,更具体地,涉及制造半导体器件和晶体管的方法。
背景技术
半导体器件被应用在许多电子应用中,诸如,个人电脑、手机、数码相机、以及其他电子设备。通常通过在半导体衬底上方顺次地沉积绝缘或介电层、导电层、以及半导体层的材料,并且使用光刻来图案化各种材料从而在其上形成电路部件和元件来制造半导体器件。
近些年来半导体技术开发出了多栅极场效应晶体管(MuGFET),该多栅极场效应晶体管通常是将一个以上栅极结合到一个器件中的金属氧化物半导体FET(MOSFET)。可以通过一个栅电极来控制多个栅极(在此,多个栅极表面在电学上用作一个栅极)或通过不相关的栅电极来控制多个栅极。一种被称为FinFET的MuGFET是带有从集成电路的硅表面中纵向地突起的鳍状半导体沟槽的晶体管。
在一些半导体设计中,将多个FinFET使用在一个晶体管设计中,同时,半导体材料的鳍被设置成平行的。有时,在鳍的上面形成有半导体材料外延生长。根据设计,该外延生长可以是混合(merged)的或非混合的。
发明内容
为解决上述问题,本发明提供了一种制造半导体器件的方法,包括:提供包括多个鳍的工件;在多个鳍的顶面上方形成半导体材料;在半导体材料上方形成蚀刻停止层;在蚀刻停止层上方设置绝缘材料;以及从多个鳍的上方去除蚀刻停止层的一部分和绝缘材料,其中,对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除蚀刻停止层的一部分时不会去除位于多个鳍上方的半导体材料的最宽部分之间的蚀刻停止层。
其中,对形成半导体材料以及形成蚀刻停止层两者进行控制。
其中,通过控制位于多个鳍上方的半导体材料的最宽部分之间的间隔来控制半导体材料的形成。
其中,通过控制蚀刻停止层的厚度来控制蚀刻停止层的形成。
其中,形成蚀刻停止层包括形成对绝缘材料具有蚀刻选择性的材料。
其中,形成蚀刻停止层包括形成SiN、SiON、SiC、或SiOC。
其中,去除蚀刻停止层的一部分包括在多个鳍上方的半导体材料的最宽部分上方留下至少大约15nm的蚀刻停止层。
其中,多个鳍包括鳍式场效应晶体管(FinFET)的鳍。
此外,本发明提供了一种制造半导体器件的方法,包括:提供工件;在工件上方形成多个鳍;在多个鳍中的每一个的顶面上方外延生长半导体材料;在半导体材料上方形成蚀刻停止层;在蚀刻停止层上方放置绝缘材料;从多个鳍的上方去除蚀刻停止层的一部分和绝缘材料;以及在多个鳍上方形成导电材料,其中,对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除蚀刻停止层的一部分时不会去除位于多个鳍上方的半导体材料的最宽部分之间的蚀刻停止层。
其中,外延生长半导体材料包括在多个鳍的顶面上方形成非混合的半导体材料。
其中,去除蚀刻停止层的一部分包括露出位于多个鳍中的每一个的顶面上方的半导体材料的顶部。
其中,形成导电材料包括形成接触件。
其中,形成接触件包括形成插槽式接触件或插塞式接触件。
其中,制造半导体器件包括形成晶体管。
此外,还提供了一种制造晶体管的方法,包括:提供工件;在工件上方形成多个鳍;在多个鳍中的每一个的顶面上方外延生长非混合的半导体材料,半导体材料的接近中心区域比半导体材料的接近顶面区域更宽;在半导体材料上方形成蚀刻停止层,其中,蚀刻停止层的一部分形成在半导体材料的较宽的中心区域下面;在蚀刻停止层上方设置绝缘材料;蚀刻掉位于多个鳍上方的蚀刻停止层的顶部和绝缘材料;以及在多个鳍上方形成导电材料,从而形成接触件,其中,对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除蚀刻停止层的顶部时不会去除位于多个鳍上方的半导体材料的较宽的中心区域之间的蚀刻停止层。
其中,形成蚀刻停止层包括在位于多个鳍上方的半导体材料之间的蚀刻停止层中形成孔,以及其中,蚀刻掉蚀刻停止层的顶部时不到达蚀刻停止层中的孔。
其中,蚀刻停止层的厚度为位于多个鳍上方的半导体材料之间的最小间隔的至少一半。
其中,形成蚀刻停止层包括形成第一蚀刻停止层,以及其中,设置绝缘材料包括:在第一蚀刻停止层上方形成第一层间电介质(ILD),在第一ILD上方形成第二蚀刻停止层,以及在第二蚀刻停止层上方形成第二ILD。
其中,设置绝缘材料包括形成第一绝缘材料,进一步包括在工件上方形成多个鳍之后,在多个鳍之间形成第二绝缘材料。
其中,形成多个鳍包括形成晶体管的沟道、漏极区域、或源极区域。
附图说明
为了更全面地理解实施例及其优势,现将结合附图所进行的描述作为参考,其中:
图1至图8示出了根据本公开的实施例的制造半导体器件的方法的截面图;
图9是图8所示的半导体器件的俯视图;
图10是图8所示的半导体器件的部分的更详细视图;
图11是制造半导体器件的流程图。
除非另行指出,不同视图中的相应的标号大体上涉及的是相应的部分。绘制视图用于清楚地说明实施例的各个方面,但不必按比例进行绘制。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
本公开的实施例涉及的是制造半导体器件和晶体管的方法。在此将阐述制造FinFET晶体管的新颖的方法。
图1至图8示出了根据本公开的实施例制造半导体器件100的方法的截面图。首先参考图1,提供了工件102。工件102可以包括半导体衬底并且可以被例如绝缘层所覆盖,该半导体衬底包括硅或其他半导体材料。工件102还可以包括其他有源部件或电路,未示出。例如,工件102可以包括位于单晶体硅上方的氧化硅。工件102可以包括其他传导层或其他半导体元件,例如,晶体管、二极管等。可以使用化合物半导体,例如,GaAs、InP、Si/Ge、或SiC来代替硅。工件102可以包括,例如,体衬底或绝缘体上半导体(SOI)衬底。
如图2所示,多个鳍104形成在工件102上方。根据工件102的类型,可以使用多种方法来制造鳍104。在一些实施例中,工件102所包括的衬底包括了体衬底,诸如,体Si、体SiP、体SiGe、体SiC、体Ge,或其组合。鳍104形成在包括了体衬底的工件102的顶部中。在其他实施例中,鳍104可以由包括了SOI衬底的工件102形成。该SOI衬底包括设置在绝缘材料两侧上的半导体材料(诸如,硅或锗)的两个层。在该实施例中,一个半导体材料层被图案化以形成鳍104。例如,工件112可以包括带有体衬底的SOI-Si工件、SOI-SiGe工件、或其组合。
视图中示出了四个鳍104,可选地在一个半导体器件100中可以包括两个或更多个鳍104。可以在一个晶体管中形成,例如,7个、14个、20个或其他数量的鳍104。鳍104被形成为彼此平行地向图2至图8所示的视图中的页面内外延伸。根据一些实施例,鳍104包括晶体管的一些部分。根据设计,鳍104可以包括,例如,晶体管的沟槽、源极区域,或漏极区域。在一些实施例中,鳍104可以包括FinFET的鳍。
例如,使用光刻和蚀刻工艺、直接蚀刻工艺、或显微机械加工来形成鳍104。可以通过包括了尺寸d1的间距将鳍104彼此间隔开,该尺寸d1可以包括大约10至1000nm。鳍104所包括的宽度包括尺寸d2,尺寸d2可以包括大约5至100nm。鳍104所包括的高度包括尺寸d3,尺寸d3可以包括大约20至1000nm。鳍104可以向纸张内外纵向地延伸若干μm。可选地,尺寸d1、d2、d3、以及鳍104的长度可以包括其他值。
如图3所示,绝缘材料106设置在鳍104之间,该绝缘材料可以包括场氧化物、浅沟道隔离(STI)或其他绝缘材料。绝缘材料106可以包括氧化物,诸如,二氧化硅或其他种类的介电材料。由于被用于形成绝缘材料106的工艺,绝缘材料106可以包括接近鳍104的凹槽区域108。该绝缘材料106可以沉积在其104的顶面上方,并且可以使用例如化学机械抛光(CMP)和/或蚀刻工艺来去除过量的绝缘材料106。
如图4所示,半导体材料110形成在鳍104的顶面上方。在一些实施例中,例如,通过外延生长来形成半导体材料110。可以引入前体(例如,引入到工件102所处的室中),并且例如,鳍104的顶面在外延生长工艺过程中可以作为半导体材料110结晶取向的晶种。半导体材料110可以包括例如Si、SiGe、SiC、SiP、SiPC、或掺杂或未掺杂其他元素的其他半导体材料。
如图4所示,半导体材料110的邻近中间区域比半导体材料110的邻近顶面或底面区域更宽。在相邻的鳍104上方的较宽的中心区域112处,可以通过包括了尺寸d4的间距将半导体材料110与相邻的半导体材料110隔开。较宽的区域112可以不精确地设置在外延生长的半导体材料110的顶面和底面之间。如图4所示,根据半导体材料110的晶体生长和结晶结构,可以将较宽的区域112定位成更接近半导体材料110的底面,或可以将较宽的区域112定位成更接近半导体材料110的顶面。在一些实施例中,尺寸d4可以包括大约5至1000nm,但可选地,尺寸d4可以包括其他值。根据本公开的实施例,尺寸d4大于0;例如,位于鳍104的顶面上方的半导体材料110是非混合的。
如图5所示,接触蚀刻停止层(CESL)114形成在半导体材料110上方和绝缘材料106上方。在此,CESL 114也被称为蚀刻停止层或第一蚀刻停止层。CESL 114可以包括例如SiN、SiON、SiC、或SiOC,但可选地,CESL 114可以包括其他材料。CESL 114可以包括对随后沉积的绝缘材料(诸如,图6所示的层118)具有蚀刻选择性的材料。可以使用化学汽相沉积(CVD)或其他类型的沉积工艺沉积CESL 114。在一些实施例中,例如,使用易流动的CVD来形成CESL 114。在一些实施例中,CESL 114的厚度包括尺寸d5,该尺寸可以包括大约15至50nm,但可选地,CESL 114可以包括其他尺寸。
部分CESL 114形成在鳍104上面的半导体材料110之间。CESL 114可以是共形的并且具有了绝缘材料116以及外延生长的半导体材料110的地势形状。CESL 114形成在半导体材料110的最宽部分112旁。在一些实施例中,孔116可以形成在CESL 114中。如所示,任选的孔116可以形成在位于半导体材料110的两个相邻的较宽的部分112旁边的结构中的纵向高度处。
如图6所示,绝缘材料118/120/122形成在CESL 114上方。绝缘材料118/120/122包括实施例中所示的三层;可选地,绝缘材料118/120/122可以包括单层或两层或多层。实施例中所示的绝缘材料118/120/122包括形成在第一蚀刻停止层114上方的第一层间电介质(ILD)118、形成在第一ILD118上方的第二蚀刻停止层120、以及形成在第二蚀刻停止层120上方的第二ILD 122。例如,第二蚀刻停止层120可以包括与第一蚀刻停止层114类似的材料。第二蚀刻停止层120可以包括中间蚀刻停止层(MESL)。第一ILD 118和第二ILD 122可以包括例如氧化物、氮化物、或其他类型的绝缘材料。
然后,如图7和图8所示,形成了接触件127,该接触件与鳍104电连接,例如,与形成在鳍104上方的半导体材料110电连接。如图7所示,通过去除绝缘材料118/120/122以及位于多个鳍104上方的部分蚀刻停止层114(例如,还去除了位于半导体材料110上方的蚀刻停止层114的顶部)来形成接触件127。例如,使用蚀刻工艺去除绝缘材料118/120/122和蚀刻停止层114的顶部。当通过探测蚀刻工艺的副产品探测出已到达蚀刻停止层114时,可以对蚀刻工艺进行调整,并且当蚀刻停止层114的副产品变少或减缓时(例如,这意味着蚀刻停止层114已经被从半导体材料110的顶面上去除掉了),可以调整停止该蚀刻工艺。根据一些实施例,如果孔116形成在位于半导体材料110之间的蚀刻停止层114中,那么蚀刻工艺无法到达蚀刻停止层114中的孔116。去除绝缘材料118/120/122和位于多个鳍104上方的蚀刻停止层114的顶部时在绝缘材料118/120/122和蚀刻停止层114的顶部中产生了凹槽124。如图7所示,去除位于鳍104上方的蚀刻停止层114的顶部使得鳍104的顶面上方的半导体材料110的顶部被暴露出来。
根据实施例,蚀刻停止层114的部分125保留在了鳍104上方的半导体材料110的最宽的部分112上面或上方。蚀刻停止层114留下的部分125可以包括尺寸d6,在一些实施例中,该尺寸可以包括至少15nm。可选地,尺寸d6可以包括其他值。
如图8所示,导电材料126形成在鳍104上方,例如,鳍104的上方的半导体材料110的暴露的顶部上方。例如,导电材料126可以包括铜、钨、其他导体材料,或其多层或组合。可选地,导体材料126可以包括其他材料。如最初所沉积的那样,半导体材料126还可以形成在第二ILD 122的顶面上方(未示出),并且可以使用CMP和/或蚀刻工艺从第二ILD 122上方去除过量的导体材料126,留下由导体材料126所形成的接触件127。在一些实施例中,接触件127可以包括插槽式接触件,例如,该接触件以大约10nm至100μm向纸张内外延伸,但可选地,接触件127可以包括其他尺寸。例如,接触件127也可以包括插塞式接触件。
图8示出了完成的半导体器件100的截面图,该完成的半导体器件包括晶体管130、半导体材料110、以及CESL 114,该晶体管包括鳍104。接触件127为晶体管130提供了电连接。接触件127可以与半导体器件100的其他器件或部件相连接,和/或接触件127可以与通过对半导体器件100的层(未示出)进行金属化而随后形成在工件102的顶面上的接触焊盘相连接。
图9是图8所示的半导体器件的俯视图,示出接触件127可以包括插槽式接触件,该接触件在鳍104的顶部上方纵向地延伸。
图10是图8所示的半导体器件100的一部分的更详细的视图。示出了半导体材料110的最宽的部分112附近的放大视图。在阴影的134处示出了通过本公开的实施例而得到缓解的潜在问题。如果在蚀刻工艺之后在半导体材料110的最宽的部分112的上方留下的蚀刻停止层114(例如,包括尺寸d7)的数量不够的话,那么位于鳍104上方的半导体材料110之间的蚀刻停止层114的顶面中将形成开口。当沉积或形成了导体材料126时,如图10阴影的132处所示的那样,导体材料126的部分将填充开口,并且在半导体材料110之间并且可能地还有鳍104的顶部之间形成导体材料。在鳍104和半导体材料110之间形成导体材料126可能造成可靠性问题并且可能增加结点漏电。
优选地,根据本文所述的实施方式,半导体材料110的形成、蚀刻停止层114的形成,或半导体材料110的形成和蚀刻停止层114的形成两者均是受控的,在用于去除绝缘材料118/120/122以及蚀刻停止层114的顶部的蚀刻工艺之后,当形成接触件127时,蚀刻停止层114的部分125以尺寸d6设置在半导体材料110的最宽的部分112的上方。可以通过控制半导体材料110之间的包括了尺寸d4(见图4)的间隔(例如,通过控制多个鳍104上方的半导体材料110的最宽的部分112之间的间隔)来控制半导体材料110的形成。例如,可以通过控制蚀刻停止层114的厚度来控制蚀刻停止层114的形成。可以可选地使用其他方法来控制半导体材料110和蚀刻停止层114的形成。
在一些实施例中,对接触蚀刻停止层114的厚度进行选择,使得接触蚀刻停止层114的厚度等于位于多个鳍104上方的半导体材料110之间最小间隔的至少一半,从而确保在半导体材料110的最宽的部分112之间不产生开口。根据一些实施例,例如,如果位于半导体材料110的最宽的部分112之间的包括了尺寸d4(见图4)的间隔约为40nm,那么接触蚀刻停止层114的厚度可以被选择成约为20nm或更大。在其他实施例中,可以基于蚀刻停止层114的厚度来选择半导体材料110的最宽部分112之间的间隔或尺寸d4。
控制半导体材料110和蚀刻停止层114的形成可以包括考虑鳍104的尺寸d1、d2、和d3以及绝缘材料106中的凹槽108的数量,这可以影响,例如,用于生长的半导体材料110的材料量和用于沉积的蚀刻停止层114的材料量。
根据一些实施例,为了避免过多地去除外延生长的半导体材料110的最宽部分112上的接触蚀刻掩膜层114,还要良好地控制用于去除绝缘材料118/120/122以及蚀刻停止层114的顶部的蚀刻工艺。
图11是制造半导体器件100的流程图140。提供了带有多个鳍104的工件102(步骤142),并且在鳍104的顶面上方形成了半导体材料110(步骤144)。由于鳍104之间存在绝缘材料106,半导体材料110不形成在鳍104的侧面上。在半导体材料110上方形成蚀刻停止层114(步骤146)。在蚀刻停止层114上方沉积绝缘材料118/120/122(步骤148),并且从多个鳍104上方去除绝缘材料118/120/122以及蚀刻停止层114的部分(步骤150)。对步骤144、步骤146或步骤144和146两者进行控制,以便去除每个蚀刻停止层114的部分,但不去除位于鳍104的顶面的半导体材料110的最宽部分之间的蚀刻停止层114(步骤152)。
本公开的实施例的优点包括提供新颖的制造方法,其中,防止了在用于FInFET结构和应用的非混合的外延轮廓中形成位于鳍104之间的传导接触材料126。该新颖的方法提供了非混合外延轮廓中的接触件放置问题以及潜在的接触件蚀刻问题的解决方案。对蚀刻停止层114的厚度和/或位于外延生长的半导体材料110的最宽部分112之间的包括了尺寸d4的间隔进行控制、调节、和/或选择来防止过度蚀刻位于半导体材料110和/或鳍104之间的蚀刻停止层114。通过被用于形成蚀刻停止层114和半导体材料110的良好的控制方法来避免在接触蚀刻停止层114旁使用空隙填充材料的要求,从而节省了制造时间和费用。减少或消除了接触件127形成时的可靠性问题。用于半导体器件100和晶体管130的新颖的制造方法在制造工艺流程中是容易实施的。
根据本公开的一个实施例,制造半导体器件的方法包括:提供包括多个鳍的工件,以及在多个鳍的顶面上方形成半导体材料。在半导体材料上方形成蚀刻停止层,以及在蚀刻停止层上方形成绝缘材料。从多个鳍的上方去除该绝缘材料和蚀刻停止层的部分。对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除部分蚀刻停止层时不会去除位于多个鳍上方的半导体材料的最宽部分之间的蚀刻停止层。
根据另一个实施例,一种制造半导体器件的方法包括:提供工件,在工件上方形成多个鳍,以及在多个鳍中的每个的顶面上方外延生长半导体材料。在半导体材料上方形成蚀刻停止层,在蚀刻停止层上方形成绝缘材料,并且从多个鳍上方去除绝缘材料和部分蚀刻停止层。在多个鳍上方形成导电材料。对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除部分蚀刻停止层时不会去除位于多个鳍上方的半导体材料的最宽部分之间的蚀刻停止层。
根据又一个实施例,一种制造晶体管的方法包括:提供工件,在工件上方形成多个鳍,以及在多个鳍中的每个的顶面上方外延生长非混合的半导体材料。与中心区域相比,半导体材料更接近半导体材料的顶面和底面。该方法包括在半导体材料上方形成蚀刻停止层,其中,部分蚀刻停止层形成在半导体材料的较宽的中心区域下面,在蚀刻停止层上方设置绝缘材料,以及蚀刻掉位于多个鳍上方的绝缘材料和蚀刻停止层的顶部。在多个鳍上方形成导电材料,从而形成接触件。对形成半导体材料或形成蚀刻停止层进行控制,从而使得去除部分蚀刻停止层时不会去除位于多个鳍上方的半导体材料的较宽的中心区域之间的蚀刻停止层。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (10)
1.一种制造半导体器件的方法,包括:
提供包括多个鳍的工件;
在所述多个鳍的顶面上方形成半导体材料;
在所述半导体材料上方形成蚀刻停止层;
在所述蚀刻停止层上方设置绝缘材料;以及
从所述多个鳍的上方去除所述蚀刻停止层的一部分和所述绝缘材料,其中,对形成所述半导体材料或形成所述蚀刻停止层进行控制,从而使得去除所述蚀刻停止层的所述一部分时不会去除位于所述多个鳍上方的所述半导体材料的最宽部分之间的蚀刻停止层。
2.根据权利要求1所述的方法,其中,对形成所述半导体材料以及形成所述蚀刻停止层两者进行控制。
3.根据权利要求1所述的方法,其中,通过控制位于所述多个鳍上方的所述半导体材料的所述最宽部分之间的间隔来控制所述半导体材料的形成。
4.根据权利要求1所述的方法,其中,通过控制所述蚀刻停止层的厚度来控制所述蚀刻停止层的形成。
5.根据权利要求1所述的方法,其中,形成所述蚀刻停止层包括形成对所述绝缘材料具有蚀刻选择性的材料。
6.根据权利要求5所述的方法,其中,形成所述蚀刻停止层包括形成SiN、SiON、SiC、或SiOC。
7.根据权利要求1所述的方法,其中,去除所述蚀刻停止层的所述一部分包括在所述多个鳍上方的所述半导体材料的所述最宽部分上方留下至少大约15nm的蚀刻停止层。
8.根据权利要求1所述的方法,其中,所述多个鳍包括鳍式场效应晶体管(FinFET)的鳍。
9.一种制造半导体器件的方法,包括:
提供工件;
在所述工件上方形成多个鳍;
在所述多个鳍中的每一个的顶面上方外延生长半导体材料;
在所述半导体材料上方形成蚀刻停止层;
在所述蚀刻停止层上方放置绝缘材料;
从所述多个鳍的上方去除所述蚀刻停止层的一部分和所述绝缘材料;以及
在所述多个鳍上方形成导电材料,其中,对形成所述半导体材料或形成所述蚀刻停止层进行控制,从而使得去除所述蚀刻停止层的所述一部分时不会去除位于所述多个鳍上方的所述半导体材料的最宽部分之间的蚀刻停止层。
10.一种制造晶体管的方法,包括:
提供工件;
在所述工件上方形成多个鳍;
在所述多个鳍中的每一个的顶面上方外延生长非混合的半导体材料,所述半导体材料的接近中心区域比所述半导体材料的接近顶面区域更宽;
在所述半导体材料上方形成蚀刻停止层,其中,所述蚀刻停止层的一部分形成在所述半导体材料的较宽的中心区域下面;
在所述蚀刻停止层上方设置绝缘材料;
蚀刻掉位于所述多个鳍上方的所述蚀刻停止层的顶部和所述绝缘材料;以及
在所述多个鳍上方形成导电材料,从而形成接触件,其中,对形成所述半导体材料或形成所述蚀刻停止层进行控制,从而使得去除所述蚀刻停止层的顶部时不会去除位于所述多个鳍上方的所述半导体材料的较宽的中心区域之间的蚀刻停止层。
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---|---|---|---|---|
CN105244380A (zh) * | 2014-07-07 | 2016-01-13 | 联华电子股份有限公司 | 鳍式场效晶体管及其制造方法 |
CN105428515A (zh) * | 2014-07-24 | 2016-03-23 | 三星电子株式会社 | 热电元件和包括热电元件的半导体装置 |
CN106024868A (zh) * | 2015-03-27 | 2016-10-12 | 三星电子株式会社 | 半导体装置 |
CN106711217A (zh) * | 2015-11-16 | 2017-05-24 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管及其制造方法 |
CN107154356A (zh) * | 2016-03-03 | 2017-09-12 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN110416297A (zh) * | 2018-04-27 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | N型鳍式场效应晶体管及其形成方法 |
CN111933615A (zh) * | 2015-05-04 | 2020-11-13 | 三星电子株式会社 | 具有接触插塞的半导体器件 |
Families Citing this family (184)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8377779B1 (en) * | 2012-01-03 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing semiconductor devices and transistors |
US9024387B2 (en) * | 2012-06-25 | 2015-05-05 | International Business Machines Corporation | FinFET with body contact |
US9018713B2 (en) | 2012-06-25 | 2015-04-28 | International Business Machines Corporation | Plural differential pair employing FinFET structure |
US8658536B1 (en) * | 2012-09-05 | 2014-02-25 | Globalfoundries Inc. | Selective fin cut process |
US9159831B2 (en) * | 2012-10-29 | 2015-10-13 | United Microelectronics Corp. | Multigate field effect transistor and process thereof |
US8921191B2 (en) * | 2013-02-05 | 2014-12-30 | GlobalFoundries, Inc. | Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same |
US9018054B2 (en) | 2013-03-15 | 2015-04-28 | Applied Materials, Inc. | Metal gate structures for field effect transistors and method of fabrication |
CN104124174B (zh) * | 2013-04-28 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US9048317B2 (en) | 2013-07-31 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US9054218B2 (en) * | 2013-08-07 | 2015-06-09 | International Business Machines Corporation | Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same |
US9123564B2 (en) | 2013-12-05 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device with conformal doping and method of making |
US9159794B2 (en) * | 2014-01-16 | 2015-10-13 | Globalfoundries Inc. | Method to form wrap-around contact for finFET |
EP2908345A1 (en) * | 2014-02-13 | 2015-08-19 | IMEC vzw | Contact formation in Ge-containing semiconductor devices |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9443769B2 (en) | 2014-04-21 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wrap-around contact |
US10177133B2 (en) | 2014-05-16 | 2019-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including source/drain contact having height below gate stack |
US9608116B2 (en) | 2014-06-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFETs with wrap-around silicide and method forming the same |
US9966471B2 (en) | 2014-06-27 | 2018-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked Gate-All-Around FinFET and method forming the same |
CN105261645B (zh) * | 2014-07-16 | 2020-02-21 | 联华电子股份有限公司 | 半导体装置及其制作方法 |
US9917240B2 (en) * | 2014-07-24 | 2018-03-13 | Samsung Electronics Co., Ltd. | Thermoelectric element, method of manufacturing the same and semiconductor device including the same |
US9614088B2 (en) | 2014-08-20 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal gate structure and manufacturing method thereof |
KR102311937B1 (ko) * | 2014-09-23 | 2021-10-14 | 삼성전자주식회사 | 콘택 플러그를 갖는 반도체 소자 및 그 형성 방법 |
US9437484B2 (en) | 2014-10-17 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US9508858B2 (en) | 2014-11-18 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contacts for highly scaled transistors |
US9466494B2 (en) | 2014-11-18 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective growth for high-aspect ration metal fill |
US9613850B2 (en) | 2014-12-19 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithographic technique for feature cut by line-end shrink |
US9412817B2 (en) | 2014-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide regions in vertical gate all around (VGAA) devices and methods of forming same |
US9876114B2 (en) | 2014-12-30 | 2018-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D FinFET metal gate |
US9673112B2 (en) | 2015-02-13 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor fabrication with height control through active region profile |
US9859115B2 (en) | 2015-02-13 | 2018-01-02 | National Taiwan University | Semiconductor devices comprising 2D-materials and methods of manufacture thereof |
US9502499B2 (en) | 2015-02-13 | 2016-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure having multi-layered isolation trench structures |
US9502502B2 (en) | 2015-03-16 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
KR102340329B1 (ko) * | 2015-03-25 | 2021-12-21 | 삼성전자주식회사 | 반도체 소자 |
US9698048B2 (en) | 2015-03-27 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor device |
KR102316119B1 (ko) * | 2015-04-02 | 2021-10-21 | 삼성전자주식회사 | 반도체 장치 |
US9761683B2 (en) | 2015-05-15 | 2017-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9576796B2 (en) | 2015-05-15 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US9741829B2 (en) | 2015-05-15 | 2017-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10062779B2 (en) | 2015-05-22 | 2018-08-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR102415327B1 (ko) * | 2015-06-01 | 2022-06-30 | 삼성전자주식회사 | 비활성-핀을 갖는 반도체 소자 및 그 형성 방법 |
KR102258109B1 (ko) * | 2015-06-08 | 2021-05-28 | 삼성전자주식회사 | 누설 전류를 차단할 수 있는 반도체 소자 및 그의 형성 방법 |
US9685368B2 (en) | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
US10403744B2 (en) | 2015-06-29 | 2019-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices comprising 2D-materials and methods of manufacture thereof |
US11424399B2 (en) | 2015-07-07 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated thermoelectric devices in Fin FET technology |
US9418886B1 (en) | 2015-07-24 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming conductive features |
US9536980B1 (en) | 2015-07-28 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate spacers and methods of forming same |
US9564363B1 (en) | 2015-08-19 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming butted contact |
US9831090B2 (en) | 2015-08-19 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for semiconductor device having gate spacer protection layer |
US9721887B2 (en) | 2015-08-19 | 2017-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of forming metal interconnection |
US9698100B2 (en) | 2015-08-19 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for interconnection |
US9728402B2 (en) | 2015-08-21 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flowable films and methods of forming flowable films |
US9786602B2 (en) | 2015-08-21 | 2017-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection structure and methods of fabrication the same |
US9490136B1 (en) | 2015-08-31 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trench cut |
US9831116B2 (en) | 2015-09-15 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETS and methods of forming FETs |
US9905641B2 (en) * | 2015-09-15 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
US9613856B1 (en) | 2015-09-18 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming metal interconnection |
US9679978B2 (en) | 2015-09-24 | 2017-06-13 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US9972529B2 (en) | 2015-09-28 | 2018-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming metal interconnection |
US10163797B2 (en) | 2015-10-09 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming interlayer dielectric material by spin-on metal oxide deposition |
US9735052B2 (en) | 2015-10-12 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal lines for interconnect structure and method of manufacturing same |
US9711533B2 (en) | 2015-10-16 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof |
US9659864B2 (en) | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
KR102427326B1 (ko) | 2015-10-26 | 2022-08-01 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US9647116B1 (en) | 2015-10-28 | 2017-05-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating self-aligned contact in a semiconductor device |
US9818690B2 (en) | 2015-10-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned interconnection structure and method |
US9627531B1 (en) | 2015-10-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field-effect transistor with dual vertical gates |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9960273B2 (en) * | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
US9899387B2 (en) | 2015-11-16 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US10164051B2 (en) | 2015-11-16 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9633999B1 (en) | 2015-11-16 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for semiconductor mid-end-of-line (MEOL) process |
US10340348B2 (en) | 2015-11-30 | 2019-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing finFETs with self-align contacts |
US9773879B2 (en) | 2015-11-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10163719B2 (en) | 2015-12-15 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming self-alignment contact |
US9873943B2 (en) | 2015-12-15 | 2018-01-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method for spatial atomic layer deposition |
US10497701B2 (en) | 2015-12-16 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9728501B2 (en) | 2015-12-21 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
DE102016119024B4 (de) | 2015-12-29 | 2023-12-21 | Taiwan Semiconductor Manufacturing Co. Ltd. | Verfahren zum Herstellen einer FinFET-Vorrichtung mit epitaktischen Elementen mit flacher Oberseite |
US9887128B2 (en) | 2015-12-29 | 2018-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for interconnection |
US10163704B2 (en) | 2015-12-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10490552B2 (en) * | 2015-12-29 | 2019-11-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device having flat-top epitaxial features and method of making the same |
DE102016116026B4 (de) | 2015-12-29 | 2024-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und Herstellungsverfahren |
US9614086B1 (en) | 2015-12-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conformal source and drain contacts for multi-gate field effect transistors |
US9899269B2 (en) | 2015-12-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-gate device and method of fabrication thereof |
US11088030B2 (en) | 2015-12-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
KR102399353B1 (ko) | 2016-01-05 | 2022-05-19 | 삼성전자주식회사 | 식각 방법 및 이를 이용한 반도체 소자의 제조 방법 |
US10115796B2 (en) | 2016-01-07 | 2018-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of pulling-back sidewall metal layer |
US10811262B2 (en) | 2016-01-14 | 2020-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a uniform and thin silicide layer on an epitaxial source/ drain structure and manufacturing method thereof |
US9881872B2 (en) | 2016-01-15 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a local interconnect in a semiconductor device |
US10727094B2 (en) | 2016-01-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd | Thermal reflector device for semiconductor fabrication tool |
US10163912B2 (en) | 2016-01-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for semiconductor device fabrication with improved source drain proximity |
US10283605B2 (en) | 2016-01-29 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Self-aligned metal gate etch back process and device |
US9812451B2 (en) | 2016-02-03 | 2017-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd | Field effect transistor contact with reduced contact resistance |
US10535558B2 (en) | 2016-02-09 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
US9543161B1 (en) | 2016-02-10 | 2017-01-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of planarizating film |
US9947756B2 (en) | 2016-02-18 | 2018-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
US9754822B1 (en) | 2016-03-02 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
US9755019B1 (en) | 2016-03-03 | 2017-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10056407B2 (en) | 2016-03-04 | 2018-08-21 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device and a method for fabricating the same |
US9711402B1 (en) | 2016-03-08 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming contact metal |
US10109627B2 (en) | 2016-03-08 | 2018-10-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric |
US9911611B2 (en) | 2016-03-17 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming openings in a material layer |
DE102016114724B4 (de) | 2016-03-25 | 2021-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen und Vorrichtung |
US9779984B1 (en) | 2016-03-25 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming trenches with different depths |
US9548366B1 (en) | 2016-04-04 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self aligned contact scheme |
US9847477B2 (en) | 2016-04-12 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a bottom electrode of a magnetoresistive random access memory cell |
US9805951B1 (en) | 2016-04-15 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of integration process for metal CMP |
US10475847B2 (en) | 2016-04-28 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having stress-neutralized film stack and method of fabricating same |
US9893062B2 (en) | 2016-04-28 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US9899266B2 (en) | 2016-05-02 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structures and methods of forming the same |
US11127629B2 (en) | 2016-05-17 | 2021-09-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
US9917085B2 (en) | 2016-05-31 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate isolation structure and method forming same |
US10276662B2 (en) | 2016-05-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming contact trench |
US10109467B2 (en) | 2016-06-01 | 2018-10-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Advanced exhaust system |
US9941386B2 (en) | 2016-06-01 | 2018-04-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with fin structure and method for forming the same |
US9627258B1 (en) | 2016-06-15 | 2017-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a contact |
US10164032B2 (en) | 2016-06-17 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned contact and manufacturing method thereof |
US10515822B2 (en) | 2016-06-20 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing bottom layer wrinkling in a semiconductor device |
US10008414B2 (en) | 2016-06-28 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for widening Fin widths for small pitch FinFET devices |
US10685873B2 (en) | 2016-06-29 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer for semiconductor devices |
US9768064B1 (en) | 2016-07-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation method of semiconductor device structure |
US9640540B1 (en) | 2016-07-19 | 2017-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for an SRAM circuit |
US10121873B2 (en) | 2016-07-29 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate and contact plug design and method forming same |
US9721805B1 (en) | 2016-07-29 | 2017-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation method of semiconductor device structure |
US10199500B2 (en) | 2016-08-02 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer film device and method |
US9991205B2 (en) | 2016-08-03 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10157918B2 (en) * | 2016-08-03 | 2018-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10510850B2 (en) | 2016-08-03 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US9929271B2 (en) | 2016-08-03 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10522536B2 (en) | 2016-08-03 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with gate stacks |
US10043886B2 (en) | 2016-08-03 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate formation through etch back process |
US10164111B2 (en) | 2016-08-03 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and methods of manufacture |
US10269926B2 (en) | 2016-08-24 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Purging deposition tools to reduce oxygen and moisture in wafers |
US9997524B2 (en) | 2016-08-24 | 2018-06-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory device and manufacturing method thereof |
US9865697B1 (en) | 2016-08-25 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US9812358B1 (en) | 2016-09-14 | 2017-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structures and methods of forming the same |
US9865589B1 (en) | 2016-10-31 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of fabricating ESD FinFET with improved metal landing in the drain |
US10049930B2 (en) | 2016-11-28 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and operation method thereof |
US10043665B2 (en) | 2016-11-28 | 2018-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation method of semiconductor device structure with semiconductor nanowire |
US10290546B2 (en) | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Threshold voltage adjustment for a gate-all-around semiconductor structure |
US9837539B1 (en) | 2016-11-29 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming |
US9881834B1 (en) | 2016-11-29 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact openings and methods forming same |
US10510598B2 (en) | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned spacers and method forming same |
US9985134B1 (en) | 2016-11-29 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods of forming FinFETs |
US10453943B2 (en) * | 2016-11-29 | 2019-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETS and methods of forming FETS |
US10008416B2 (en) | 2016-11-30 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming a protective layer to prevent formation of leakage paths |
US10707316B2 (en) | 2016-12-09 | 2020-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure with gate structure |
US9865595B1 (en) | 2016-12-14 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same |
US10157781B2 (en) | 2016-12-14 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor structure using polishing process |
US10651171B2 (en) | 2016-12-15 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co. Ltd. | Integrated circuit with a gate structure and method making the same |
US10049936B2 (en) | 2016-12-15 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same |
US9972571B1 (en) | 2016-12-15 | 2018-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Logic cell structure and method |
US10079289B2 (en) | 2016-12-22 | 2018-09-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structure and methods thereof |
US10164106B2 (en) | 2016-12-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
KR102568562B1 (ko) * | 2017-01-24 | 2023-08-18 | 삼성전자주식회사 | 반도체 장치 |
US9985023B1 (en) | 2017-02-21 | 2018-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure |
US9859364B1 (en) | 2017-03-03 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10153198B2 (en) | 2017-04-07 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-resistance contact plugs and method forming same |
US10522643B2 (en) | 2017-04-26 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate |
US10522417B2 (en) | 2017-04-27 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with different liners for PFET and NFET and method of fabricating thereof |
DE102018114209A1 (de) * | 2017-07-31 | 2019-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source -und-drain-struktur mit einem reduzierten kontaktwiderstand und einer verbesserten beweglichkeit |
US10510875B2 (en) * | 2017-07-31 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
US10141431B1 (en) | 2017-07-31 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxy source/drain regions of FinFETs and method forming same |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1641845A (zh) * | 2003-12-08 | 2005-07-20 | 国际商业机器公司 | 一种形成翅片场效应晶体管的方法 |
TW200536122A (en) * | 2004-04-30 | 2005-11-01 | Taiwan Semiconductor Mfg | Finfet transistor device on soi and method of fabrication |
US7550773B2 (en) * | 2007-06-27 | 2009-06-23 | International Business Machines Corporation | FinFET with top body contact |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6642090B1 (en) * | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
US6933183B2 (en) | 2003-12-09 | 2005-08-23 | International Business Machines Corporation | Selfaligned source/drain FinFET process flow |
US7087471B2 (en) | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Locally thinned fins |
US7241655B2 (en) * | 2004-08-30 | 2007-07-10 | Micron Technology, Inc. | Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array |
US8440517B2 (en) * | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8264021B2 (en) | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
US8377779B1 (en) * | 2012-01-03 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing semiconductor devices and transistors |
-
2012
- 2012-01-03 US US13/342,772 patent/US8377779B1/en active Active
- 2012-04-13 KR KR1020120038512A patent/KR101374489B1/ko active IP Right Grant
- 2012-05-11 CN CN201210147693.8A patent/CN103187304B/zh active Active
- 2012-12-28 US US13/730,590 patent/US8679925B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1641845A (zh) * | 2003-12-08 | 2005-07-20 | 国际商业机器公司 | 一种形成翅片场效应晶体管的方法 |
TW200536122A (en) * | 2004-04-30 | 2005-11-01 | Taiwan Semiconductor Mfg | Finfet transistor device on soi and method of fabrication |
US7550773B2 (en) * | 2007-06-27 | 2009-06-23 | International Business Machines Corporation | FinFET with top body contact |
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CN105244380A (zh) * | 2014-07-07 | 2016-01-13 | 联华电子股份有限公司 | 鳍式场效晶体管及其制造方法 |
CN105428515A (zh) * | 2014-07-24 | 2016-03-23 | 三星电子株式会社 | 热电元件和包括热电元件的半导体装置 |
CN105428515B (zh) * | 2014-07-24 | 2019-05-31 | 三星电子株式会社 | 热电元件和包括热电元件的半导体装置 |
CN106024868A (zh) * | 2015-03-27 | 2016-10-12 | 三星电子株式会社 | 半导体装置 |
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CN106711217B (zh) * | 2015-11-16 | 2023-08-08 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管及其制造方法 |
CN107154356B (zh) * | 2016-03-03 | 2020-01-14 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN107154356A (zh) * | 2016-03-03 | 2017-09-12 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN110416297A (zh) * | 2018-04-27 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | N型鳍式场效应晶体管及其形成方法 |
CN110416297B (zh) * | 2018-04-27 | 2023-07-04 | 中芯国际集成电路制造(上海)有限公司 | N型鳍式场效应晶体管及其形成方法 |
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US8679925B2 (en) | 2014-03-25 |
US8377779B1 (en) | 2013-02-19 |
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US20130171790A1 (en) | 2013-07-04 |
KR101374489B1 (ko) | 2014-03-13 |
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