CN106206308A - 制造finfet器件的方法 - Google Patents

制造finfet器件的方法 Download PDF

Info

Publication number
CN106206308A
CN106206308A CN201510226190.3A CN201510226190A CN106206308A CN 106206308 A CN106206308 A CN 106206308A CN 201510226190 A CN201510226190 A CN 201510226190A CN 106206308 A CN106206308 A CN 106206308A
Authority
CN
China
Prior art keywords
grid
fin
stack
fin part
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510226190.3A
Other languages
English (en)
Other versions
CN106206308B (zh
Inventor
林志翰
林志忠
张铭庆
陈昭成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106206308A publication Critical patent/CN106206308A/zh
Application granted granted Critical
Publication of CN106206308B publication Critical patent/CN106206308B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

本发明公开了一种制造鳍式场效应晶体管(FinFET)器件的方法。该方法包括在鳍部件的不同部分上方形成第一栅极堆叠件和第二栅极堆叠件，鳍部件形成在衬底上，在第一和第二栅极堆叠件之间的间隙中形成第一介电层，去除第一栅极堆叠件以形成第一栅极沟槽，因此第一栅极沟槽暴露鳍部件的部分。该方法也包括去除鳍部件的暴露部分并在第一栅极沟槽中形成隔离部件。

Description

制造FINFET器件的方法
技术领域
本发明涉及制造FINFET器件的方法。
背景技术
半导体集成电路(IC)工业已经经历了快速发展。在IC演进过程中，功能密度(即，每芯片面积中互连器件的数量)通常已经增加，同时几何尺寸(即，可使用制造工艺生成的最小组件(或线))已经减小。这种按比例缩小工艺通常通过增加生产效率和降低相关成本来提供益处。
这种按比例缩小已经增加了处理和制造IC的复杂性，并且为了实现这些进步，需要IC处理和制造中的类似的发展。例如，已经引进了诸如鳍式场效应晶体管(FinFET)的三维晶体管来取代平面晶体管。尽管现有的FinFET器件及制造FinFET器件的方法通常已经足够用于它们的预期目的，但它们并非在所有方面完全令人满意。例如，期望一种用于形成鳍切口的更灵活的集成。
发明内容
为了解决现有技术中的问题，根据本发明的一个方面，提供了一种方法，包括：在鳍部件的不同部分上方形成第一栅极堆叠件和第二栅极堆叠件，所述鳍部件形成在衬底上；在所述第一栅极堆叠件和所述第二栅极堆叠件之间的间隙中形成第一介电层；去除所述第一栅极堆叠件以形成第一栅极沟槽，其中，所述第一栅极沟槽暴露所述鳍部件的部分；去除所述鳍部件的暴露部分；以及在所述第一栅极沟槽中形成隔离部件。
在上述方法中，其中，在去除所述鳍部件的所述暴露部分之后，所述鳍部件具有与第二部分间隔开的第一部分。
在上述方法中，其中，去除所述第一栅极堆叠件包括：用图案化的硬掩模覆盖所述第二栅极堆叠件。
在上述方法中，其中，通过不蚀刻所述第一介电层的选择性蚀刻来去除所述第一栅极堆叠件。
在上述方法中，其中，通过不蚀刻所述第一介电层的选择性蚀刻来去除所述鳍部件的所述暴露部分。
在上述方法中，还包括：在形成所述第一栅极堆叠件之后，沿着所述第一栅极堆叠件的侧壁形成间隔件，其中，通过不蚀刻所述间隔件的选择性蚀刻来去除所述第一栅极堆叠件，其中，通过不蚀刻所述间隔件的所述选择性蚀刻来去除所述鳍结构的所述暴露部分。
在上述方法中，其中，形成所述隔离部件包括：用第二介电层填充所述第一栅极沟槽和鳍切口；以及应用化学机械抛光(CMP)以去除过量的所述第二介电层。
在上述方法中，还包括：在用所述第一介电层填充两个邻近的所述第一栅极堆叠件之间的间隙之后，应用CMP以去除过量的第一介电层并暴露所述第一栅极堆叠件的顶面。
在上述方法中，还包括：在形成所述隔离部件之后，去除所述第二栅极堆叠件以暴露所述鳍部件的相应的部分；以及在所述鳍结构的所述暴露部分上方形成所述第二栅极堆叠件，其中，所述第一栅极堆叠件是伪栅极堆叠件，其中，所述第二栅极堆叠件是高k/金属栅极堆叠件(HK/MG)。
在上述方法中，还包括：在形成所述隔离部件之后，去除所述第二栅极堆叠件以暴露所述鳍部件的相应的部分；以及在所述鳍结构的所述暴露部分上方形成所述第二栅极堆叠件，其中，所述第一栅极堆叠件是伪栅极堆叠件，其中，所述第二栅极堆叠件是高k/金属栅极堆叠件(HK/MG)；其中，通过不蚀刻所述第一介电层和第二介电层的选择性蚀刻来去除所述第二栅极堆叠件，其中，在不使用图案化的硬掩模的情况下，去除所述第二栅极堆叠件。
根据本发明的另一个方面，提供了一种用于制造鳍式场效应晶体管(FinFET)器件的方法，所述方法包括：在鳍部件的不同部分上方形成第一栅极堆叠件，所述鳍部件形成在衬底上；沿着所述第一栅极堆叠件的侧壁形成间隔件；用介电层填充两个邻近的所述第一栅极堆叠件之间的间隙；去除所述第一栅极堆叠件以形成栅极沟槽，其中，所述鳍部件的相应的部分暴露在所述栅极沟槽中；去除第一区域中的所述鳍部件的所述暴露部分，同时保留第二区域中的所述鳍部件的所述暴露部分；在所述第二区域中的所述鳍部件的所述暴露部分上方形成第二栅极堆叠件；以及同时在所述第一区域中的所述栅极沟槽中形成栅极堆叠部件。
在上述方法中，其中，在去除所述第一区域中的所述鳍部件的所述暴露部分之后，所述鳍部件具有与第二部分隔离开的第一部分。
在上述方法中，其中，去除所述第一区域中的所述鳍部件的所述暴露部分包括：用图案化的硬掩模覆盖所述第二区域中的所述鳍部件的所述暴露部分。
在上述方法中，其中，通过不蚀刻所述间隔件和所述介电层的选择性蚀刻来去除所述第一栅极堆叠件。
在上述方法中，其中，通过不蚀刻所述间隔件和所述介电层的选择性蚀刻来去除所述第一栅极堆叠件；其中，在不使用图案化的硬掩模的情况下去除所述第一栅极堆叠件。
在上述方法中，其中，通过不蚀刻所述间隔件和所述介电层的选择性蚀刻来去除所述第一区域中的所述鳍部件的所述暴露部分。
在上述方法中，还包括：在用所述介电层填充两个邻近的所述第一栅极堆叠件之间的间隙之后，应用化学机械抛光(CMP)以去除过量的所述介电层并暴露所述第一栅极堆叠件的顶面。
根据本发明的又一个方面，提供了一种器件，包括：鳍部件的第一部分和所述鳍部件的第二部分，设置在衬底上方，其中所述第一部分沿着在第一方向上的线与所述第二部分对准；隔离部件，将所述鳍部件的所述第一部分和所述第二部分隔离开，从而使得所述隔离部件的底面嵌入在所述衬底中；以及高k/金属栅极(HK/MG)，包裹在所述鳍部件的第一部分和所述鳍部件的第二部分上方。
在上述器件中，其中，所述隔离部件包括沿着垂直于所述第一方向的第二方向的具有垂直轮廓的介电层。
在上述器件中，其中，所述隔离部件包括沿着垂直于所述第一方向的第二方向的具有垂直轮廓的HK/MG。
附图说明
当结合附图进行阅读时，从下面详细的描述可以最佳地理解本发明的各方面。应该注意，根据工业中的标准实践，图中的各个部件没有按比例绘制。实际上，为了清楚的讨论，示出的部件的尺寸可以被任何增加或减少。
图1是根据一些实施例的用于制造FinFET器件的示例性方法的流程图。
图2A是根据一些实施例的示例性FinFET器件的示意性透视图。
图2B是示例性半导体器件沿着图2A中的线A-A的截面图。
图3A是根据一些实施例的示例性FinFET器件的示意性透视图。
图3B是示例性半导体器件沿着图3A中的线A-A的截面图。
图4和图5是示例性FinFET器件沿着图3A中的线B-B的截面图。
图6、图7和图8A是根据一些实施例的示例性FinFET器件的示意性透视图。
图8B是示例性FinFET器件沿着图8A中的线B-B的截面图。
图9A是根据一些实施例的示例性FinFET器件的示意性透视图。
图9B是示例性FinFET器件沿着图9A中的线B-B的截面图。
图10和图11A是根据一些实施例的示例性FinFET器件的示意性透视图。
图11B是示例性FinFET器件沿着图11A中的线B-B的截面图。
图11C是示例性FinFET器件沿着图11A中的线C-C的截面图。
图12是根据一些实施例的用于制造FinFET器件的示例性方法的流程图。
图13至图16A是根据一些实施例的示例性FinFET器件的示意性透视图。
图16B是示例性FinFET器件沿着图16A中的线B-B的截面图。
图16C是示例性FinFET器件沿着图16A中的线C-C的截面图。
具体实施方式
以下公开内容提供了许多不同的实施例或实例用以实现本发明的不同特征。以下描述了元件和布置的特定实例以简化本发明。当然，这些仅仅是实例并不打算限定。例如，在随后的说明书中，在第二部件上方或上形成第一部件可以包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件可能形成在第一部件和第二部件之间，使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实施例中重复参考标号和/或字符。该重复只是为了简单和清楚的目的，且其本身并不指定所讨论的各个实施例和/或结构之间的关系。
而且，为便于描述，本文中可以使用诸如“在···之下”、“下面”、“下”、“在···之上”、“上”等空间相对术语以描述附图中所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位之外，空间相对术语旨在包括器件在使用或操作中的的不同方位。装置可以以其他方位定向(旋转90度或者在其他方位上)，并且本文所使用的空间相对描述符可同样地作出相应的解释。
本发明涉及，但并不以其他方式限制于，一种FinFET器件。例如，该FinFET器件可为包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。以下公开将继续用FinFET为实例以示出本发明的各个实施例。然而，应当理解，本申请不应限于特定类型的器件，除非特别声明。
图1是根据一些实施例的用于制造FinFET器件200的方法100的流程图。应当理解，在该方法之前、期间和之后，可执行额外的步骤，并且对于该方法的其他实施例可以替代或消除所描述的步骤中的一些。参照各个附图共同描述FinFET器件200及其制造方法100。
参照图1和图2A至图2B，方法100开始于步骤102，提供具有多个鳍部件220和隔离区域230的衬底210。衬底210可以是块状硅衬底。可选地，衬底210可包括元素半导体，诸如多晶硅结构的硅或锗；化合物半导体，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。可能的衬底210也包括绝缘体上硅(SOI)衬底。使用注氧隔离(SIMOX)、晶圆接合和/或其他合适的方法来制造SOI衬底。
一些示例性衬底210也包括绝缘层。该绝缘层包括任何合适的材料，包括氧化硅、蓝宝石和/或它们的组合。示例性绝缘层可为埋氧层(BOX)。通过任何合适的工艺形成绝缘体，诸如注入(例如，SIMOX)、氧化、沉积和/或其他合适的工艺。在一些示例性FinFET前体200中，绝缘层为绝缘体上硅衬底的组件(例如，层)。
衬底210也可以包括各个掺杂区域。该掺杂区域可以掺杂有诸如硼或BF2的p型掺杂剂；诸如磷或砷的n型掺杂剂；或它们的组合。可以在衬底210上、在P阱结构中、在N阱结构中、在双阱结构中或使用凸起结构直接形成该掺杂区域。衬底210可进一步包括各个有源区域，诸如配置用于N型金属氧化物半导体晶体管器件的区域和配置用于P型金属氧化物半导体晶体管器件的区域。
在衬底210上形成多个鳍部件220。参照图2A，鳍部件220的高度沿着Z方向，而其长度沿着Y方向。通过任何合适的工艺形成鳍部件220，包括各个沉积、光刻和/或蚀刻工艺。示例性光刻工艺包括在衬底上方(例如，在硅层上)形成光刻胶层(抗蚀剂)、曝光该光刻胶至某图案、实施曝光后烘烤工艺、以及显影该光刻胶以形成包括光刻胶的掩蔽的元件。该掩蔽的元件然后被用于在衬底210内蚀刻鳍结构。使用反应性离子蚀刻(RIE)工艺和/或其他合适的工艺来蚀刻未由掩蔽的元件保护的区域。在实例中，通过图案化和蚀刻部分硅衬底210来形成鳍部件220。在另一实例中，通过图案化和蚀刻沉积在绝缘层(例如，SOI衬底的硅-绝缘体-硅堆叠件的上硅层)上方的硅层来形成鳍部件220。
在衬底210上形成多个隔离区域230以将有源区域隔离开。例如，隔离区域230将鳍部件220隔离开。隔离区域230可使用诸如浅沟槽隔离(STI)的传统隔离技术形成以限定并电隔离各个区域。该隔离区域230包氧化硅、氮化硅、氮氧化硅、气隙、其他合适的材料或它们的组合。隔离区域230通过任何合适的工艺形成。作为一个实例，通过将隔离层沉积在衬底210上方并使隔离层的部分凹进来形成隔离区域230并暴露鳍部件220的上部来形成隔离区域230。
在一些实施例中，衬底210具有源极/漏极区域(S/D)232和栅极区域234。在一些实施例中，S/D 232为源极区域且另一S/D区域232为漏极区域。S/D 232通过栅极区域234隔离开。
参照图1和图3A至图3B，方法100进行至步骤104，在衬底210上方形成包裹鳍部件220上方的第一栅极堆叠件310。在一个实施例中，第一栅极堆叠件310包括伪栅极堆叠件且该伪栅极堆叠件在后续阶段将由最终栅极堆叠件替代。具体地，在诸如在源极/漏极形成期间用于源极/漏极激活的热退火的高温热工艺(high thermal temperature processes)之后，随后高k介电/金属栅极(HK/MG)替代伪栅极堆叠件310。在一个实施例中，伪栅极堆叠件310包括伪介电层312和多晶硅(多晶硅)314。伪栅极堆叠件310可通过包括沉积、光刻图案化和蚀刻的合适的工序形成。在各个实例中，该沉积包括CVD、物理汽相沉积(PVD)、原子层沉积(ALD)、热氧化、其他合适的技术或它们的组合。该蚀刻工艺包括干蚀刻、湿蚀刻和/或其他蚀刻方法(例如，反应性离子蚀刻)。在本实施例中，栅极堆叠件310形成为具有垂直的轮廓。
再次参照图1和图3A至图3B，方法100进行至步骤106，沿着伪栅极堆叠件310的侧壁形成间隔件320。在一个实施例中，间隔件320的形成包括在衬底210和伪栅极堆叠件310上沉积间隔件材料层，以及随后对间隔件材料层实施各向异性蚀刻，从而形成间隔件320。该间隔件材料层可包括介电材料(诸如氧化硅、氮化硅或碳化硅)但与伪栅极堆叠件310的材料不同以在后续蚀刻工艺期间实现蚀刻选择性。间隔件材料层的沉积包括诸如CVD、PVD和/或ALD的合适的技术。在一个实例中各向异性蚀刻可包括等离子体蚀刻。在本实施例中，间隔件320形成为具有垂直的轮廓。
参照图1和图4，方法100进行至步骤108，在S/D区域232中形成源极/漏极部件350。在一个实施例中，通过选择性蚀刻工艺使S/D区域232中的鳍部件220凹进。然后通过诸如CVD、VPE和/或UHV-CVD、分子束外延和/或其他合适的工艺的外延生长工艺在凹进的鳍部件220上方形成S/D部件350。S/D部件350可包括锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、磷砷化镓(GaAsP)、锑化镓(GaSb)、锑化铟(InSb)、砷化铟镓(InGaAs)、砷化铟(InAs)或其他合适的材料。
参照图1和图5，方法100进行至步骤110，在衬底210上方沉积第一介电层410，包括完全填充伪栅极堆叠件310之间的间隙。第一介电层410可包括氧化硅、氮氧化硅、氮化硅、碳化硅、氮碳化硅、低k介电材料或其他合适的介电材料。通过诸如CVD、ALD和旋涂(SOG)的合适的技术来形成第一介电层410。此后可以实施化学机械抛光(CMP)工艺以去除过量的介电层410并平坦化第一介电层410与伪栅极堆叠件310的顶面。在一个实施例中，在CMP工艺之后暴露伪栅极堆叠件310的顶面。
参照图1和图6，方法100进行至步骤112，在第一介电层410和伪栅极堆叠件310上方形成图案化的硬掩模(HM)510以限定第一区域520和第二区域530。图案化的HM 510覆盖第一区域520并保留第二区域530不被覆盖。为了简化以更好地描述方法100的目的，第一区域520和第二区域530中的伪栅极堆叠件310现在分别以参考标号310A和310B进行标记。在一个实施例中，图案化的HM 510包括通过光刻工艺形成的图案化的光刻胶层。
现在参照图1和图7，方法100进行至步骤114，去除伪栅极堆叠件310B以在第二区域530中形成伪栅极沟槽610。在本实施例中，伪栅极堆叠件310B通过包括选择性湿蚀刻或选择性干蚀刻的选择性蚀刻工艺去除并携带了间隔件320的垂直的轮廓。利用选择性蚀刻工艺，伪栅极沟槽610形成为具有自对准特性，自对准特性放松了诸如未对准、和/或光刻工艺中的重叠问题、蚀刻工艺中的沟槽轮廓控制、图案加载效应和蚀刻工艺窗口的工艺约束。
在一个实施例中，湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液、NH4OH、KOH(氢氧化钾)、HF(氢氟酸)或其他合适的溶液。相应的蚀刻工艺可通过多种蚀刻参数进行调整，诸如所使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻剂流速和/或其他合适的参数。干蚀刻工艺包括使用基于氯的化学剂的偏置等离子体蚀刻工艺。其他干蚀刻剂气体包括CF4、NF3、SF6和He。也可使用如DRIE(深反应离子蚀刻)的这种机制各向异性地实施干蚀刻。
在伪栅极沟槽610中，暴露了鳍部件220的相应的部分。为了简化以更好地描述方法100的目的，鳍部件220的第一暴露部分以参考标号220A进行标记。
参照图1和图8A至图8B，方法100进行至步骤116，去除暴露的鳍部件220A以在第一伪栅极沟槽610中形成鳍切口620。因此，将鳍部件220划分为称作鳍部件220B的一个以上的子部分，并且这些子部分通过鳍切口620间隔开。鳍切口620形成为具有垂直的轮廓。在一个实施例中，鳍切口620以深度d延伸至衬底210。在本实施例中，通过选择性蚀刻工艺去除暴露的部分220A。该蚀刻工艺选择性地去除暴露部分220A但基本不蚀刻第二区域530中的间隔件320和介电层410。因此，鳍切口620形成为具有自对准特性，自对准特性放松了鳍切口形成工艺的约束，自对准特性放松了诸如未对准、光刻工艺中的重叠问题、蚀刻轮廓控制和图案加载效应的工艺约束。同样由于选择性蚀刻特性，改进了蚀刻工艺窗口。在图案化的HM 510是光刻胶图案的一个实例中，此后通过湿剥离或等离子体灰化来去除图案化的HM 510。
参照图1和图9A至图9B，方法100进行至步骤118，在包括鳍切口620的伪栅极沟槽610中形成隔离部件715。隔离部件715将两个邻近的鳍部件220B彼此隔离。通过用第二介电层710填充伪栅极沟槽610和鳍切口620来形成隔离部件715。因此，隔离部件715的底部嵌入在衬底210中并物理接触衬底210。第二介电层710可包括氧化硅、氮氧化硅、氮化硅、碳化硅、氮碳化硅、低k介电材料和/或其他合适的介电材料。可通过诸如CVD、ALD或旋转涂覆的合适的技术形成第二介电层710。第二介电层710携带伪栅极沟槽610和鳍切口620的垂直轮廓。此后可实施CMP工艺来去除过量的第二介电层710并平坦化第二介电层710与伪栅极堆叠件310的顶面。
参照图1和图10，方法100进行至步骤120，去除伪栅极堆叠件310A以在第一区域520中形成栅极沟槽810。以在许多方面与以上关联图7所讨论的伪栅极堆叠件310B的去除类似的方式来去除伪栅极堆叠件310A。在本实施例中，通过选择性蚀刻工艺去除伪栅极堆叠件310A而不使用图案化的硬掩模或称为毯式蚀刻(blank etch)，选择性蚀刻工艺提供了非常简单的工艺。该选择性蚀刻工艺可包括选择性湿蚀刻或选择性干蚀刻。该蚀刻工艺选择性地去除伪栅极堆叠件310A但基本不蚀刻间隔件320、第一介电层410和第二介电层710。相应的鳍部件220B暴露在栅极沟槽810中。
参照图1和图11A至图11C，方法100进行至步骤122，在衬底210上方形成包裹鳍部件220B上方的HK/MG 910。在此图11B是沿着线B-B的截面图，且图11C为沿着线C-C的截面图。HK/MG 910可包括栅极介电层和设置在栅极介电层上方的栅电极且栅电极包括金属、金属合金或金属硅化物。HK/MG 910的形成包括形成各个栅极材料的沉积以及去除过量的栅极材料并且平坦化FinFET器件200的顶面的CMP工艺。
再次参照图11B至图11C，在一个实施例中，栅极介电层912包括通过诸如原子层沉积(ALD)、CVD、热氧化或臭氧氧化的合适的方法沉积的界面层(IL)。该IL包括氧化物、HfSiO和氮氧化物。通过合适的技术在IL上沉积HK介电层，诸如ALD、CVD、金属有机CVD(MOCVD)、物理汽相沉积(PVD)、其他合适的技术或它们的组合。该HK介电层可包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适的材料。
栅极介电层912包裹栅极区域中的鳍部件220B上方，其中栅极沟道将在操作FinFET器件200期间形成。因此，两个邻近的栅极沟道(在两个邻近的鳍部件220B上方形成)通过隔离部件715彼此隔离开。
金属栅极(MG)电极914可包括单层结构或可选的多层结构，诸如具有提高器件性能的功函数的金属层(功函金属层)、衬垫层、湿润层、粘附层以及金属导电层、金属合金导电层或金属硅化物导电层的各个组合。MG电极914可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、任何合适的材料或它们的组合。可通过ALD、PVD、CVD或其他合适的工艺来形成MG电极914。MG电极914可独立地形成以用于具有不同金属层的N-FET和P-FFET。可实施CMP工艺以去除过量的MG电极914。
在方法100之前、期间和之后提供额外的步骤，且对于该方法的其他实施例可以替代或消除所描述的步骤中的一些。
图12为用于制造FinFET器件2000另一示例性方法1000的流程图。该方法的前五个步骤1002、1004、1006、1008和1010分别类似于以上在方法100的步骤102、104、106、108和110中所讨论的那些。因此，以上参照步骤102、104、106、108和110的讨论分别适用于步骤1002、1004、1006、1008和1010。本发明在各个实施例中重复参考标号和/或字符。这种重复是为了简单和清楚的目的，从而使得重复的参照标号和/或字符在各个实施例中表示类似的部件，除非另外声明。
参照图12和图13，方法1000进行至步骤1012，去除伪栅极堆叠件310以在衬底210上方形成伪栅极沟槽610。在本实施例中，通过选择性蚀刻工艺去除伪栅极堆叠件310，而非使用图案化的硬掩模或称作毯式蚀刻，选择性蚀刻工艺提供非常简单的工艺。去除伪栅极堆叠件310的蚀刻工艺在许多方面类似于以上在方法100的步骤112中所讨论的那些。鳍部件220暴露在伪栅极沟槽610中。
参照图11和图14，方法1000进行至步骤1014，形成图案化的HM 5100以限定第一区域520和第二区域530。图案化的HM 5100覆盖第一区域520并保留第二区域530未被覆盖。以在许多方面与以上在方法100的步骤112中所讨论的图案化的HM 510相类似地形成图案化的HM 5100。鳍部件220A暴露在第二区域530中的伪栅极沟槽610中。
参照图11和图15，方法1000进行至步骤1016，去除鳍部件220A以形成鳍切口610同时用图案化的HM 5100覆盖第一区域520。以在许多方面与以上在方法100的步骤116中所讨论的那些类似地形成鳍切口610。在图案化的HM 5100为光刻胶图案的一个实例中，此后通过湿剥离或等离子体灰化来去除图案化的HM 5100。与在步骤116中所提到的相同，通过形成鳍切口620，两个邻近的鳍部件220B彼此间隔开。
参照图11和图16A至图16C，方法1000进行至步骤1018，在第一区域520中形成HK/GM 910，HK/GM 910包裹鳍部件220B、伪栅极沟槽610中的HK/金属部件920、以及鳍切口620的上方。以在许多方面与以上在方法100的步骤122中所讨论的那些类似地形成HK/MG 910和HK/金属部件920。在本实施例中，HK/金属部件920将两个邻近的鳍部件220B彼此间隔开。通过用栅极介电层912和栅电极914填充在伪栅极沟槽610和鳍切口620中来形成HK/金属部件920。因此，HK/金属部件920的底部嵌入在衬底210中并物理接触衬底210。
在方法1000之前、期间和之后可以提供额外的步骤，且对于该方法的其他实施例可以替代或消除所描述的步骤中的一些。
FinFET器件200和2000经历进一步的CMOS或MOS技术处理以形成各个部件和区域。例如，FinFET器件200和2000可包括在衬底210上方的各个接触件/通孔/衬垫和多层互连部件(例如，金属层和层间电介质)。作为实例，多层互连件包括诸如传统通孔或接触件的垂直互连件和诸如金属线的水平互连件。各个互连部件可采用包括铜、钨和/或硅的各个导电材料。在一个实例中，使用镶嵌和/或双镶嵌工艺以形成与铜相关的多层互连结构。
基于以上所述，本发明提供了一种用于制造FinFET器件的方法。该方法采用形成具有自对准特性的鳍切口，该自对准特性放松了工艺约束、改善了工艺窗口和工艺控制并简化了工艺。
本发明提供了制造FinFET器件的许多不同的实施例，这些实施例提供了优于现有方法的一个或多个改进。在一个实施例中，用于制造FinFET器件的方法包括在鳍部件的不同部分上方形成第一栅极堆叠件和第二栅极堆叠件，鳍部件形成在衬底上，在第一栅极堆叠件和第二栅极堆叠件之间的间隙中形成第一介电层，去除第一栅极堆叠件以形成第一栅极沟槽，因此第一栅极沟槽暴露鳍部件的部分。该方法也包括去除鳍部件的暴露部分并在第一栅极沟槽中形成隔离部件。
在另一实施例中，一种用于制造FinFET器件的方法包括在鳍部件的不同部分上方形成第一栅极堆叠件，鳍部件形成在衬底上，沿着第一栅极堆叠件的侧壁形成间隔件，用介电层填充两个邻近的第一栅极堆叠件之间的间隙，去除第一栅极堆叠件以形成栅极沟槽，其中，鳍部件的相应的部分暴露在栅极沟槽中，去除第一区域中的鳍部件的暴露部分同时保留第二区域中的鳍部件的暴露部分，在第二区域中的鳍部件的暴露部分上方形成第二栅极堆叠件，并同时在第一区域中的栅极沟槽中形成栅极堆叠部件。
本发明也提供了FinFET器件的实施例。该器件包括设置在衬底上方的鳍部件的第一部分和鳍部件的第二部分。第一部分沿着在第一方向上的线与第二部分对准。该器件也包括将鳍部件的第一部分和第二部分隔离开的隔离部件，从而使得隔离部件的底面嵌入在衬底中。该器件也包括包裹第一鳍部件的部分上方和第二鳍部件的部分上方的高k/金属栅极(HK/MG)。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以很容易地使用本发明作为基础来设计或更改用于实现与本文所介绍实施例相同的目的和/或实现相同优点的其他处理和结构。本领域技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以进行多种变化、替换以及改变。

Claims (10)

1.一种方法，包括：
在鳍部件的不同部分上方形成第一栅极堆叠件和第二栅极堆叠件，所述鳍部件形成在衬底上；
在所述第一栅极堆叠件和所述第二栅极堆叠件之间的间隙中形成第一介电层；
去除所述第一栅极堆叠件以形成第一栅极沟槽，其中，所述第一栅极沟槽暴露所述鳍部件的部分；
去除所述鳍部件的暴露部分；以及
在所述第一栅极沟槽中形成隔离部件。
2.根据权利要求1所述的方法，其中，在去除所述鳍部件的所述暴露部分之后，所述鳍部件具有与第二部分间隔开的第一部分。
3.根据权利要求1所述的方法，其中，去除所述第一栅极堆叠件包括：
用图案化的硬掩模覆盖所述第二栅极堆叠件。
4.根据权利要求1所述的方法，其中，通过不蚀刻所述第一介电层的选择性蚀刻来去除所述第一栅极堆叠件。
5.根据权利要求1所述的方法，其中，通过不蚀刻所述第一介电层的选择性蚀刻来去除所述鳍部件的所述暴露部分。
6.根据权利要求1所述的方法，还包括：
在形成所述第一栅极堆叠件之后，沿着所述第一栅极堆叠件的侧壁形成间隔件，其中，通过不蚀刻所述间隔件的选择性蚀刻来去除所述第一栅极堆叠件，其中，通过不蚀刻所述间隔件的所述选择性蚀刻来去除所述鳍结构的所述暴露部分。
7.根据权利要求1所述的方法，其中，形成所述隔离部件包括：
用第二介电层填充所述第一栅极沟槽和鳍切口；以及
应用化学机械抛光(CMP)以去除过量的所述第二介电层。
8.根据权利要求1所述的方法，还包括：
在用所述第一介电层填充两个邻近的所述第一栅极堆叠件之间的间隙之后，应用CMP以去除过量的第一介电层并暴露所述第一栅极堆叠件的顶面。
9.一种用于制造鳍式场效应晶体管(FinFET)器件的方法，所述方法包括：
在鳍部件的不同部分上方形成第一栅极堆叠件，所述鳍部件形成在衬底上；
沿着所述第一栅极堆叠件的侧壁形成间隔件；
用介电层填充两个邻近的所述第一栅极堆叠件之间的间隙；
去除所述第一栅极堆叠件以形成栅极沟槽，其中，所述鳍部件的相应的部分暴露在所述栅极沟槽中；
去除第一区域中的所述鳍部件的所述暴露部分，同时保留第二区域中的所述鳍部件的所述暴露部分；
在所述第二区域中的所述鳍部件的所述暴露部分上方形成第二栅极堆叠件；以及
同时在所述第一区域中的所述栅极沟槽中形成栅极堆叠部件。
10.一种器件，包括：
鳍部件的第一部分和所述鳍部件的第二部分，设置在衬底上方，其中所述第一部分沿着在第一方向上的线与所述第二部分对准；
隔离部件，将所述鳍部件的所述第一部分和所述第二部分隔离开，从而使得所述隔离部件的底面嵌入在所述衬底中；以及
高k/金属栅极(HK/MG)，包裹在所述鳍部件的第一部分和所述鳍部件的第二部分上方。
CN201510226190.3A 2014-09-30 2015-05-06 制造finfet器件的方法 Active CN106206308B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/502,550 2014-09-30
US14/502,550 US9245883B1 (en) 2014-09-30 2014-09-30 Method of making a FinFET device

Publications (2)

Publication Number Publication Date
CN106206308A true CN106206308A (zh) 2016-12-07
CN106206308B CN106206308B (zh) 2019-12-10

Family

ID=55086236

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510226190.3A Active CN106206308B (zh) 2014-09-30 2015-05-06 制造finfet器件的方法

Country Status (4)

Country Link
US (3) US9245883B1 (zh)
KR (1) KR101770458B1 (zh)
CN (1) CN106206308B (zh)
TW (1) TWI579904B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158864A (zh) * 2014-10-17 2016-11-23 台湾积体电路制造股份有限公司 用于FinFET隔离的方法和结构
CN108228943A (zh) * 2016-12-21 2018-06-29 中国科学院微电子研究所 一种FinFET器件的CMP工艺建模方法
WO2018193342A1 (en) * 2017-04-17 2018-10-25 International Business Machines Corporation Vertical fet with reduced parasitic capacitance
CN109841618A (zh) * 2017-11-29 2019-06-04 台湾积体电路制造股份有限公司 半导体结构切割工艺和由此形成的结构
CN110176431A (zh) * 2018-02-20 2019-08-27 格芯公司 进行用于finfet半导体装置的鳍片切口蚀刻程序的方法
CN110648919A (zh) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 带有凹口的栅极结构制造

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9805991B2 (en) * 2015-08-20 2017-10-31 International Business Machines Corporation Strained finFET device fabrication
US9536981B1 (en) * 2015-09-29 2017-01-03 International Business Machines Corporation Field effect transistor device spacers
US20170140992A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9761450B1 (en) 2016-09-26 2017-09-12 International Business Machines Corporation Forming a fin cut in a hardmask
CN106409913B (zh) * 2016-11-15 2019-04-09 中国科学院微电子研究所 具有连续侧墙的半导体设置及其制造方法
CN106449641B (zh) * 2016-11-15 2019-04-12 中国科学院微电子研究所 具有连续侧墙的半导体设置及其制造方法
US10460995B2 (en) 2016-11-29 2019-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a FinFET device
US10056481B2 (en) * 2017-01-13 2018-08-21 Globalfoundries Inc. Semiconductor device structure
US10903336B2 (en) 2017-11-28 2021-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US10867833B2 (en) 2017-11-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Buried metal for FinFET device and method
DE102018128925B4 (de) 2017-11-30 2024-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur Herstellung einer Halbleitervorrichtung und Halbleitervorrichtung
US11217582B2 (en) 2018-03-30 2022-01-04 Intel Corporation Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
US10586736B2 (en) 2018-06-11 2020-03-10 Globalfoundries Inc. Hybrid fin cut with improved fin profiles
KR102552696B1 (ko) * 2018-07-19 2023-07-05 삼성전자주식회사 반도체 장치
KR102647231B1 (ko) * 2018-08-02 2024-03-13 삼성전자주식회사 반도체 소자 및 이의 제조방법
US10797049B2 (en) 2018-10-25 2020-10-06 Globalfoundries Inc. FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same
US10930734B2 (en) 2018-10-30 2021-02-23 International Business Machines Corporation Nanosheet FET bottom isolation
US10741401B1 (en) 2019-02-09 2020-08-11 International Business Machines Corporation Self-aligned semiconductor gate cut
US11515403B2 (en) 2019-11-27 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11532479B2 (en) 2020-04-01 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cut metal gate refill with void

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201427010A (zh) * 2012-10-15 2014-07-01 Marvell World Trade Ltd 形成於半導體基板之鰭片特徵部上之電晶體的隔離組件
CN103943499A (zh) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8426923B2 (en) 2009-12-02 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate semiconductor device and method
US8487378B2 (en) 2011-01-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Non-uniform channel junction-less transistor
US8685808B2 (en) 2011-09-28 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device fabrication method
US8887106B2 (en) 2011-12-28 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US8753970B2 (en) * 2012-09-12 2014-06-17 Globalfoundries Inc. Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
TWI543268B (zh) * 2012-10-01 2016-07-21 聯華電子股份有限公司 電晶體的結構及其製作方法
US8826213B1 (en) 2013-03-11 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Parasitic capacitance extraction for FinFETs
US8943455B2 (en) 2013-03-12 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for layout verification for polysilicon cell edge structures in FinFET standard cells
US9064959B2 (en) 2013-03-13 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for forming a CMOS device
US20140315371A1 (en) * 2013-04-17 2014-10-23 International Business Machines Corporation Methods of forming isolation regions for bulk finfet semiconductor devices
US9034748B2 (en) * 2013-09-04 2015-05-19 International Business Machines Corporation Process variability tolerant hard mask for replacement metal gate finFET devices
US20150162438A1 (en) * 2013-12-11 2015-06-11 International Business Machines Corporation Memory device employing an inverted u-shaped floating gate
US9305930B2 (en) * 2013-12-11 2016-04-05 Globalfoundries Inc. Finfet crosspoint flash memory
US9064890B1 (en) * 2014-03-24 2015-06-23 Globalfoundries Inc. Methods of forming isolation material on FinFET semiconductor devices and the resulting devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201427010A (zh) * 2012-10-15 2014-07-01 Marvell World Trade Ltd 形成於半導體基板之鰭片特徵部上之電晶體的隔離組件
CN103943499A (zh) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158864B (zh) * 2014-10-17 2019-06-14 台湾积体电路制造股份有限公司 用于FinFET隔离的方法和结构
CN106158864A (zh) * 2014-10-17 2016-11-23 台湾积体电路制造股份有限公司 用于FinFET隔离的方法和结构
CN108228943A (zh) * 2016-12-21 2018-06-29 中国科学院微电子研究所 一种FinFET器件的CMP工艺建模方法
GB2577185B (en) * 2017-04-17 2020-11-04 Ibm Vertical FET with reduced parasitic capacitance
US10283504B2 (en) 2017-04-17 2019-05-07 International Business Machines Corporation Vertical FET with reduced parasitic capacitance
GB2577185A (en) * 2017-04-17 2020-03-18 Ibm Vertical FET with reduced parasitic capacitance
WO2018193342A1 (en) * 2017-04-17 2018-10-25 International Business Machines Corporation Vertical fet with reduced parasitic capacitance
CN109841618A (zh) * 2017-11-29 2019-06-04 台湾积体电路制造股份有限公司 半导体结构切割工艺和由此形成的结构
US11114549B2 (en) 2017-11-29 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure cutting process and structures formed thereby
CN109841618B (zh) * 2017-11-29 2022-04-01 台湾积体电路制造股份有限公司 半导体结构切割工艺和由此形成的结构
CN110176431A (zh) * 2018-02-20 2019-08-27 格芯公司 进行用于finfet半导体装置的鳍片切口蚀刻程序的方法
CN110176431B (zh) * 2018-02-20 2023-08-22 格芯(美国)集成电路科技有限公司 进行用于finfet半导体装置的鳍片切口蚀刻程序的方法
CN110648919A (zh) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 带有凹口的栅极结构制造
CN110648919B (zh) * 2018-06-27 2022-10-18 台湾积体电路制造股份有限公司 带有凹口的栅极结构制造

Also Published As

Publication number Publication date
TW201626444A (zh) 2016-07-16
CN106206308B (zh) 2019-12-10
US10037993B2 (en) 2018-07-31
KR101770458B1 (ko) 2017-08-22
US9496372B2 (en) 2016-11-15
TWI579904B (zh) 2017-04-21
US20160155824A1 (en) 2016-06-02
US9245883B1 (en) 2016-01-26
KR20160038673A (ko) 2016-04-07
US20170062422A1 (en) 2017-03-02

Similar Documents

Publication Publication Date Title
CN106206308A (zh) 制造finfet器件的方法
US11670717B2 (en) Structure of S/D contact and method of making same
US9640636B1 (en) Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device
US10347751B2 (en) Self-aligned epitaxy layer
CN103928515B (zh) 半导体器件及其制造方法
US8786019B2 (en) CMOS FinFET device
CN103578954B (zh) 具有金属栅极的半导体集成电路
CN106711044A (zh) 切割金属栅极的方法
CN104681615A (zh) 用于具有掩埋SiGe氧化物的FinFET器件的结构和方法
CN105428394B (zh) 鳍部件的结构及其制造方法
US20240088145A1 (en) Integrated circuits with gate cut features
CN102074506A (zh) 鳍式场效应晶体管元件的制作方法
US11398482B2 (en) Semiconductor device and method
CN105280699A (zh) 源极/漏极结构及其形成方法
US11038059B2 (en) Semiconductor device and method of forming the same
CN105280641B (zh) 用于集成电路的结构和方法
TWI685025B (zh) 製造半導體裝置的方法及半導體裝置
CN107039508A (zh) 半导体装置
CN103579004B (zh) FinFET及其制造方法
US10784359B2 (en) Non-conformal oxide liner and manufacturing methods thereof
CN105280558A (zh) 用于FinFET器件的结构和方法
US10847634B2 (en) Field effect transistor and method of forming the same
US20240021619A1 (en) Finfet device and method
US20230261048A1 (en) Semiconductor device and method of manufacture
CN103855027A (zh) FinFET及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant