CN105280558A - 用于FinFET器件的结构和方法 - Google Patents
用于FinFET器件的结构和方法 Download PDFInfo
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- CN105280558A CN105280558A CN201510288647.3A CN201510288647A CN105280558A CN 105280558 A CN105280558 A CN 105280558A CN 201510288647 A CN201510288647 A CN 201510288647A CN 105280558 A CN105280558 A CN 105280558A
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Abstract
一种用于制造鳍式场效应晶体管(FinFET)器件的方法包括在衬底上方形成第一鳍结构,在第一鳍结构上方形成介电层,在介电层内形成具有垂直轮廓的沟槽,在沟槽的侧壁和底部上方共形地沉积第一半导体材料层,在第一半导体材料层上方沉积第二半导体材料层以填充剩余的沟槽,使介电层凹进以横向暴露第一半导体材料层以及蚀刻暴露的第一半导体材料层以露出第二半导体材料层。本发明的实施例还涉及用于FinFET器件的结构。
Description
技术领域
本发明的实施例涉及集成电路器件,更具体地,涉及用于FinFET器件的结构和方法。
背景技术
半导体集成电路(IC)工业已经经历了指数式增长。IC材料和设计中的技术进步已经产生了数代的IC,其中每代IC都具有比上一代IC更小和更复杂的电路。在IC发展过程中,功能密度(即,每一芯片面积上互连器件的数量)通常已经增加而几何尺寸(即,使用制造工艺可以制造的最小部件(或线))却已减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本而提供益处。
这种按比例缩小也增大了加工和制造IC的复杂度,并且为了继续实现这些进步,需要IC加工和制造中的类似发展。例如,已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管以代替平面晶体管。虽然现有的FinFET器件及其制造方法通常已经能够满足它们的预期目的,但是它们不是在所有方面都已完全令人满意。期望在该领域中具有改进。
发明内容
本发明的实施例提供了一种用于制造鳍式场效应晶体管(FinFET)器件的方法,所述方法包括:在衬底上方形成第一鳍结构;在所述第一鳍结构上方形成介电层;在所述介电层内形成沟槽,其中,在所述沟槽的底部中暴露所述第一鳍结构;在所述沟槽内沉积第一半导体材料层;在所述沟槽内的所述第一半导体材料层上方沉积第二半导体材料层;使所述介电层凹进以横向暴露所述第一半导体材料层;以及蚀刻暴露的第一半导体材料层以露出所述第二半导体材料层,其中,位于所述第二半导体材料层下方的所述第一半导体材料层的至少一部分保持完整。
根据本发明的另一实施例,提供了一种用于制造鳍式场效应晶体管(FinFET)器件的方法,所述方法包括:在衬底上方形成由介电层围绕的第一鳍结构;使所述第一鳍结构凹进以在所述介电层中形成沟槽;扩大所述沟槽以具有垂直的侧壁轮廓;在所述沟槽的侧壁和底部上方共形地沉积第一半导体材料层;从剩余的沟槽的底部外延生长第二半导体材料层;使所述介电层凹进以横向暴露所述第一半导体材料层;去除沿着所述第二半导体材料层的侧壁的暴露的第一半导体材料层,但是基本上不蚀刻所述第二半导体材料层,其中,位于所述第二半导体材料层下方的所述第一半导体材料层的至少一部分保持完整;以及在所述衬底上方形成高k/金属栅极,所述高k/金属栅极包裹在所述第二半导体材料层上方和位于所述第二半导体材料层下方的剩余的第一半导体材料层上方。
根据本发明的又一实施例,提供了一种半导体器件,包括:第一鳍结构,设置在衬底上方;第二鳍结构,设置在所述第一鳍结构上方,所述第二鳍结构包括:第一半导体材料层,作为所述第二鳍结构的下部;和第二半导体材料层,作为所述第二鳍结构的上部并且具有垂直的侧壁轮廓;以及高k/金属栅极(HK/MG),设置在所述衬底上方并且包裹在所述第二鳍结构上方。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的用于制造FinFET器件的示例性方法的流程图。
图2至图13是根据图1的方法构建的处于制造阶段的示例性FinFET器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作相应的解释。
本发明涉及但不以其他方式限制于FinFET器件。例如,FinFET器件可以是包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。以下公开内容将继续以FinFET实例来说明本发明的各个实施例。然而,应该理解,除了权利要求中特别声明,本申请不应限制于特定类型的器件。
图1是根据本发明的各方面的用于制造FinFET器件200的方法100的流程图。图2至图13是根据图1的方法100构建的处于制造阶段的FinFET器件200的截面图。参照图1至图9共同地描述FinFET器件200。应该理解,在方法100之前、期间和之后可以提供额外的步骤,并且对于方法的其他实施例,可以替代或消除描述的一些步骤。
参照图1和图2,方法100开始于步骤102,在衬底210中形成第一鳍结构220。衬底210包括硅。在另一实施例中,衬底可以包括锗、硅锗、砷化镓或其他适当的半导体材料。可选地并且对于一些实施例,衬底210可以包括外延层。例如,衬底210可以具有位于块状半导体上面的外延层。此外,衬底210可以被应变以用于性能增强。例如,外延层可以包括与块状半导体的那些材料不同的半导体材料,诸如通过包括选择性外延生长(SEG)的工艺形成的位于块状硅上面的硅锗层或者位于块状硅锗上面的硅层。此外,衬底210可以包括诸如掩埋介电层的绝缘体上半导体(SOI)结构。同样可选地,衬底210可以包括诸如通过称为注氧隔离(SIMOX)技术、晶圆接合、SEG的方法或其他适当的方法形成的诸如埋氧(BOX)层的掩埋介电层。实际上,各个实施例可以包括各种衬底结构和材料的任何结构和材料。
可以通过诸如沉积、光刻和蚀刻的一个或多个工序形成第一鳍结构220。在一个实施例中,在衬底210上方形成硬掩模(HM)层。HM层可以包括氮化硅、氧化硅、碳化硅、氧化钛、氮化钛、氧化钽、氮化钽或任何合适的材料。然后在HM层上方形成图案化的光刻胶层以限定第一鳍结构220。通常地,图案化工艺可以包括光刻胶涂布(例如,旋涂)、曝光、显影光刻胶、其他合适的工艺或它们的组合。可选地,由诸如无掩模光刻、电子束写入、直接写入和/或离子束写入的其他适当的方法实施或代替光刻曝光工艺。然后通过图案化的光刻胶层蚀刻HM层以形成图案化的HM层215。然后通过图案化的HM层蚀刻衬底210以形成第一鳍结构220。
可以通过包括干蚀刻、湿蚀刻或它们的组合的各种方法蚀刻衬底210。在一个实施例中,湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液或其他合适的溶液。可以利用诸如所使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻剂流量和/或其他合适的参数的各种蚀刻参数调节相应的蚀刻工艺。干蚀刻工艺可以包括使用氯基化学物质的偏置等离子体蚀刻工艺。其他干蚀刻剂气体包括CF4、NF3、SF6和He。也可以使用诸如DRIE(深反应离子蚀刻)的机制各向异性地实施干蚀刻。
也参照图1和图2,方法100进行至步骤104,在衬底210上方沉积介电层240,包括填充每个第一鳍结构220之间的空间。在一个实施例中,位于每个第一鳍结构220之间的介电层240用作隔离区以使衬底210中的各个器件区分隔开。介电层240可以包括氧化硅、氮化硅、氮氧化物、具有比热氧化硅的介电常数更低的介电常数(k)的介电材料(因此称为低k介电材料层)、或其他合适的介电材料层。介电层240可以包括单层或多层。可以通过化学汽相沉积(CVD)、原子层沉积(ALD)或旋涂沉积介电层240。此外,可以实施化学机械抛光(CMP)工艺以平坦化介电层240的顶面(并且也去除图案化的HM层)。
参照图1和图3,方法100进行至步骤106,使第一鳍结构220凹进以在介电层240中形成沟槽250。在一个实施例中,首先实施化学机械抛光(CMP)工艺以去除过量的介电层240并且暴露第一鳍结构220的顶面。然后通过基本上不蚀刻介电层240的选择性蚀刻使第一鳍结构220凹进。凹进工艺可以包括选择性湿蚀刻、选择性干蚀刻或它们的组合。在一个实施例中,选择性湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液或其他合适的溶液。干蚀刻工艺可以包括使用诸如Cl2、CHCl3、CCl4和/或BCl3的氯基化学物质的偏置等离子体蚀刻工艺。沟槽250形成为具有作为其底部的凹进的第一鳍结构220和作为其侧壁的介电层240。换句话说,凹进的第一鳍结构220暴露于沟槽250中。
参照图1和图4,方法100进行至步骤108,扩大沟槽250以形成扩大的沟槽260。在本实施例中,扩大的沟槽260具有基本上垂直的轮廓。扩大的沟槽260具有第一宽度w1。在一个实施例中,通过穿过图案化的光刻胶层蚀刻介电层240形成扩大的沟槽260。蚀刻工艺包括各向异性蚀刻。各向异性电介质蚀刻可以包括使用诸如CF4、SF6、CH2F2、CHF3和/或C2F6的氟基化学物质的等离子体干蚀刻工艺。各向异性电介质蚀刻选择性地去除介电层240,但是基本上不蚀刻凹进的第一鳍结构220。
参照图1和图5,方法100进行至步骤110,沿着扩大的沟槽260的侧壁和底部共形地沉积第一半导体材料层310。第一半导体材料层310可以包括诸如锗(Ge)或硅(Si)的元素半导体材料;诸如砷化镓(GaAs)、砷化铝镓(AlGaAs)的化合物半导体材料;或者诸如硅锗(SiGe)、磷砷化镓(GaAsP)的半导体合金。可以通过包括CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其他合适的工艺的外延工艺沉积第一半导体材料层310。在本实施例中,第一半导体材料层310包括外延Si层。可以在外延工艺期间原位掺杂第一半导体材料层310。例如,外延生长的半导体材料层310可以掺杂有硼。对于另一实例,外延生长的Si层310可以掺杂有碳、或磷、或碳和磷。在另一实施例中,未原位掺杂第一半导体层310,实施注入工艺(即,结注入工艺)。
在本实施例中,半导体材料层310共形地覆盖扩大的沟槽260的具有第一厚度t1的垂直侧壁和扩大的沟槽260的具有第二厚度t2的底部。在一个实施例中,第二厚度t2薄于第一厚度t1。在另一实施例中,第二厚度t2可以与第一厚度t1基本上相同。在沉积第一半导体材料层310之后,扩大的沟槽260的第一宽度w1减小至第二宽度w2,其中w2=w1-(2×t1)。通过选择第一宽度w1和厚度t,第二宽度w2是目标的鳍宽度,这将在之后描述。
参照图1和图6,方法100进行至步骤112,从剩余的扩大的沟槽260的底部外延生长第二半导体层320。第二半导体层320可以包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP或其他合适的材料。在本实施例中,第二半导体层320包括SiGe。可以通过包括CVD、分子束外延和/或其他合适的工艺的外延工艺外延生长第二半导体材料层320。外延生长的第二半导体材料层320完全填充剩余的扩大的沟槽260。然后实施另一CMP工艺以去除过量的第一和第二半导体材料层310和320,并且平坦化第一和第二半导体材料层310和320的顶面与介电层的顶面。
在步骤112之后,方法100具有两条路径,分别由后缀“A”和“B”标示。下面单独地讨论这两条路径。
参照图1和图7,方法100沿着路径A进行至步骤114A,使介电层240凹进以横向暴露第一半导体材料层310。通过诸如选择性湿蚀刻、选择性干蚀刻或它们的组合的适当的蚀刻工艺使介电层240凹进。该蚀刻选择性地去除介电层240,但是基本上不蚀刻第一和第二半导体材料层310和320。在本实施例中,控制凹进工艺以使凹进的介电材料层240的顶面240a低于半导体材料层310的底面310a。
参照图1和图8,方法100进行至步骤116A,蚀刻暴露的第一半导体材料层310。在本实施例中,通过选择性蚀刻来蚀刻暴露的第一半导体材料层310,从而使得蚀刻工艺基本上不蚀刻第二半导体材料层320。因此,第二半导体材料层320的垂直侧壁轮廓保持完整。在一个实施例中,通过相对于SiGe层320具有高选择性的NH4OH:H2O2的湿蚀刻溶液蚀刻Si层310。在另一实施例中,通过TMAH的湿蚀刻溶液蚀刻Si层310。控制蚀刻工艺,使得完全去除沿着第二半导体材料层320的侧壁的暴露的第一半导体材料层310,而使得位于第二半导体材料层320下方的第一半导体材料层310的至少一部分部分地保持完整。
在本实施例中,第二半导体材料层320与位于其下方的剩余的第一半导体材料层310组合形成第二鳍结构410。因此,第二鳍结构410具有作为其上部的第二半导体材料层320和作为其下部的第一半导体材料层310。上部的二半导体材料层320具有垂直的侧壁轮廓,而下部的第一半导体材料层310具有非垂直的侧壁轮廓,诸如下部的第一半导体材料层310在其底部处具有较宽的宽度。本文中,下部的第一半导体材料层310的非垂直的侧壁轮廓是倾斜的和/或锥形的。上部的宽度(称为第二鳍结构410的宽度)是第二宽度w2。如先前所述,w2=w1-(2×t1)。因此,可以通过选择第一宽度w1和第一厚度t1获得目标的小鳍结构宽度。下部的宽度等于或小于第二宽度w2。
参照图1和图9,可选地,在完成步骤112之后,方法100沿着路径B进行至步骤114B(而不是114A),使介电层240凹进以横向暴露第一半导体材料层310。该凹进在许多方面类似于以上在步骤114A中讨论的那些。但是控制凹进深度以使凹进的介电材料层240的顶面240a定位于第一半导体材料层310的底面310a之上。本文中,凹进的介电材料层240的顶面240a处于与第一半导体材料层310的底面310a相对的第一半导体材料层310的顶面310b相同的水平面处。
参照图1和图10,方法100进行至步骤116B,蚀刻暴露的第一半导体材料层310。步骤116B在许多方面类似于步骤116A。实施选择性蚀刻工艺,并且去除沿着第二半导体材料层320的侧壁的暴露的第一半导体材料层310,而使得第二半导体材料层320保持未被蚀刻。因此,第二半导体材料层320的垂直的侧壁轮廓保持完整。而且,由于相对于第二半导体材料层320和介电层240的第一半导体材料层310的充分的选择性蚀刻,位于第二半导体材料层320下方的第一半导体材料层310的部分在凹进工艺期间保持完整。
参照图1和图11,方法100进行至步骤118B,进一步使介电层240凹进以暴露位于第二半导体材料层320下方的第一半导体材料层310的剩余部分。该凹进工艺在许多方面类似于以上在步骤114B中讨论的那些。
参照图1和图12A至图12C,方法100进行至步骤120B,修整第一半导体材料层310的剩余部分。该修整工艺在许多方面类似于以上在步骤116A中讨论的那些。在本实施例中,修整工艺是选择性蚀刻,其选择性修整第一半导体材料层310的剩余部分,但是基本上不蚀刻第二半导体材料层320。因此,第二半导体材料层320的垂直的侧壁轮廓保持完整。
如在步骤116A中所述的,第二鳍结构410形成为具有作为其上部的第二半导体材料层320和作为其下部的第一半导体材料层310。上部具有垂直的侧壁轮廓和第二宽度w2。下部具有非垂直的侧壁轮廓。通过控制修整工艺,诸如修整时间、修整工艺条件,可以实现第二鳍结构410的下部的各种形状以满足各种器件需求。如图12A所示,在一个实施例中,第二鳍结构410的下部形成为具有梯形形状,其在其底部处具有较宽的宽度。如图12B所示,在另一实施例中,由于较长的修整时间,第二鳍结构410的下部形成为具有缩颈形状,其在中间具有最窄的宽度。如图12C所示,在又另一实施例中,进一步修整第二鳍结构410的缩颈形状的下部以使第二鳍结构具有Ω形415。将在Ω形第二鳍结构410上方形成全环栅(GAA)栅极,这将在之后描述。
FinFET200也可以经受进一步的CMOS或MOS技术加工以形成诸如源极/漏极(S/D)部件和栅极堆叠件的各种部件。第二鳍结构410包括源极/漏极(S/D)区和栅极区。在S/D区中形成S/D部件,并且在第二鳍结构410的栅极区中形成栅极堆叠件。在一个实施例中,伪栅极堆叠件首先形成在衬底210上并且部分地设置在栅极区中的第二鳍结构410上方。伪栅极堆叠件将在随后的阶段中由最终的栅极堆叠件替代。具体地,在高温热工艺之后,诸如源极/漏极形成期间的用于S/D活化的热退火,伪栅极堆叠件之后将由高k介电层(HK)和金属栅电极(MG)代替。
然后在第二鳍结构410中的S/D区上方形成S/D部件。在一个实施例中,使S/D区中的第二鳍结构410的上部凹进,并且然后在凹进的第二鳍结构410上外延生长S/D部件。S/D部件包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP或其他合适的材料。也可以掺杂S/D部件,诸如在外延生长工艺期间原位掺杂S/D部件。可选地,不原位掺杂S/D部件,并且实施注入工艺(即,结注入工艺)以掺杂S/D部件。
出于示例的目的,以下描述将针对图12C的实施例。应该理解,可以对图8和图12A至图12B的实施例实施类似的工艺。
现在参照图13,在第二鳍结构410之间的衬底210上方形成层间介电(ILD)层510。ILD层510包括氧化硅、氮氧化硅、低k介电材料或其他合适的介电材料。ILD层510可以包括单层或可选地包括多层。通过诸如CVD、ALD和旋涂(SOG)的合适的技术形成ILD层510。此后可以实施CMP工艺以去除过量的ILD层510并且平坦化FinFET200的顶面。
然后伪栅极堆叠件由高k/金属栅极(HK/MG)堆叠件610代替,HK/MG堆叠件610形成在衬底210上方并且包裹在第二鳍结构410的部分上方。HK/MG堆叠件610可以包括栅极介电层和位于栅极介电层上的栅电极。在一个实施例中,栅极介电层包括具有高介电常数的介电材料层(HK介电层-在本实施例中,大于热氧化硅的介电常数),并且栅电极包括金属、金属合金或金属硅化物。HK/MG堆叠件610的形成包括沉积以形成各种栅极材料以及CMP工艺以去除过量的栅极材料并且平坦化FinFET200的顶面。
在一个实施例中,栅极介电层包括通过诸如原子层沉积(ALD)、CVD、热氧化或臭氧氧化的合适的方法沉积的界面层(IL)620。IL620可以包括氧化物、HfSiO和氮氧化物。通过诸如ALD、CVD、金属有机CVD(MOCVD)、物理汽相沉积(PVD)、其他合适的技术或它们的组合的合适的技术在IL620上沉积HK介电层630。HK介电层630可以包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适的材料。栅极介电层包裹在栅极区中的第二鳍结构410上方。
在HK介电层630上方形成金属栅(MG)电极640。MG电极640可以包括单层结构或可选地包括多层结构,诸如具有功函数以增强器件性能的金属层(功函金属层)、衬垫层、润湿层、粘合层以及金属、金属合金或金属硅化物的导电层的各种组合。MG电极可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、任何合适的材料或它们的组合。可以通过ALD、PVD、CVD或其他合适的工艺形成MG电极640。可以实施CMP工艺以去除过量的MG电极640。
随后的加工也可以在衬底210上形成各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质),接触件/通孔/线和多层互连部件配置为连接FinFET200的各种部件或结构。例如,多层互连包括诸如传统的通孔或接触件的垂直互连件和诸如金属线的水平互连件。各种互连部件可以采用包括铜、钨和/或硅化物的各种导电材料。在一个实例中,镶嵌和/或双镶嵌工艺用于形成铜相关的多层互连结构。
可以在方法100之前、期间和之后提供额外的步骤,并且对于方法的其他实施例,可以替代或消除描述的一些步骤。
基于以上所述,本发明提供了用于FinFET器件的方法和结构。该方法采用在不修整鳍结构本身的情况下形成具有非常小的宽度的鳍结构以改进鳍结构形状和临界尺寸(CD)控制。该方法也采用形成在其上部具有期望的垂直轮廓的鳍结构。该方法也采用形成鳍结构的下部的各种形状以满足各种器件需求,诸如用于全环栅器件。
本发明提供了制造FinFET器件的许多不同的实施例,这些实施例提供了优于现有技术的一个或多个改进。在一个实施例中,一种用于制造FinFET器件的方法包括在衬底上方形成第一鳍结构,在第一鳍结构上方形成介电层,在介电层内形成沟槽,其中,在沟槽的底部中暴露第一鳍结构,在沟槽内沉积第一半导体材料层,在沟槽内的第一半导体材料层上方沉积第二半导体材料层,使介电层凹进以横向暴露第一半导体材料层以及蚀刻暴露的第一半导体材料层以露出第二半导体材料层,其中,位于第二半导体材料层下方的第一半导体材料层的至少一部分保持完整。
在上述方法中,其中,在所述介电层内形成所述沟槽包括:实施化学机械抛光(CMP)以去除过量的介电层并且暴露所述第一鳍结构的顶面;使所述第一鳍结构凹进以在所述介电层中留下第一沟槽;以及扩大所述第一沟槽以形成具有垂直的侧壁轮廓的所述沟槽。
在上述方法中,其中,在所述介电层内形成所述沟槽包括:实施化学机械抛光(CMP)以去除过量的介电层并且暴露所述第一鳍结构的顶面;使所述第一鳍结构凹进以在所述介电层中留下第一沟槽;以及扩大所述第一沟槽以形成具有垂直的侧壁轮廓的所述沟槽,其中,沿着所述沟槽的侧壁的所述第一半导体材料层承载所述沟槽的所述垂直的侧壁轮廓。
在上述方法中,其中,在所述介电层内形成所述沟槽包括:实施化学机械抛光(CMP)以去除过量的介电层并且暴露所述第一鳍结构的顶面;使所述第一鳍结构凹进以在所述介电层中留下第一沟槽;以及扩大所述第一沟槽以形成具有垂直的侧壁轮廓的所述沟槽,其中,沿着所述沟槽的侧壁的所述第一半导体材料层承载所述沟槽的所述垂直的侧壁轮廓,其中,沉积在所述第一半导体材料层上方的所述第二半导体材料层承载所述垂直的侧壁轮廓。
在上述方法中,其中,通过从剩余的沟槽的底部外延生长来沉积所述第二半导体材料层。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处低于所述第一半导体材料层。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处低于所述第一半导体材料层,其中,在蚀刻暴露的第一半导体材料层期间去除位于所述沟槽的底部处的所述第一半导体材料层的外部。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处位于所述第一半导体材料层之上。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处位于所述第一半导体材料层之上,其中,所述方法还包括:去除位于所述介电层之上的所述第一半导体材料层;使所述介电层进一步凹进以暴露剩余的第一半导体材料层;以及修整暴露的剩余的第一半导体材料层的外层。
在上述方法中,其中,所述方法还包括:在所述衬底上方形成高k/金属栅极,所述高k/金属栅极包裹在所述第二半导体材料层上方以及剩余的第一半导体材料层上方。
在又另一实施例中,一种用于制造FinFET器件的方法包括用于制造鳍式场效应晶体管(FinFET)器件的方法,该方法包括在衬底上方形成由介电层围绕的第一鳍结构,使第一鳍结构凹进以在介电层中形成沟槽,扩大沟槽以具有垂直的侧壁轮廓,在沟槽的侧壁和底部上方共形地沉积第一半导体材料层,从剩余的沟槽的底部外延生长第二半导体材料层,使介电层凹进以横向暴露第一半导体材料层,去除沿着第二半导体材料层的侧壁的暴露的第一半导体材料层,但是基本上不蚀刻第二半导体材料层。位于第二半导体材料层下方的第一半导体材料层的至少一部分保持完整。该方法也包括在衬底上方形成高k/金属栅极,高k/金属栅极包裹在第二半导体材料层上方和位于第二半导体材料层下方的剩余的第一半导体材料层上方。
在上述方法中,其中,沿着所述沟槽的侧壁的所述第一半导体材料层承载所述沟槽的所述垂直的侧壁轮廓。
在上述方法中,其中,沿着所述沟槽的侧壁的所述第一半导体材料层承载所述沟槽的所述垂直的侧壁轮廓,其中,沉积在所述第一半导体材料层上方的所述第二半导体材料层承载所述垂直的侧壁轮廓。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处低于所述第一半导体材料层。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处低于所述第一半导体材料层,其中,在蚀刻暴露的第一半导体材料层期间去除位于所述沟槽的底部处的所述第一半导体材料层的外部。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处位于所述第一半导体材料层之上。
在上述方法中,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处位于所述第一半导体材料层之上,其中,所述方法还包括:去除位于所述介电层之上的所述第一半导体材料层;使所述介电层进一步凹进以暴露所述剩余的第一半导体材料层;以及修整暴露的剩余的第一半导体材料层的外层。
在另一实施例中,一种FinFET器件包括:第一鳍结构,设置在衬底上方;第二鳍结构,设置在第一鳍结构上方。第二鳍结构包括作为其下部的第一半导体材料层和作为其上部的具有垂直的侧壁轮廓的第二半导体材料层。该器件也包括设置在衬底上方并且包裹在第二鳍结构上方的高k/金属栅极(HK/MG)。
在上述半导体器件中,其中,所述第二鳍结构具有Ω形,其中,所述下部的宽度基本上短于所述上部的宽度,其中,所述HK/MG包裹在Ω形鳍结构上方。
在上述半导体器件中,其中,所述第二鳍结构具有Ω形,其中,所述下部的宽度基本上短于所述上部的宽度,其中,所述HK/MG包裹在Ω形鳍结构上方,其中,所述第一半导体材料层包括硅(Si);以及所述第二半导体材料层包括硅锗(SiGe)。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种用于制造鳍式场效应晶体管(FinFET)器件的方法,所述方法包括:
在衬底上方形成第一鳍结构;
在所述第一鳍结构上方形成介电层;
在所述介电层内形成沟槽,其中,在所述沟槽的底部中暴露所述第一鳍结构;
在所述沟槽内沉积第一半导体材料层;
在所述沟槽内的所述第一半导体材料层上方沉积第二半导体材料层;
使所述介电层凹进以横向暴露所述第一半导体材料层;以及
蚀刻暴露的第一半导体材料层以露出所述第二半导体材料层,其中,位于所述第二半导体材料层下方的所述第一半导体材料层的至少一部分保持完整。
2.根据权利要求1所述的方法,其中,在所述介电层内形成所述沟槽包括:
实施化学机械抛光(CMP)以去除过量的介电层并且暴露所述第一鳍结构的顶面;
使所述第一鳍结构凹进以在所述介电层中留下第一沟槽;以及
扩大所述第一沟槽以形成具有垂直的侧壁轮廓的所述沟槽。
3.根据权利要求2所述的方法,其中,沿着所述沟槽的侧壁的所述第一半导体材料层承载所述沟槽的所述垂直的侧壁轮廓。
4.根据权利要求3所述的方法,其中,沉积在所述第一半导体材料层上方的所述第二半导体材料层承载所述垂直的侧壁轮廓。
5.根据权利要求1所述的方法,其中,通过从剩余的沟槽的底部外延生长来沉积所述第二半导体材料层。
6.根据权利要求1所述的方法,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处低于所述第一半导体材料层。
7.根据权利要求6所述的方法,其中,在蚀刻暴露的第一半导体材料层期间去除位于所述沟槽的底部处的所述第一半导体材料层的外部。
8.根据权利要求1所述的方法,其中,使所述介电层凹进以使所述介电层的顶面在所述沟槽的底部处位于所述第一半导体材料层之上。
9.一种用于制造鳍式场效应晶体管(FinFET)器件的方法,所述方法包括:
在衬底上方形成由介电层围绕的第一鳍结构;
使所述第一鳍结构凹进以在所述介电层中形成沟槽;
扩大所述沟槽以具有垂直的侧壁轮廓;
在所述沟槽的侧壁和底部上方共形地沉积第一半导体材料层;
从剩余的沟槽的底部外延生长第二半导体材料层;
使所述介电层凹进以横向暴露所述第一半导体材料层;
去除沿着所述第二半导体材料层的侧壁的暴露的第一半导体材料层,但是基本上不蚀刻所述第二半导体材料层,其中,位于所述第二半导体材料层下方的所述第一半导体材料层的至少一部分保持完整;以及
在所述衬底上方形成高k/金属栅极,所述高k/金属栅极包裹在所述第二半导体材料层上方和位于所述第二半导体材料层下方的剩余的第一半导体材料层上方。
10.一种半导体器件,包括:
第一鳍结构,设置在衬底上方;
第二鳍结构,设置在所述第一鳍结构上方,所述第二鳍结构包括:
第一半导体材料层,作为所述第二鳍结构的下部;和
第二半导体材料层,作为所述第二鳍结构的上部并且具有垂直的侧壁轮廓;以及
高k/金属栅极(HK/MG),设置在所述衬底上方并且包裹在所述第二鳍结构上方。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111261507A (zh) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | 用于制造半导体布置的方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11121238B2 (en) * | 2018-11-29 | 2021-09-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN111834208B (zh) * | 2019-04-16 | 2024-06-04 | 中芯国际集成电路制造(上海)有限公司 | 一种金属栅极的形成方法及半导体器件 |
KR20210018573A (ko) | 2019-08-05 | 2021-02-18 | 삼성전자주식회사 | 활성 영역 및 게이트 구조물을 갖는 반도체 소자 |
US11901457B2 (en) * | 2019-12-02 | 2024-02-13 | Intel Corporation | Fin shaping and integrated circuit structures resulting therefrom |
US20230268345A1 (en) * | 2022-02-22 | 2023-08-24 | International Business Machines Corporation | Integration of stacked nanosheets and finfet |
CN115863252B (zh) * | 2023-01-29 | 2023-05-23 | 合肥晶合集成电路股份有限公司 | 一种半导体结构的制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090008705A1 (en) * | 2007-07-05 | 2009-01-08 | International Business Machines Corporation | Body-contacted finfet |
US20110193178A1 (en) * | 2010-02-09 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-Notched SiGe FinFET Formation Using Condensation |
CN103928518A (zh) * | 2013-01-14 | 2014-07-16 | 台湾积体电路制造股份有限公司 | FinFET器件及其制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8901537B2 (en) * | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
US8618556B2 (en) * | 2011-06-30 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET design and method of fabricating same |
US9318431B2 (en) * | 2011-11-04 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having a MOM capacitor and method of making same |
US9306069B2 (en) * | 2013-09-11 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure of fin field effect transistor |
US8901607B2 (en) * | 2013-01-14 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
US9318606B2 (en) * | 2013-01-14 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of fabricating same |
US9559181B2 (en) * | 2013-11-26 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device with buried sige oxide |
US8614127B1 (en) * | 2013-01-18 | 2013-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
FR3002813B1 (fr) * | 2013-03-01 | 2016-08-05 | St Microelectronics Sa | Procede de fabrication d'un transistor mos a ailette |
US9093302B2 (en) * | 2013-11-13 | 2015-07-28 | Globalfoundries Inc. | Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices |
US9472652B2 (en) * | 2013-12-20 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of semiconductor device |
US9142676B2 (en) * | 2013-12-30 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor liner of semiconductor device |
US9214553B2 (en) * | 2014-03-07 | 2015-12-15 | Globalfoundries Inc. | Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device |
US9520498B2 (en) * | 2014-03-17 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structure and method for fabricating the same |
US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
US9472446B2 (en) * | 2014-06-18 | 2016-10-18 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device with a unique gate configuration, and the resulting FinFET device |
-
2014
- 2014-06-27 US US14/318,140 patent/US9406782B2/en active Active
- 2014-12-23 KR KR1020140186815A patent/KR101706432B1/ko active IP Right Grant
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- 2015-05-29 CN CN201510288647.3A patent/CN105280558B/zh active Active
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- 2016-08-01 US US15/225,480 patent/US10269792B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090008705A1 (en) * | 2007-07-05 | 2009-01-08 | International Business Machines Corporation | Body-contacted finfet |
US20110193178A1 (en) * | 2010-02-09 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-Notched SiGe FinFET Formation Using Condensation |
CN103928518A (zh) * | 2013-01-14 | 2014-07-16 | 台湾积体电路制造股份有限公司 | FinFET器件及其制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111261507A (zh) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | 用于制造半导体布置的方法 |
CN111261507B (zh) * | 2018-11-30 | 2023-03-24 | 台湾积体电路制造股份有限公司 | 用于制造半导体布置的方法 |
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