CN104425410A - 具有纳米线的集成电路 - Google Patents

具有纳米线的集成电路 Download PDF

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CN104425410A
CN104425410A CN201310688355.XA CN201310688355A CN104425410A CN 104425410 A CN104425410 A CN 104425410A CN 201310688355 A CN201310688355 A CN 201310688355A CN 104425410 A CN104425410 A CN 104425410A
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nanowires
length
diameter
district
mos
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CN104425410B (zh
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江国诚
黄俊嘉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • B82—NANOTECHNOLOGY
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Abstract

本发明提供了集成电路（IC）。IC包括具有金属氧化物半导体（MOS）区的衬底。IC还包括第一栅极区、源极区和漏极区，以及第二栅极区、源极区和漏极区，其中第一栅极区具有第一长度，第二栅极区具有第二长度。第一纳米线组设置在第一栅极区中，第一纳米线组包括具有第一直径的纳米线，并连接至第一源极区中的部件和第一漏极区中的部件。第二纳米线组设置在第二栅极区中，第二纳米线组包括具有第二直径的纳米线，并连接至第二源极区中的部件和第二漏极区中的部件。直径为：如果第一长度大于第二长度，则第一直径小于第二直径，反之亦然。本发明还提供了具有纳米线的集成电路。

Description

具有纳米线的集成电路
技术领域
本发明涉及半导体技术领域，更具体地，涉及具有纳米线的集成电路。
背景技术
集成电路（IC）工业经历了指数增长。IC材料和设计方面的技术进步已经产生了数代IC，其中每一代IC比前一代IC具有更小和更复杂的电路。在IC演变的过程中，功能密度（即，每芯片面积上互连器件的数目）通常增加，而几何尺寸（即，使用制造工艺可以制成的最小部件（或线））却已减小。这种按比例缩小工艺通常通过增加生产效率和降低相关成本而带来益处。
这种按比例缩小还提高了处理和制造IC的复杂性，并且为了实现这些进步，需要IC处理和制造方面的类似发展。例如，已引入三维晶体管，诸如具有纳米线的半导体器件，以替换平面晶体管。期望在此领域中得到改进。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种集成电路，包括：
衬底，具有金属氧化物半导体（MOS）区；
位于所述MOS区中的第一器件的第一栅极区、第一源极区和第一漏极区，其中，所述第一栅极区具有第一长度；
第一纳米线组，设置在所述第一栅极区中，所述第一纳米线组包括具有第一直径的纳米线，并连接至所述第一源极区中的第一部件和所述第一漏极区中的所述第一部件；
位于所述MOS区中的第二器件的第二栅极区、第二源极区和第二漏极区，其中，所述第二栅极区具有第二长度；以及
第二纳米线组，设置在所述第二栅极区中，所述第二纳米线组包括具有第二直径的纳米线，并连接至所述第二源极区中的第二部件和所述第二漏极区中的所述第二部件，
其中，如果所述第一长度大于所述第二长度，则所述第一直径小于所述第二直径；以及
其中，如果所述第一长度小于所述第二长度，则所述第一直径大于所述第二直径。
在可选实施例中，所述IC还包括：多个所述第一纳米线组，设置在所述第一栅极区中，两个相邻的所述第一纳米线组的纳米线之间具有不同的间距；以及，其中，当所述间距改变时，所述第一纳米线组的第一直径改变。
在可选实施例中，所述第一长度和所述第二长度的差值约为20%。
在可选实施例中，所述第一纳米线组和所述第二纳米线组包括半导体材料。
在可选实施例中，所述半导体材料包括硅（Si）。
在可选实施例中，所述第一直径和所述第二直径的差值约为20%。
在可选实施例中，所述半导体材料包括锗（Ge）。
在可选实施例中，所述第一纳米线组包括至少两个纳米线。
在可选实施例中，至少两个所述第一纳米线组共同连接至所述第一源极区中的部件和所述第一漏极区中的部件。
在可选实施例中，如果不同的第一纳米线组具有不同的间距，则所述第一纳米线组的第一直径与所述不同的第一纳米线组的第一直径不同。
在可选实施例中，所述IC还包括：高k（HK）层，设置在所述衬底上方，包裹所述第一栅极区和所述第二栅极区中的所述第一纳米线组的第一纳米线和所述第二纳米线组的第二纳米线；以及，金属栅极，设置在所述MOS区的所述第一栅极区和所述第二栅极区中的所述HK层上方。
根据本发明的另一方面，还提供了一种集成电路（IC），包括：
衬底，具有金属氧化物半导体（MOS）区；
位于所述MOS区中的第一器件的第一栅极区、第一源极区和第一漏极区，其中，所述MOS区具有第一栅极区长度；
多个第一纳米线组，设置在所述第一栅极区中，在两个相邻的第一纳米线组之间具有不同的间距，所述第一纳米线组包括具有第一直径的纳米线并连接至所述第一源极区中的公共部件和所述第一漏极区中的公共部件；其中，如果不同的第一纳米线组具有不同的间距，则所述第一纳米线组的第一直径与所述不同的第一纳米线组的第一直径不同；
位于所述MOS区中的第二器件的第二栅极区、第二源极区和第二漏极区，其中，所述MOS区具有第二栅极区长度；
第二纳米线组，设置在所述第二栅极区中，所述第二纳米线组包括具有第二直径的纳米线并连接至所述第二源极区中的部件和所述第二漏极区中的部件，
其中，如果所述第一长度大于所述第二长度，则所述第一直径小于所述第二直径；以及
其中，如果所述第一长度小于所述第二长度，则所述第一直径大于所述第二直径。
在可选实施例中，所述第一长度与所述第二长度的差值约为20%。
在可选实施例中，所述第一纳米线组和所述第二纳米线组包括半导体材料。
在可选实施例中，所述半导体材料包括硅（Si）。
在可选实施例中，所述第一直径和所述第二直径的差值约为20%。
在可选实施例中，所述半导体材料包括锗（Ge）。
在可选实施例中，所述IC还包括：高k（HK）层，设置在所述衬底上方，包裹所述第一栅极区和所述第二栅极区中的所述第一纳米线组和所述第二纳米线组中的纳米线；以及，金属栅极，设置在所述第一栅极区和所述第二栅极区中的所述HK层上方。
根据本发明的又一方面，还提供了一种集成电路（IC），包括：
衬底，具有N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区；
多个栅极结构，位于所述NMOS区和所述PMOS区中，其中，所述栅极结构的长度和所述栅极结构的间距在至少两个栅极结构之间不同；以及
纳米线组，设置在所述多个栅极结构的每一个中，其中，每一个纳米线组中的每一个纳米线的直径均与相邻栅极结构的相对间距和所述相邻栅极结构的相对长度直接对应。
在可选实施例中，所述PMOS区中的栅极结构中的纳米线与所述NMOS区中的栅极结构中的纳米线具有不同的材料。
在可选实施例中，所述PMOS区中的栅极结构中的纳米线包括锗（Ge），而所述NMOS区中的栅极结构中的纳米线包括硅（Si）。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚论述起见，各个部件的尺寸可以被任意增大或缩小。
图1A是根据本发明实施例的具有纳米线的集成电路（IC）的示意性立体图。
图1B是沿着图1A中的线A-A的具有纳米线的IC的截面图。
图1C是沿着图1A中的线B-B的具有纳米线的IC的截面图，其中，线B-B垂直于线A-A。
图1D是根据本发明实施例的具有纳米线的IC的示意性立体图。
图2A是根据本发明实施例的具有纳米线的IC的示意性立体图。
图2B至图2C和图3A至图3B是沿着图2A中的线A-A的具有纳米线的示例性IC的截面图。
图4是具有纳米线组的示例性IC的俯视图。
具体实施方式
可以理解，下面公开的内容提供了许多不同的实施例或者实例，用以实现本发明的不同特征。下面将描述部件或者布置的具体实例以简化本发明。当然它们仅为实例而并不旨在限制本发明。例如，在以下描述中，第一部件形成在第二部件上方或者之上可以包括以直接接触的方式形成第一部件和第二部件的实施例，也可以包括在第一部件和第二部件之间形成额外部件使得第一部件和第二部件不直接接触的实施例。此外，本发明可在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其自身并不表示所论述的各个实施例和/或结构之间的关系。
本发明的目的在于但不限于包括P型金属氧化物半导体（PMOS）器件和N型金属氧化物半导体（NMOS）器件的互补金属氧化物半导体（CMOS）器件。以下公开将继续以CMOS器件作为实例来描述本发明的各个实施例。然而，应当理解，除非特别说明，否则本发明并不应限于特定类型的器件。
图1A为根据本发明实施例的IC100的侧视图。图1B和1C分别为沿着图1中的线A-A和B-B的IC100的横截面图。线B-B垂直于线A-A的方向。图1D是根据本发明另一实施例的IC100的侧视图。其他附图根据制造的各个阶段提供了IC100的侧视图和截面图。
参考图1A至图1C，IC100可为具有多个不同的器件、区域和面积的较大的集成电路（IC）的一部分，诸如位于衬底210中或其上的p型MOS（PMOS）和/或N型MOS（NMOS）。如图中所示，衬底210包括源极区/漏极区212以及具有长度L的栅极区214，该长度在整个器件中可以变化。例如，栅极区在一个位置处可具有第一长度L1，并且在另一位置处可具有第二长度L2。在本实施例中，第二长度L2大于20nm，该长度比第一长度L1长出20%以上。具有第一长度L1的栅极区214被称为短沟道栅极区，而具有第二长度L2的栅极区214被称为长沟道栅极区。源极区/漏极区212由栅极区214所分隔。
在本实施例中，衬底210为块状硅衬底。可选地，衬底210可包括：元素半导体，诸如晶体结构的硅或锗；化合物衬底，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。合适的衬底210还包括绝缘体上半导体衬底，诸如绝缘体上硅（SOI）、绝缘体上硅锗（SGOI）、绝缘体上锗衬底。例如，使用注氧隔离（SIMOX）、晶圆接合和/或其他适合的方法来制造SOI衬底。
一些示例性衬底210还包括绝缘层。绝缘层包括任何适合的材料，包括氧化硅、蓝宝石和/或它们的组合。示例性绝缘层可为埋氧层（BOX）。通过适合的工艺，诸如注入（例如：SIMOX）、氧化、沉积和/或其他适合的工艺，形成绝缘体。
根据本领域已知的设计需求，衬底210可包括多种掺杂区。掺杂区可掺杂诸如硼或BF2的p型掺杂剂；诸如磷或砷的n型掺杂剂，或者它们的组合。掺杂区可以P-阱结构、N-阱结构、双-阱结构或使用凸起结构直接形成在衬底210上。
在源极/漏极区212中形成凹进的第一鳍220。在一个实施例中，通过首先在衬底210上方形成第一鳍然后使第一鳍凹进来形成凹进的第一鳍220。可通过包括各种沉积、光刻和/或蚀刻工艺的任何适合的工艺来形成第一鳍。在一个实例中，通过对硅衬底210的一部分进行图案化和蚀刻来形成第一鳍。在另一实例中，通过对沉积在绝缘层上方的硅层（例如，SOI衬底的硅-绝缘体-硅堆叠件的上硅层）进行图案化和蚀刻来形成第一鳍。应当理解，第一鳍可包括以相似方式形成的多个平行的鳍。
在衬底210上形成多个隔离区230以隔离有源区。例如，隔离区230分隔第一鳍。可使用传统的隔离技术来形成隔离区230，诸如浅沟槽隔离（STI），以限定并电隔离多个区域。隔离区230包括氧化硅、氮化硅、氮氧化硅、气隙（air gap）、其他适合的材料或它们的组合。由任何适合的工艺形成隔离区230。作为一个实例，STI的形成包括光刻工艺、在衬底中蚀刻沟槽（例如，通过使用干蚀刻和/或湿蚀刻）、以及用一种或多种介电材料来填充沟槽（例如，通过使用化学汽相沉积工艺）。如在本实施例中，可部分地填充沟槽，保留在沟槽之间的衬底形成鳍结构。在一些实例中，填充后的沟槽可具有多层结构，诸如填充有氮化硅或氧化硅的热氧化衬里层。
然后对第一鳍实施凹进以形成凹进的第一鳍220。凹进工艺可包括干蚀刻工艺、湿蚀刻工艺和/或它们的组合。凹进工艺还可包括选择性湿蚀刻或选择性干蚀刻。湿蚀刻方案包括氢氧化四甲铵（TMAH）、HF/HNO3/CH3COOH方案或其他适合的方案。干蚀刻工艺包括使用氯基化学物的偏压等离子体蚀刻工艺。其他干蚀刻剂气体包括CF4、NF3、SF6和He。
在源极/漏极区212中的凹进的第一鳍220上方形成源极/漏极部件240。在一个实施例中，第一半导体材料层通过外延生长工艺沉积在凹进的第一鳍220上方以形成源极/漏极部件240。外延生长工艺包括CVD沉积技术（例如，汽相外延（VPE）和/或超高真空CVD（UHV-CVD）），分子束外延和/或其他适合的工艺。第一半导体材料层可包括锗（Ge）、硅（Si）、砷化镓（GaAs）、砷化铝镓（AlGaAs）、硅锗（SiGe）、磷砷化镓（GaAsP）或其他适合的材料。在外延工艺期间可原位掺杂源极/漏极部件240。例如，外延生长的SiGe源极/漏极部件240可掺杂硼；外延生长的Si外延源极/漏极部件240可掺杂碳以形成Si:C源极/漏极部件，掺杂磷以形成Si:P源极/漏极部件或者掺杂碳和磷以形成SiCP源极/漏极部件。在一个实施例中，源极/漏极部件240并非原位掺杂，实施注入工艺（即，结注入工艺）以掺杂源极/漏极部件240。
可选地，如图1D所示，在两个隔离区230之间形成内区域216。在内区域216中，去除每一个单独的第一鳍以在衬底210上方形成台面218。在源极/漏极区212的台面218上方形成公共源极/漏极部件240。在一个实施例中，公共源极/漏极部件240直接连接至栅极区214中的每一个纳米线组310。
位于衬底210上方的层间介电（ILD）层250包括在源极/漏极部件240之间。ILD层250包括氧化硅、氮氧化物或其他适合的材料。ILD层250可包括单层或多层。通过诸如CVD、ALD或旋涂（SOG）的适合技术形成ILD层250。可进行化学机械抛光（CMP）以平坦化ILD层250的顶面。
在本实施例中，在栅极区214中的衬底210上方形成一个或多个纳米线组310和高k/金属栅极（HK/MG）320。每一个纳米线组310可具有一个纳米线或多个纳米线。一个纳米线组310中的每一个纳米线可与相应的源极/漏极部件240相连接。在一个实施例中，纳米线组310直接与相应的源极/漏极部件240相连接。纳米线组310中的纳米线可被形成为具有直径d的棒状形，后文将描述更多细节。
HK/MG320可包括界面层（IL）322、HK介电层324和MG326。IL322和HK介电层324设置在衬底210上方，包括一致地包裹纳米线组310。HK介电层324可包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3（STO）、BaTiO3（BTO）、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、（Ba,Sr）TiO3（BST）、Al2O3、HfAlO、Si3N4、氮氧化物（SiON）或其他适合的材料。可通过ALD或其他适合的方法来沉积IL322和HK介电层324。
MG326可包括单层或多层，诸如金属层、衬里层、润湿层和粘合层。MG326可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W或任何适合的材料。可通过ALD、PVD、CVD或其他适合的工艺来形成MG326。可单独地形成MG326以用于具有不同金属层的NMOS和PMOS。
以下描述将针对在工艺阶段中栅极区214中的纳米线310的形成和结构，该阶段在图1A至图1C的阶段之前。图2A至图2C示出了纳米线310的形成和结构的实例。
参考图2A至图2C，在栅极区214中的衬底210上方形成第二鳍420。第二鳍420的形成在很多方面与上文中结合图1所论述的第一鳍220相似。在一个实施例中，凹进的第一鳍220和第二鳍420是相同的鳍。隔离区230设置在第二鳍420之间。
在本实施例中，使第二鳍420凹进并且在凹进的第二鳍420上方形成半导体层堆叠件430。半导体层堆叠件430可包括多个半导体层。这些半导体层中的每一个可具有基本上互相不同的厚度。半导体层堆叠件430可包括锗（Ge）、硅（Si）、砷化镓（GaAs）、硅锗（SiGe）、磷砷化镓（GaAsP）或其他适合的材料。可通过外延生长工艺（诸如CVD、VPE、UHV-CVD、分子束外延和或其他适合的工艺）来沉积半导体层堆叠件430。
在一个实施例中，在PMOS单元（如图2B中所示）中，半导体层堆叠件430具有（从下到上）SiGe（433）/Si（434）/SiGe（433）/Si（434）/SiGe（433）/Si（434），而在NMOS单元（如图2C中所示）中具有SiGe（433）/Si（434）/SiGe（433）/Si（434）/SiGe（433）。
半导体层堆叠件430可包括不同半导体层的其他适合的组合。可实施化学CMP工艺以平坦化具有隔离区230的半导体层堆叠件430的顶面。
在本实施例中，可回蚀刻隔离区230以形成开口间距以横向地暴露半导体层堆叠件430的至少一部分。蚀刻工艺可包括选择性湿蚀刻或选择性干蚀刻，从而对半导体层堆叠件430具有适当的蚀刻选择性。设计开口间距的各种尺寸以满足特定的器件结构需求，诸如用于随后形成的互连接触件的开口间距。例如，第一区610中的第一开口间距s1基本上大于第二区620中的第二开口间距s2。第二开口间距s2基本上大于第三区630中的第三开口间距s3。例如，在PMOS单元中，s1在25nm至150nm的范围内，s2在20nm至50nm的范围内，以及s3在20nm至35nm的范围内。又例如，在NMOS单元中，s1在25nm至150nm的范围内，s2在20nm至35nm的范围内以及s3在20nm至35nm的范围内。
在PMOS单元中，在横向地暴露半导体层堆叠件430之后，实施第一热氧化工艺以暴露栅极区214中的半导体材料层堆叠件430。在热氧化工艺期间，半导体层堆叠件430中的每一半导体层的至少一部分被转化为半导体氧化层。可在氧气环境中，或在蒸汽环境和氧气环境的结合中进行热氧化工艺。
在NMOS单元中，在横向地暴露出半导体层堆叠件430之后，实施选择性蚀刻工艺以去除半导体层堆叠件430中的一种类型的半导体层并且留下悬置在栅极区214中（由源极/漏极部件240支承）的另一种类型的半导体层。例如，通过选择性蚀刻去除SiGe层433并将Si层434悬置在栅极区214中。然后，进行第二热氧化工艺。第二热氧化工艺在许多方面与上面论述的第一热工艺相似。在一个实施例中，第一和第二热工艺是一个热工艺。
参考图3A至图3B，在本实施例中，控制第一/第二热氧化工艺以将暴露的半导体层堆叠件430转化为半导体氧化层堆叠件530的设计结构，其在预定的半导体氧化层中具有引线部件532。例如，在PMOS单元中，SiGe层433被转化为具有Ge引线部件532的硅锗氧化物533，而Si层434被完全转化为氧化硅层534。Ge引线部件532被称作Ge纳米线。作为另一个实例，在NMOS单元中，悬置的Si层434被转化为具有Si引线部件535的氧化硅层534。Si引线部件535被称作Si纳米线。
在本实施例中，在第一、第二和第三区610、620和630中的引线部件532/535的直径基本上不同。在一个实施例中，形成在第一区610中的引线部件532/535具有第一直径d1，第一直径d1基本上小于形成在第二区620中的引线部件532/535的第二直径d2。第二直径d2基本上小于第三区630中的第三直径d3。在一个实施例中，第一直径d1比第二直径d2小10%。第二直径d2比第三直径d3小10%。例如，在PMOS单元中，d1在4nm至15nm的范围内，d2在1nm至3nm的范围内并且d3在1nm至3nm的范围内。对于另一例子，在NMOS单元中，d1在4nm至13nm的范围内，d2在1nm至3nm的范围内并且d3在1nm至3nm的范围内。
在本实施例中，长栅极区中的引线部件532/535的直径基本上小于短栅极区中相应的引线部件532/535的直径。在一个实施例中，长栅极区中的引线部件532/535的直径比短栅极区中的相应的引线部件532/535小20%。
在形成引线部件532/535之后，通过选择性蚀刻工艺去除半导体氧化层堆叠件530的所有层并将引线部件532/535保留在栅极区214中。如图1A至图1C所示，在栅极区214的相同位置处垂直对准的引线部件532/535称为纳米线组310。如图1A至如1C所述，HK/MG320形成在栅极区214中，包括一致地包裹纳米线组310。
参考图4，在一个实施例中，第一晶体管710与第二晶体管720相邻，每一个晶体管可包括多个纳米线组310。为了描述起见，位于晶体管710的最左侧、最右侧以及它们之间的纳米线组310的直径分别为D1l、D1r和D1c。同时，位于晶体管720的最左侧、最右侧以及它们之间的纳米线组310的直径分别为D2l、D2r和D2c。在位于最左侧和最右侧的纳米线组的中间可以有一个以上的纳米线组310。晶体管710和720的栅电极326之间的间距为Sg。晶体管710的外部间距分别为So(l)和So(r)。第一晶体管710内的间距为Si。在一个实施例中，第一晶体管710包括三个纳米线组310。So(l)和So(r)两者都大于Si，D1c大于D1l和D1r。在另一实施例中，第一晶体管710包括四个纳米线组310。So(l)和So(r)两者都大于Si，D1c（在最左纳米线组和最右纳米线组之间有两个纳米线组）大于D1l和D1r。
IC100可具有本领域已知的用于CMOS或MOS器件的各种另外的部件和区域。例如，各种接触件/通孔/线以及多层互连部件（例如，金属层和层间电介质）形成在衬底210上方，被配置为连接IC100的各个部件或结构。多层互连件可包括诸如传统的通孔或接触件的垂直互连件，以及诸如金属线的水平互连件。各种互连结构可利用包括铜、钨、铝和/或硅化物（例如PtSi、CoSi2、NiSi、NiPtSi、WSi2、MoSi2、TaSi2或其他难熔金属硅化物）的各种导电材料。在一个例子中，单镶嵌和/或双镶嵌工艺用于形成铜相关的多层互连结构。
基于上述描述，本发明提供了在PMOS单元和NMOS单元中具有纳米线组的集成电路。纳米线组具有一个或多个纳米线。纳米线根据纳米线不同的环境和位置（诸如介于相邻纳米线组之间的开口间距的尺寸或栅极区长度）形成为具有不同的直径。
本发明提供了集成电路（IC）的多个不同实施例。IC包括具有金属氧化物半导体（MOS）区的衬底、位于MOS区中的第一器件的第一栅极区、源极区和漏极区。第一栅极区具有第一长度。IC还包括设置在第一栅极区中的第一纳米线组，第一纳米线组包括具有第一直径的纳米线，并连接至第一源极区中的第一部件和第一漏极区中的第一部件。IC还包括MOS区中的第二器件的第二栅极区、源极区和漏极区。第二栅极区具有第二长度。IC还包括设置在第二栅极区中的第二纳米线组，第二纳米线组包括具有第二直径的纳米线，并连接至第二源极区中的第二部件和第二漏极区中的第二部件。如果第一长度大于第二长度，则第一直径小于第二直径。如果第一长度小于第二长度，则第一直径大于第二直径。
在另一实施例中，集成电路包括具有金属氧化物半导体（MOS）区的衬底、具有第一栅极区长度的MOS区中的第一器件的第一栅极区、源极区和漏极区。IC还包括设置在第一栅极区中的多个第一纳米线组，在两个相邻的第一纳米线组之间具有不同的间距，第一纳米线组包括具有第一直径的纳米线，并连接至第一源极区的共同部件和第一漏极区的共同部件。如果不同的第一纳米线组具有不同的间距，则第一纳米线组的直径与不同的第一纳米线组的第一直径不同。IC还包括具有第二栅极区长度的MOS区中的第二器件的第二栅极、源极和漏极区。IC还包括设置在第二栅极区中的第二纳米线组，第二纳米线组包括具有第二直径的纳米线，并连接至第二源极区中的部件和第二漏极区中的部件。如果第一长度大于第二长度，则第一直径小于第二直径，并且，如果第一长度小于第二长度，则第一直径大于第二直径。
在又一实施例中，集成电路（IC）包括具有N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区的衬底、位于NMOS区和PMOS区中的多个栅极结构。栅极结构的长度和栅极结构之间的间距在至少两个栅极结构之间不同。纳米线组设置在多个栅极结构中的每一个栅极结构中。每一个纳米线组中的每一个纳米线的直径与相邻栅极结构的相对间距和栅极结构的相对长度直接对应。
上面论述了若干实施例的轮廓特征，以使本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，它们可以很容易地使用本发明作为基础来设计或修改用于达到与本文所介绍的实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，它们可对本发明作出多种变化、替换以及改变。

Claims (10)

1.一种集成电路，包括：
衬底，具有金属氧化物半导体（MOS）区；
位于所述MOS区中的第一器件的第一栅极区、第一源极区和第一漏极区，其中，所述第一栅极区具有第一长度；
第一纳米线组，设置在所述第一栅极区中，所述第一纳米线组包括具有第一直径的纳米线，并连接至所述第一源极区中的第一部件和所述第一漏极区中的所述第一部件；
位于所述MOS区中的第二器件的第二栅极区、第二源极区和第二漏极区，其中，所述第二栅极区具有第二长度；以及
第二纳米线组，设置在所述第二栅极区中，所述第二纳米线组包括具有第二直径的纳米线，并连接至所述第二源极区中的第二部件和所述第二漏极区中的所述第二部件，
其中，如果所述第一长度大于所述第二长度，则所述第一直径小于所述第二直径；以及
其中，如果所述第一长度小于所述第二长度，则所述第一直径大于所述第二直径。
2.根据权利要求1所述的IC，还包括：
多个所述第一纳米线组，设置在所述第一栅极区中，两个相邻的所述第一纳米线组的纳米线之间具有不同的间距；以及
其中，当所述间距改变时，所述第一纳米线组的第一直径改变。
3.根据权利要求1所述的IC，其中，所述第一长度和所述第二长度的差值约为20%。
4.根据权利要求1所述的IC，其中，所述第一纳米线组和所述第二纳米线组包括半导体材料。
5.一种集成电路（IC），包括：
衬底，具有金属氧化物半导体（MOS）区；
位于所述MOS区中的第一器件的第一栅极区、第一源极区和第一漏极区，其中，所述MOS区具有第一栅极区长度；
多个第一纳米线组，设置在所述第一栅极区中，在两个相邻的第一纳米线组之间具有不同的间距，所述第一纳米线组包括具有第一直径的纳米线并连接至所述第一源极区中的公共部件和所述第一漏极区中的公共部件；其中，如果不同的第一纳米线组具有不同的间距，则所述第一纳米线组的第一直径与所述不同的第一纳米线组的第一直径不同；
位于所述MOS区中的第二器件的第二栅极区、第二源极区和第二漏极区，其中，所述MOS区具有第二栅极区长度；
第二纳米线组，设置在所述第二栅极区中，所述第二纳米线组包括具有第二直径的纳米线并连接至所述第二源极区中的部件和所述第二漏极区中的部件，
其中，如果所述第一长度大于所述第二长度，则所述第一直径小于所述第二直径；以及
其中，如果所述第一长度小于所述第二长度，则所述第一直径大于所述第二直径。
6.根据权利要求5所述的IC，其中，所述第一长度与所述第二长度的差值约为20%。
7.根据权利要求5所述的IC，其中，所述第一纳米线组和所述第二纳米线组包括半导体材料。
8.一种集成电路（IC），包括：
衬底，具有N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区；
多个栅极结构，位于所述NMOS区和所述PMOS区中，其中，所述栅极结构的长度和所述栅极结构的间距在至少两个栅极结构之间不同；以及
纳米线组，设置在所述多个栅极结构的每一个中，其中，每一个纳米线组中的每一个纳米线的直径均与相邻栅极结构的相对间距和所述相邻栅极结构的相对长度直接对应。
9.根据权利要求8所述的IC，其中，所述PMOS区中的栅极结构中的纳米线与所述NMOS区中的栅极结构中的纳米线具有不同的材料。
10.根据权利要求9所述的IC，其中，所述PMOS区中的栅极结构中的纳米线包括锗（Ge），而所述NMOS区中的栅极结构中的纳米线包括硅（Si）。
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