CN102986010A - 多重直径纳米线场效晶体管的生成 - Google Patents

多重直径纳米线场效晶体管的生成 Download PDF

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CN102986010A
CN102986010A CN201180023254XA CN201180023254A CN102986010A CN 102986010 A CN102986010 A CN 102986010A CN 201180023254X A CN201180023254X A CN 201180023254XA CN 201180023254 A CN201180023254 A CN 201180023254A CN 102986010 A CN102986010 A CN 102986010A
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J·斯雷特
S·邦萨伦提普
G·科恩
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GlobalFoundries Inc
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Abstract

本发明提供一种修改具有设置在绝缘体上的半导体的晶片的方法，所述方法包括以下步骤：分别在第一和第二晶片区域处形成在每个端部处连接至半导体衬垫的第一和第二纳米线沟道，其中第二纳米线沟道侧壁比第一纳米线沟道侧壁相对于所述半导体的晶面更加错位；以及朝向所述侧壁与所述晶面之间的对准状态转移所述半导体，以使所述第一和第二纳米线沟道之间的厚度差反映所述第二纳米线沟道侧壁的更大错位。

Description

多重直径纳米线场效晶体管的生成
技术领域
本发明的方面涉及对生成多重直径纳米线场效晶体管的方法。
背景技术
作为未来互补金氧半导体(CMOS)部件设计的选择，纳米线FET正在引起人们相当大的关注。虽然正在取得进展，但仍将考虑若干关键问题。在这些问题中，一个特定问题为将要求纳米线FET器件提供具有不同驱动电流强度和/或不同阈值电压(Vt)的器件。
尽管当前存在对提供具有不同驱动电流强度和/或不同阈值电压的器件的问题的解决方案，但该解决方案通常依赖于通过相应地调制栅极功函数来调制器件的阈值电压。因此，此解决方案倾向于具有相对困难且成本高昂的工艺集成操作以及，附加地，该解决方案倾向于存在变化问题。
发明内容
根据本发明的方面，本发明提供一种修改具有设置在绝缘体上的半导体的晶片的方法，该方法包括以下步骤：分别在第一和第二晶片区域处形成在每个端部处连接至半导体衬垫的第一和第二纳米线沟道，其中第二纳米线沟道侧壁比第一纳米线沟道侧壁相对于所述半导体的晶面更大程度地错位（misaligned）；以及朝向所述第一和第二纳米线沟道的侧壁与所述晶面之间的对准状态从所述第一和第二纳米线沟道转移半导体材料，以使在所述转移之后所述第一和第二纳米线沟道之间的厚度差反映所述第二纳米线沟道侧壁的更大错位。
根据本发明的方面，本发明提供一种修改具有设置在绝缘体上的半导体的晶片的方法，该方法包括以下步骤：分别在第一和第二晶片区域处形成在每个端部处连接至半导体衬垫的第一和第二纳米线沟道，其中第一纳米线沟道侧壁的特征在于具有相对于所述半导体的晶面的第一对准度，且第二纳米线沟道侧壁的特征在于具有相对于所述晶面的第二对准度，所述第二对准度不同于所述第一对准度，以及朝向所述侧壁与所述晶面之间的对准状态促使半导体材料从所述第一和第二纳米线沟道转移，以使在转移之后在所述第一和第二纳米线沟道之间的厚度差根据所述第一和第二对准度差异。
根据本发明的方面，本发明提供一种修改具有设置在绝缘体上的半导体的晶片的方法，该方法包括以下步骤：在所述晶片的第一区域中形成由纳米线沟道连接的半导体衬垫对，所述纳米线沟道具有沿所述半导体的{110}晶面定向的长轴以及基本上平行于所述半导体的{110}面中的一个的侧壁；在所述晶片的第二区域中形成由纳米线沟道连接的半导体衬垫对，所述纳米线沟道具有相对于所述半导体的{110}晶面成一角度的长轴以及相似地相对于所述半导体的{110}面成角度的侧壁；以及再定向所述第二区域的所述纳米线沟道，以通过将半导体材料从所述纳米线沟道扩散至所述衬垫，使得所述第二区域中的所述纳米线沟道与处于所述第一区域的纳米线沟道相比被减薄而形成平行于所述半导体的{110}面的侧壁。
根据本发明的另一方面，本发明提供一种晶片，该晶片包括衬底；掩埋氧化物(BOX)层，其设置在所述衬底上；以及绝缘体上硅(SOI)结构，其设置在第一和第二区域处的所述BOX层上，在每个区域处的所述SOI结构具有通过在其中形成的各纳米线沟道连接的各SOI衬垫对，处于所述区域中的一个的所述SOI衬垫和所述纳米线沟道比处于所述区域中的另一个的所述SOI衬垫和所述纳米线沟道相对于所述SOI的{110}面更加错位。
附图说明
被视为本发明的主题在本专利说明书结束处的权利要求中被特别指出且明确主张。结合附图，本发明的前述及其他方面、特征结构及优点将从以上详细描述显而易见，其中：
图1为在第一和第二区域处具有限定于其上的纳米线沟道的图1的晶片的透视图；
图2为图1的纳米线沟道的尺寸的平面图；
图3为具有限定于其上的再成形纳米线的图1的晶片的透视图；
图4为具有栅极结构的再成形纳米线的透视图；以及
图5包括具有不同厚度的纳米线的截面图。
具体实施方式
本文经由关于硅(Si)纳米线及Si处理的描述提供支撑例如环绕栅极(GAA)纳米线场效晶体管(FET)的结构以及用于制造该晶体管的方法。然而，本技术亦可由诸如例如锗(Ge)的其他半导体材料实施。当使用非含Si半导体时，本教导的处理步骤类似于且适合于所用的特定半导体。因此，诸如Si、硅锗(SiGe)、Si/SiGe、碳化硅(SiC)或碳化硅锗(SiGeC)的含Si半导体材料的使用仅理解为示例性的。
参看图1及图2，提供晶片1，且其包括Si衬底101、掩埋氧化物(BOX)层102及绝缘体上硅(SOI)层103。晶片1可使用诸如注氧隔离(SIMOX)或晶片接合（例如SmartCutTM）的方法制造。此晶片制造技术为本领域技术人员公知，因此本文不再进一步描述。亦可以本领域所已知的其他SOI衬底取代本文所述的BOX上SOI配置，且其将在本教导的范围内。
晶片1至少具有建立于其上的第一区域10及第二区域20。SOI衬垫对103A及将其连接的纳米线沟道104可被构图为处于第一区域10及第二区域20的SOI层103中，以在各区域中形成例如梯状结构。纳米线沟道104及SOI衬垫103A的构图可经由光刻（例如光或电子束）及随后的反应离子蚀刻(RIE)或经由侧壁转移技术达成。此构图技术为本领域技术人员公知。
处于第一区域10及第二区域20的SOI层103最初各自由具有相似厚度的相似部件形成。然而，如图1及图2所示，处于第一区域10的SOI衬垫103A及纳米线沟道104经形成为具有基本上平行于和/或对准于例如半导体的{110}晶面中的一者的侧壁，虽然其他平面参考坐标系是可能的。即，纳米线沟道104中的每一者的主（长）轴沿半导体的{110}晶面的方向定向。另一方面，处于第二区域20的SOI衬垫103A及纳米线沟道104经形成为具有相对于{110}晶面成角度α和/或以角度α错位的侧壁，其中纳米线沟道104的主（长）轴亦相对于{110}晶面以角度α错位。例如，第一区域10中的纳米线沟道104可经构图以具有平行于{110}面的侧壁及平行于{100}面的顶面，而第二区域20中的纳米线沟道104将具有相对于{110}晶面以一角度（诸如α=1度）错位的侧壁及平行于{100}面的顶面。
在第二区域20的纳米线沟道104成角度和/或错位的情况下，如上所述，对第一区域10及第二区域20两者进行的减薄操作（例如纳米线沟道104的退火）将倾向于在第二区域20处比在第一区域10处具有更大的减薄效果。此状况由于处于第二区域20的SOI层103的偏移结晶取向使得在第二区域20的SOI层103比第一区域10的SOI层103对减薄操作的效果更为敏感。该减薄操作倾向于通过将半导体材料自纳米线沟道104扩散至SOI衬垫103A再定向第二区域20的纳米线沟道104，以形成平行于{110}晶面的侧壁。此举具有第二区域20中的纳米线沟道104在再定向之后比第一区域10的沟道变得更薄的效果。
第二区域20的SOI层103被减薄超过第一区域10的SOI层103的程度可通过增加或减少第一区域10及第二区域20的侧壁的相对错位来控制。例如，处于第一区域10的纳米线沟道104的侧壁可相对于该半导体的{110}晶面对准，或仅以一小角度α错位。同时，处于第二区域20的纳米线沟道104的侧壁可相对于该半导体的{110}晶面以一相对大角度α有意错位。此处，第一区域10及第二区域20的侧壁的相对错位越大，则在该第二区域20处的减薄程度越大。
确实，参看图2，了解到该角度的倾斜越大，则产生的再成形纳米线108将越薄，纳米线沟道104相对于{110}晶面的角度α可为小于45°的任何角度（且实践上α不超过几度）。即，成更倾斜角度的纳米线沟道104将比更垂直的纳米线沟道104倾向于形成更薄的再成形纳米线108。因此，尽管纳米线沟道104的尺寸及其倾斜度可根据设计考虑而变化，但纳米线沟道104的轮廓（profile）应至少包括所要形成的再成形纳米线108的轮廓。
其中硅自纳米线沟道104扩散的再定向处理在G.M.Cohen等人的来自San Francisco,CA(2010)的Material Research Symposium的“Controlling the shape and dimensional variability of top-downfabricated silicon nanowires by hydrogen annealing”中有更充分的描述，其内容以引用的方式并入本文。晶面方向的规格遵循密勒指数（Millerindices）规定，其在例如Ashcroft及Mermin的固态物理学(1976)的第5章中有所描述，其内容以引用的方式并入本文。遵循此规定，晶面族（即，根据晶体的对称性等价的面）通常通过一对{}括号引用。例如，面(100)、(010)及(001)在立方晶体中全部等价。以{100}面代表其全体。当引用晶体中的方向时，使用[]方括号，例如[100]、[010]、[001]、[-100]、[0-10]、[00-1]，且同样地，以<100>代表晶向族全体。
因此，处于第二区域20的纳米线沟道104可被形成为再成形纳米线108（见图3），再成形纳米线108比第一区域10的纳米线更薄，即使其中在各区域处以类似方式进行退火处理。具体而言，第一区域10的再成形纳米线108将具有厚度T1′，且第二区域20的再成形纳米线108将具有厚度T2'，厚度T2'将不同于厚度T1'且通常比厚度T1′更薄。因此,在第一区域10及第二区域20处的再成形纳米线108的此相对厚度差异将导致再成形纳米线108显示相对彼此独特的物理特性。
纳米线沟道104的成角度化可以各种方式实现。例如，光刻掩模可包括用于区域10及区域20的绘制后的（as-drawn）对准图形和错位图形，或在成角度纳米线沟道104的构图期间，晶片1或构图掩模可相对于{110}晶面旋转。然而，纳米线沟道104的成角度化无须处于任何特定晶面中，且上述{110}晶面仅理解为示例性的。
参看图3，将纳米线沟道104再成形为纳米线108通常通过在惰性气氛中退火实现。此处理可为同时或顺序应用于区域10及区域20的无掩模处理。
例如，晶片1可在示例性H2气体中退火。在此H2退火之前不久，可自纳米线沟道104及SOI衬垫103A的侧壁蚀刻掉本征氧化物。该H2中的退火具有若干目的，包括但不限于经由Si的再分布平滑化纳米线沟道104的侧壁、将该侧壁重新对准至SOI衬垫103A的晶面、将纳米线沟道104截面从矩形再成形为更加圆柱形以及将纳米线沟道104体减薄。
根据示例性实施例，该惰性气体退火在以下条件下进行：自约30托（Torr）至约1000托的气体压力、自约摄氏600度(℃)至约1100℃的温度及从约1分钟至约120分钟的持续时间。基本而言，Si再分布的速率随温度而增大且随压力增大而减小。
如图3所示，纳米线沟道104经由该退火处理或经由BOX层102的进一步蚀刻及凹陷可再成形为纳米线108，且悬置于BOX层102上或自BOX层102释放。在第一区域10及第二区域20中，再成形纳米线108因此在SOI衬垫103A之间且在凹陷氧化物105之上形成悬置的桥。可达成BOX层102的凹陷，其由该退火处理所致，或使用稀氢氟酸(DHF)蚀刻以底切BOX层102。尽管SOI衬底提供限定及悬置纳米线沟道104和/或再成形纳米线108的便利途径，但有可能由其他衬底获得悬置。例如，在体Si晶片上外延生长的SiGe/Si叠层亦可经构图而形成纳米线沟道104和/或再成形纳米线108。SiGe层亦可用作被底切的牺牲层（类似于BOX层102）。
处于第一区域10且具有厚度T1'的再成形纳米线108及处于第二区域20且具有厚度T2'的再成形纳米线108可具有不同的驱动电流和/或阈值电压。以此方式，应当了解，可通过相应地控制部分决定最终厚度T1′及T2'的处于第一区域10及第二区域20的纳米线沟道104的成角度化来控制至少处于晶片1的第一区域10及第二区域20的电路特性。
现参看图4及图5，栅极结构402可围绕再成形纳米线108形成。首先，用第一及第二栅极电介质112A及112涂覆再成形纳米线108。第一（以及可选的）栅极电介质112A通常为SiO2。第二栅极电介质112可包括二氧化硅(SiO2)、氮氧化硅(SiON)、二氧化铪(HfO2)或任何其他合适的一种或多种高k电介质，且在SiO2和SiON的情况下，可利用化学气相沉积(CVD)、原子层沉积(ALD)或氧化炉进行沉积。然后，可形成例如TaN或TiN的薄栅极导体117的保形沉积。这之后可为掺杂多晶硅113的沉积，以在环绕再成形纳米线108的周边形成栅极叠层118。掩模115可用于促进经由例如RIE蚀刻栅极线。在栅极叠层118外部的薄栅极导体117的一部分可经由RIE移除，或在替代性实施例中，自栅极叠层外部表面移除薄栅极导体117可能需要附加的湿法蚀刻操作。
多晶锗或另一合适的组成可用作多晶硅113的替代物。另外，任何多晶SiGe合金亦可用于替代多晶硅113。更进一步，多晶硅113能够以多晶形式沉积或以非晶形式沉积，该非晶形式当曝露于高温时随后转变成多晶硅。
尽管已结合示例性实施例描述本公开，但本领域技术人员应理解，在不脱离本公开的范围的情况下，可进行各种修改，并且其元件可由等价物替代。此外，在不脱离其基本范围的情况下，可进行诸多修改以使特定情况或材料适合于本公开的教导。因此，希望本公开不限于作为所预期用于实施本公开的最佳方式而揭示的特定示例性实施例，但本公开将包括落入所附权利要求的范围内的全部实施例。

Claims (15)

1.一种修改具有设置在绝缘体上的半导体的晶片的方法，所述方法包括以下步骤：
分别在第一和第二晶片区域处形成在每个端部处连接至半导体衬垫的第一和第二纳米线沟道，其中第二纳米线沟道侧壁比第一纳米线沟道侧壁相对于所述半导体的晶面更大程度地错位；以及
朝向所述第一和第二纳米线沟道的侧壁与所述晶面之间的对准状态从所述第一和第二纳米线沟道转移半导体材料，以使在所述转移之后所述第一和第二纳米线沟道之间的厚度差反映所述第二纳米线沟道侧壁的更大错位。
2.一种修改具有设置在绝缘体上的半导体的晶片的方法，所述方法包括以下步骤：
在所述晶片的第一区域中形成由纳米线沟道连接的半导体衬垫对，所述纳米线沟道具有沿所述半导体的{110}晶面定向的长轴以及基本上平行于所述半导体的{110}面中的一个的侧壁；
在所述晶片的第二区域中形成由纳米线沟道连接的半导体衬垫对，所述纳米线沟道具有相对于所述半导体的{110}面成一角度的长轴以及相似地相对于所述半导体的{110}面成角度的侧壁；以及
再定向所述第二区域的所述纳米线沟道，以通过将半导体材料从所述纳米线沟道扩散至所述衬垫，使得所述第二区域中的所述纳米线沟道与处于所述第一区域的纳米线沟道相比被减薄而形成平行于所述半导体的{110}面的侧壁。
3.根据权利要求1或2所述的方法，其中所述形成包括：形成彼此平行的所述第一区域的所述纳米线沟道，以及形成彼此平行的所述第二区域的所述纳米线沟道。
4.根据权利要求1或2所述的方法，其中所述第一纳米线沟道侧壁相对于所述晶面对准，且所述第二纳米线沟道侧壁相对于所述晶面错位。
5.根据权利要求1或2所述的方法，其中所述第一和第二纳米线沟道侧壁均相对于所述晶面错位。
6.根据权利要求1或2所述的方法，其中转移所述半导体材料包括退火。
7.根据权利要求1或2所述的方法，进一步包括将所述纳米线沟道再成形为纳米线。
8.根据权利要求7所述的方法，进一步包括环绕每个所述纳米线形成各栅极。
9.根据权利要求8所述的方法，其中所述栅极均包括电介质、薄栅极导体以及掺杂导电材料。
10.根据权利要求8所述的方法，其中所述纳米线均具有各自的驱动电流和/或阈值电压，所述驱动电流和/或阈值电压根据所述第一和第二纳米线的厚度之间的差异而不同。
11.根据权利要求1或2所述的方法，其中所述形成包括构图处理。
12.根据权利要求1所述的方法，其中第一纳米线沟道侧壁的特征在于具有相对于所述半导体的晶面的第一对准度，且第二纳米线沟道侧壁的特征在于具有相对于所述晶面的第二对准度，所述第二对准度不同于所述第一对准度。
13.一种晶片，其包括：
衬底；
掩埋氧化物(BOX)层，其设置在所述衬底上；以及
绝缘体上硅(SOI)结构，其设置在第一和第二区域处的所述BOX层上，在每个区域处的所述SOI结构具有通过在其中形成的各纳米线沟道连接的各SOI衬垫对，
处于所述区域中的一个的所述SOI衬垫和所述纳米线沟道比处于所述区域中的另一个的所述SOI衬垫和所述纳米线沟道相对于所述SOI的{110}面更加错位。
14.根据权利要求13所述的晶片，其中错位纳米线沟道的轮廓包括可从其形成的再成形纳米线。
15.根据权利要求13所述的晶片，其中所述纳米线沟道分别在所述第一和第二区域中的每一个处彼此平行。
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US20110278539A1 (en) 2011-11-17
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US8519479B2 (en) 2013-08-27
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