TW201209930A - Generation of multiple diameter nanowire field effect transistors - Google Patents

Abstract

A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.

Description

201209930 VI. Description of the Invention: [Technical Field of the Invention] The aspect of the present invention is directed to a method of producing multi-diameter nanowire field effect transistors (FETs). [Prior Art] As a choice of future complementary metal oxide semiconductor (CMOS) component designs, nanowire FETs are attracting considerable attention. Although progress is being made, a number of key issues remain to be considered. Among these problems, a particular problem is that the nanowire F E T component will be required to provide components having different drive current intensities and/or different threshold voltages (Vt). <Solutions for problems with components such as hurricane 5 worms and/or different threshold voltages, but such solutions typically rely on modulating the voltage between components by a corresponding modulating gate function (). Therefore, these solutions tend to have relatively difficult and costly process integration operations and, in addition, these solutions tend to present a change relationship. κ [Abstract] According to the invention, the present invention provides a method, a method of arranging a semiconductor-wafer disposed on an insulator, and the following steps: forming the ends to be respectively connected to The first and second nanowire channels of the semiconductor pads of the second and second layers of the 201209930, and the sidewalls of the second nanowire channel are opposite to the crystallographic plane of the semiconductor of the first nanowire channel (crystallographic The plane is more misaligned; and the semiconductor material is displaced from the first and second nanowire channels to an alignment condition between the sidewalls and the crystal face such that the displacement is after the The difference in thickness between the first and second nanowire channels reflects the larger misalignment of the sidewalls of the second nanowire channel. According to an aspect of the present invention, there is provided a method of modifying a wafer having a semiconductor disposed on an insulator, the method comprising the steps of: forming respective ends to be respectively connected to the first and second wafer regions First and second nanowire channels of the semiconductor pad, and the sidewalls of the first nanowire channel are characterized by a first alignment with respect to one of the crystal faces of the semiconductor; and the second nanowire channel is Characterizing the second alignment relative to one of the crystal faces, the second alignment being different from the first alignment; and encuring the semiconductor material from the first and first nanowire channels An alignment condition between the sidewalls and the crystallized surface is such that a difference in thickness between the first and second nanowire channels after the displacement is consistent with the first and second alignment degrees . According to an aspect of the present invention, there is provided a method of modifying a wafer having a semiconductor disposed on an insulator, the method comprising the steps of: forming a nanowire channel connection in a first region of the wafer a pair of semiconductor pads having a major axis oriented along a (110) crystal plane of the semiconductor and a sidewall substantially parallel to one of the 201209930 {110} faces of the semiconductor; Forming, in the second region of the wafer, a pair of semiconductor pads connected by a nanowire channel having a major axis at an angle relative to the {i 10} crystal faces of the semiconductor and the same relative Forming an angled sidewall on the {110} faces of the semiconductor; and reorienting the nanowire channels of the second region to form a semiconductor material from the nanowire channels to the pads Parallel to the sidewalls of the {丨丨0 } faces of the semiconductor such that the antenna line channels in the second region are thinned compared to the nanowire channels in the first region (thinned ). According to another aspect of the present invention, the present invention provides a wafer including a substrate, a buried oxide (BOX) layer disposed on the substrate, and a first layer disposed on the BOX layer And a silicon-on-insulator (SOI) structure at one of the second regions, the S 01 structures at each region having respective SOI pad pairs connected via respective nanowire channels formed therein, The SOI pads and the nanowire channels in one of the regions are opposite to the SOI pads and the nanowire channels of the other of the regions The {110} face is more misplaced. [Embodiment] Provided herein are structures for supporting, for example, gate-all-around (GAA) nanowire field effect transistors (FETs) and for fabrication via the description of germanium (Si) nanowires and Si processing. The method of the transistor. However, 6 201209930 the present technology can also be implemented by other semiconductor materials such as, for example, germanium (Ge). When the field uses a #Sl I conductor, the processing steps are similar and suitable for the particular semiconductor used. Therefore, the use of <semiconductor materials such as Si, SiGe, Si/SiGe, Sic or SiGeC is understood to be merely exemplary. The wafer i is provided with reference to Figs. 1 and 2, and includes a Si substrate ιοί, a buried oxide (Β〇χ) layer 1〇2, and an insulator overlying layer W3. Wafer 1 can be fabricated using methods such as oxygen injection isolation (IMplanted® Xygen; SIM〇x) or wafer bonding (eg, SmartCut). Such wafer fabrication techniques are known to those skilled in the art and are therefore not further described herein. Other SOI substrates known in the art may also be substituted for the SOI's described herein and which are within the teachings of the present teachings. The dome 1 has at least one of the first region 1〇 and the second region 20. The 801 pad (the 103~ pair and the nanowire channel 1〇4 connected thereto can be patterned to be in The first region 1 〇 and the second region 2 〇 〇 I layer 1 〇 3 to form, for example, a ladder structure in each region. The patterning of the nanowire channel and the SOI liner 103A can be via lithography ( For example, a beam of electron beams) and subsequent reactive ion etching (RIE) or via sidewall displacement techniques. Such patterning techniques are known to those skilled in the art. The two regions 2 〇 〇 I layer 1 〇 3 are initially formed by similar elements having similar thicknesses. However, as shown in the first and second figures, the s〇I pad i 〇 3A in the first region and Nano 201209930 line channel 104 is formed to have sidewalls that are substantially parallel to and/or aligned to one of the {110} crystal faces of, for example, a semiconductor, although other planar reference coordinate systems are possible, ie, nanowires The main (long) axis of each of the channels 丨04 is along the { ii 〇} crystal plane of the semiconductor Directional orientation. On the other hand, the SOI liner 103A and the nanowire channel 104 in the second region 20 are formed to have a side wall with an angle α with respect to the {11〇丨 crystal plane and/or with an angle α. The main (long) axis of the line channel 1 〇4 is also offset by an angle α with respect to the {110} crystal plane. For example, the nanowire channel 1 〇4 in the first region 10 can be patterned to have parallel The side wall of the face is parallel to the top surface of the {1〇〇} face, and the nanowire channel 104 in the second zone 2〇 will have an angle α with respect to the {丨丨〇) crystal face ( The side wall of the misalignment such as α = 1 degree and the top surface of the {1〇〇} plane. In the case where the nanowire channel 104 of the second region 20 is angled and/or misaligned, as described above, the thinning operation is performed on both the first region 10 and the second region (for example, the nanowire channel 丨〇4) The annealing) will tend to have a greater thinning effect at the first region 20 than at the first region 1〇. This condition is more sensitive to the effect of the thinning operation of the SOI layer 103 in the second region 20 than the SOI layer 103 in the first region 10 due to the offset of the SOI layer ι3 in the second region. The thinning operation tends to redirect the second region 2N of the nanowire channel 1〇4 to form a parallel to {1 1 by diffusing the semiconductor material from the nanowire channel 104 to the s〇I pad 1〇3A. 〇}The side wall of the crystal face. This has the effect that the nanowire channels 104 in the second region 2 Q become thinner after the reorientation than the channels of the first region 1〇. 201209930 4 - The degree to which SOI layer 1〇3 of region 20 is thinned beyond S〇I|103 of first region (7) can be controlled by increasing or decreasing the relative misalignment of the sidewalls of first region 1 and region 20 . For example, the sidewalls of the nanowire channel 1Q4 at the first region 10 may be aligned with respect to the {110} crystal plane of the semiconductor, or may be misaligned only by a small angle a. At the same time, the side wall of the nanowire channel 1〇4 of the first region 20 may be offset by a larger angle α.# with respect to the (no) crystal plane of the semiconductor. Here, the greater the relative misalignment of the sidewalls of the first region 10 and the second region 20, the greater the degree of thinning at the second region 20. Indeed, referring to Fig. 2, the angle α of the nanowire channel 104 relative to the {11〇} crystal plane may be less than 45. Any angle (and practically α does not exceed a few degrees)' condition is that the greater the slope of the angle, the thinner the resulting reshaped nanowire 108 will be. That is, the nanowire channel 1〇4 at a more oblique angle tends to form a thinner reshaped nanowire 108 than the more vertical nanowire channel 104. Therefore 'although the size and inclination of the nanowire channel 丨〇4 can vary depending on design considerations', the profile of the nanowire channel 1 should cover at least one of the reshaped nanowires 8 to be formed. profile. Among them, Shi Xi’s re-orientation treatment from the diffusion of the channel 104 in g.M.

Cohen et al., "Controlling the shape and dimensional variability of top-down fabricated silicon nanowires by hydrogen annealing" from San Francisco, CA (2010), Material Synthesis Symposium, which is incorporated by reference. This article. The specification of the direction of the crystal faces follows the provisions of the 201209930 Miller indices, which are described, for example, in Chapter 5 of Yang (4) and Mennin's Solid State Physics (1976), the contents of which are incorporated herein by reference. Following this rule, a family of crystal faces (i.e., planes equivalent to the symmetry of the crystal) is usually referenced by the pair of {} brackets. For example, the faces (_, (4)) and (10) are all equivalent in the cubic crystal. - The person is represented by {10〇}. When referring to the direction of the crystal t, use the [] square brackets, such as [100], [〇1〇], [〇〇1], [-100], [0-10], [0(M], and the same Ground, <1〇〇> represents a group of crystal orientations. Therefore, the nanowire channel 1〇4 in the second region 20 can be formed into a reshaped nanowire 108 (see Fig. 3). The formed nanowires 1〇8 are thinner than the nanowires of the first region 10, even though annealing is performed in a similar manner at each region. In detail, the first region 1〇 reshaped nanowire H) 8 will have a thickness Τι, and the reshaped nanowire 108 of the fourth domain 2q will have a thickness T2. The thickness T2. will be different from the thickness Tl. and is generally thinner than the thickness TV. Thus, such relative thickness differences in the reshaped nanowires 1〇8 at the first region 1〇 and the second region 2〇 will cause the reshaped nanowires 108 to exhibit physical properties that are unique to each other. The angle of the nanowire channel 104 can be achieved in different ways. For example, the lithography mask may include an as-drawn alignment pattern and a misalignment pattern for the region 1 and region 2, or during the (iv) period of the angled nanowire channel 1G4. The round or (iv) mask can be rotated relative to the (11〇) crystal plane. However, the angle of the nanowire through H04 does not need to be in any particular crystal plane' and the above (11 (^ crystal plane only understands 10 201209930 as an example) Referring to Figure 3, the recrystallization of the nanowire channel 1 〇4 to the nanowire 1 〇8 is usually achieved by annealing in an inert atmosphere. This treatment can be applied to the regions 10 and 20 simultaneously or sequentially. No mask treatment. For example, 'Wafer 1 can be annealed in an exemplary Hz atmosphere. So far before the annealing?', the raw oxide can be etched away from the sidewall of the nanowire channel 1 〇4 and the S0I liner 1〇3A. The annealing in H2 has several purposes including, but not limited to, smoothing the sidewalls of the nanowire channel 104, realigning the sidewalls to the crystal plane of the SOI liner 103A, and the nanowire channel 104 cross section. Reshaping from a rectangle to a more cylindrical shape and redistribution via si The nanowire channel 丨〇4 body is thinned. According to an exemplary embodiment, the inert gas annealing is performed under the following conditions: from about 30 Torr to about 1000 Torr, from about 600 degrees Celsius (°) 〇 to a temperature of about 1100 〇c and a duration of from about 1 minute to about 12 minutes. In general, the rate of 'S i redistribution increases with temperature and decreases with increasing pressure. As shown, the nanowire channel 1〇4 can be reshaped into a nanowire 108 and suspended on the BOX layer 102 or from the BOX layer 1 via the annealing process or further etching and recessing via the box layer i 〇2. 〇2 release. The reshaped nanowire 108 thus forms a suspended bridge between the first region 1〇 and the SOI liner 〇3〇 in the second region 2〇 and over the recessed oxide 1〇5 (suspended bridges) The depression of the BOX layer 1〇2 can be achieved by the annealing treatment, or by diluted hydrofluoric (DHF) etching to undercut the BOX layer 1〇2. The 201209930 tube SOI substrate is provided to define And a convenient way to suspend the nanowire channel 1〇4 and/or reshape the rice noodle 108, but it may be by other The substrate is suspended. For example, the (four) stacking of epitaxial growth on the bulk Si wafer may also be patterned to form a nanowire pass 1胄4 and/or a reshaped nanowire 1〇8. The SiGe layer can also be used as a sacrificial layer for undercutting (similar to the B0X layer 102). The reshaped nanowire 108 having the thickness TV in the first region 10 and the second region 2〇 having a thickness T2, The shaped nanowire ι 8 can have different drive currents and/or threshold voltages. In this way, it should be understood that at least the wafer can be controlled by the corresponding control portion determining the final thickness Τι, and h, which are at the angle of the first region ίο and the second region 20 of the nanowire channel 1〇4. Circuit characteristics of the first-region 10 and the second region 20 of 1. Referring to Figures 4 and 5, the gate structure 4〇2 can be formed around the reshaped non-rice line 108. f First, the first and third closed-cell dielectrics "Μ and 112 t overmolded nanowires 1〇8. The first (and optionally) closed-electrode dielectric 112A is usually Si〇2. The two-gate dielectric ι 2 may include yttrium oxide (Si〇2), yttrium oxynitride (Si〇N), cerium oxide (η(7)2) or any other suitable one or more high-k dielectrics, and for §1 〇2 and si〇N. It can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or an oxidizing furnace. Then, a thin gate conductor such as TaN $(4) can be formed. Shape deposition. This can be followed by deposition of doped polycrystalline dreams (1) to form a gate stack 118 around the perimeter of the reshaped nano, line 1 。 8. The mask 115 can be used to facilitate the closure of the via via RIE 12 201209930 • A portion of the thin gate conductor 117 outside of the gate stack 118 may be removed via RIE, or in an alternative embodiment, removing the thin gate conductor 117 from the outer surface of the gate stack may require additional Wet etching operation. Polycrystalline germanium or another suitable composition can be used as a substitute for polycrystalline germanium 13. In addition, any polycrystalline SiGe doping The material (aU〇y) can also be used in place of the polycrystalline stone 113. Further, the polycrystalline stone 113 can be deposited in a polycrystalline form or in an amorphous form which is subsequently converted to polycrystalline germanium when exposed to high temperatures. Although the present disclosure has been described in connection with the exemplary embodiments, those skilled in the art should understand that various modifications may be made and the elements may be replaced by equivalents without departing from the scope of the disclosure. Numerous modifications may be made to adapt a particular situation or material to the teachings of the present disclosure. It is therefore contemplated that the disclosure is not limited to the preferred embodiments disclosed. Specific exemplary embodiments, but the disclosure will include all embodiments falling within the scope of the appended claims. [Brief Description] The subject matter of the present invention is considered to be the subject matter of the present application. The foregoing and other aspects, features, and advantages of the present invention will be It is obvious that: Figure 1 is a perspective view of the wafer of Figure 1 with the nanometer 13 201209930 line channel defined on the first and second regions; Figure 2 is the first nanometer. A plan view of the dimensions of the line channel; Figure 3 is a perspective view of the wafer having the second figure of the reshaped nanowire defined thereon; and Figure 4 is a perspective view of the reshaped nanowire with the gate structure And, Fig. 5 includes a cross-sectional view of a nanowire having different thicknesses. [Main component symbol description] 1 Wafer 20 Second region 102 Buried oxide layer 103A SOI lining 105 Oxide 112 Second gate dielectric Electrical 113 Polycrystalline 117 Thin Gate Conductor 402 Gate Structure 厚度 Thickness 10 First Area 101 Si Substrate 103 Insulator Overlying Layer 104 Nea Line Channel 108 Reshaped Nanowire 112A First Gate Dielectric 115 Mask 118 gate stack α angle τ2· thickness

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Claims (1)

201209930 VII. Patent Application Range: 1 · A method for modifying a wafer having a semiconductor disposed on an insulator, the method comprising the steps of: forming a semiconductor connected at each end to the first and second wafer regions The first and second nanowire channels of the liner, and the sidewalls of the second nanowire channel are misaligned to a greater extent than the crystalline side of the first nanowire channel; and The first and second nanowire channels of the Xuanzang displace the semiconductor material toward an alignment condition between the sidewall and the crystal plane such that the thickness difference between the first and second nanowire channels after the displacement Reflecting the larger misalignment of the sidewalls of the second nanowire channels. 2. A method of modifying a wafer having a semiconductor disposed on an insulator, the method comprising the steps of: forming a semiconductor profile connected by a nanowire channel in a first region of the wafer The nanowire channel has its major axis oriented along the {110} crystal planes of the semiconductor, and a sidewall substantially parallel to one of the {11 0 } faces of the semiconductor; Forming, in a second region, a semiconductor profile connected by a nanowire vial to the long axis of the nanochannel channel having an angle with respect to the {110} crystal faces of the semiconductor, and also relative to the The {11 〇} faces of the semiconductor are angled sidewalls; and the nanowire channels of the second region are reoriented to diffuse the semi-201209930 conductor material from the nanowire channels to the lining Forming a sidewall parallel to the {1 1 〇} faces of the semiconductor such that the nanowire channels in the second region are thinned compared to the nanowire channels in the first region . 3. The method of claim 1 or claim 2, wherein the step of forming comprises the steps of: forming the nanowire channels of the first region parallel to each other, and forming the second regions parallel to each other These nanowire channels. 4. The method of claim 1 or claim 2, wherein the first nanowire channel sidewalls are aligned with respect to the crystal face and the second nanowire channel sidewalls are misaligned relative to the crystal face. 5. The method of claim 2, wherein the sidewalls of the first and second nanowire channels are offset relative to the crystal plane. 6. The step of the displacement of the semiconductor material, as recited in claim 1 or claim ^2, comprises annealing. 7. The claim 1 or the request step: the method of the above item 2, which is reshaped into a nanowire in a line channel. The step includes the following steps: Surrounding as described in claim 7, which proceeds to a 16 201209930 each of the nanowires forms a respective gate. 9. The method of claim 8, wherein the gates of the 辇胡~A τ bian temple each comprise a dielectric material, a thin gate conductor, and a doped conductive material. 1 0. If the request item 8 is ... 丨 丨 咏 咏 卉 卉 卉 卉 卉 卉 卉 卉 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , These differences between thicknesses are the same. The step of forming π. The method of claim 1 or claim 2 includes a patterning process. 12. As requested! The method 'where the sidewall of the first nanowire channel is characterized by a first alignment with respect to one of the crystal faces of the semiconductor, and the sidewall of the second nanowire channel is second with respect to one of the crystal faces The alignment is characterized by a second alignment that is different from the first alignment. 1 3 - a wafer comprising: a substrate; a buried oxide (BOX) layer disposed on the substrate; and an insulator overlying (SOI) structure disposed on the BOX layer At the first and second regions, the s〇I structure at each region has respective S 〇 1 pad pairs connected via respective nanowire channels formed by t, 17 201209930 being in the regions The SOI pads and the other nanowire channels are more misaligned relative to the {110} plane of the SOI than the other of the SOI pads in the other regions. The wafer of claim 13 wherein a contour of the misaligned nanowire channels encompasses one of the reshaped nanowires from which it can be formed. 1 5 - The wafer of claim 13 wherein the nanowire channels are parallel to each other in each of the first and second regions. 18